git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3/port.c

   1 /*\r
   2     FreeRTOS V8.1.0 - Copyright (C) 2014 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     ***************************************************************************\r
   8      *                                                                       *\r
   9      *    FreeRTOS provides completely free yet professionally developed,    *\r
  10      *    robust, strictly quality controlled, supported, and cross          *\r
  11      *    platform software that has become a de facto standard.             *\r
  12      *                                                                       *\r
  13      *    Help yourself get started quickly and support the FreeRTOS         *\r
  14      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  15      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  16      *                                                                       *\r
  17      *    Thank you!                                                         *\r
  18      *                                                                       *\r
  19     ***************************************************************************\r
  20 \r
  21     This file is part of the FreeRTOS distribution.\r
  22 \r
  23     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  24     the terms of the GNU General Public License (version 2) as published by the\r
  25     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  26 \r
  27     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  28     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  29     >>!   obliged to provide the source code for proprietary components     !<<\r
  30     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  31 \r
  32     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  33     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  34     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  35     link: http://www.freertos.org/a00114.html\r
  36 \r
  37     1 tab == 4 spaces!\r
  38 \r
  39     ***************************************************************************\r
  40      *                                                                       *\r
  41      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  42      *    not run, what could be wrong?"                                     *\r
  43      *                                                                       *\r
  44      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  45      *                                                                       *\r
  46     ***************************************************************************\r
  47 \r
  48     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  49     license and Real Time Engineers Ltd. contact details.\r
  50 \r
  51     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  52     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  53     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  54 \r
  55     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  56     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  57     licenses offer ticketed support, indemnification and middleware.\r
  58 \r
  59     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  60     engineered and independently SIL3 certified version for use in safety and\r
  61     mission critical applications that require provable dependability.\r
  62 \r
  63     1 tab == 4 spaces!\r
  64 */\r
  65 \r
  66 /*-----------------------------------------------------------\r
  67  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  68  *----------------------------------------------------------*/\r
  69 \r
  70 /* Scheduler includes. */\r
  71 #include "FreeRTOS.h"\r
  72 #include "task.h"\r
  73 \r
  74 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\r
  75 defined.  The value should also ensure backward compatibility.\r
  76 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */\r
  77 #ifndef configKERNEL_INTERRUPT_PRIORITY\r
  78         #define configKERNEL_INTERRUPT_PRIORITY 255\r
  79 #endif\r
  80 \r
  81 #ifndef configSYSTICK_CLOCK_HZ\r
  82         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  83         /* Ensure the SysTick is clocked at the same frequency as the core. */\r
  84         #define portNVIC_SYSTICK_CLK_BIT        ( 1UL << 2UL )\r
  85 #else\r
  86         /* The way the SysTick is clocked is not modified in case it is not the same\r
  87         as the core. */\r
  88         #define portNVIC_SYSTICK_CLK_BIT        ( 0 )\r
  89 #endif\r
  90 \r
  91 /* Constants required to manipulate the core.  Registers first... */\r
  92 #define portNVIC_SYSTICK_CTRL_REG                       ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
  93 #define portNVIC_SYSTICK_LOAD_REG                       ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
  94 #define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
  95 #define portNVIC_SYSPRI2_REG                            ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
  96 /* ...then bits in the registers. */\r
  97 #define portNVIC_SYSTICK_INT_BIT                        ( 1UL << 1UL )\r
  98 #define portNVIC_SYSTICK_ENABLE_BIT                     ( 1UL << 0UL )\r
  99 #define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )\r
 100 #define portNVIC_PENDSVCLEAR_BIT                        ( 1UL << 27UL )\r
 101 #define portNVIC_PEND_SYSTICK_CLEAR_BIT         ( 1UL << 25UL )\r
 102 \r
 103 #define portNVIC_PENDSV_PRI                                     ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 104 #define portNVIC_SYSTICK_PRI                            ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 105 \r
 106 /* Constants required to check the validity of an interrupt priority. */\r
 107 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
 108 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
 109 #define portAIRCR_REG                                           ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
 110 #define portMAX_8_BIT_VALUE                                     ( ( uint8_t ) 0xff )\r
 111 #define portTOP_BIT_OF_BYTE                                     ( ( uint8_t ) 0x80 )\r
 112 #define portMAX_PRIGROUP_BITS                           ( ( uint8_t ) 7 )\r
 113 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
 114 #define portPRIGROUP_SHIFT                                      ( 8UL )\r
 115 \r
 116 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\r
 117 #define portVECTACTIVE_MASK                                     ( 0x1FUL )\r
 118 \r
 119 /* Constants required to set up the initial stack. */\r
 120 #define portINITIAL_XPSR                                        ( 0x01000000UL )\r
 121 \r
 122 /* The systick is a 24-bit counter. */\r
 123 #define portMAX_24_BIT_NUMBER                           ( 0xffffffUL )\r
 124 \r
 125 /* A fiddle factor to estimate the number of SysTick counts that would have\r
 126 occurred while the SysTick counter is stopped during tickless idle\r
 127 calculations. */\r
 128 #define portMISSED_COUNTS_FACTOR                        ( 45UL )\r
 129 \r
 130 /* Let the user override the pre-loading of the initial LR with the address of\r
 131 prvTaskExitError() in case is messes up unwinding of the stack in the\r
 132 debugger. */\r
 133 #ifdef configTASK_RETURN_ADDRESS\r
 134         #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
 135 #else\r
 136         #define portTASK_RETURN_ADDRESS prvTaskExitError\r
 137 #endif\r
 138 \r
 139 /* Each task maintains its own interrupt status in the critical nesting\r
 140 variable. */\r
 141 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
 142 \r
 143 /*\r
 144  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 145  * file is weak to allow application writers to change the timer used to\r
 146  * generate the tick interrupt.\r
 147  */\r
 148 void vPortSetupTimerInterrupt( void );\r
 149 \r
 150 /*\r
 151  * Exception handlers.\r
 152  */\r
 153 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 154 void xPortSysTickHandler( void );\r
 155 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 156 \r
 157 /*\r
 158  * Start first task is a separate function so it can be tested in isolation.\r
 159  */\r
 160 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
 161 \r
 162 /*\r
 163  * Used to catch tasks that attempt to return from their implementing function.\r
 164  */\r
 165 static void prvTaskExitError( void );\r
 166 \r
 167 /*-----------------------------------------------------------*/\r
 168 \r
 169 /*\r
 170  * The number of SysTick increments that make up one tick period.\r
 171  */\r
 172 #if configUSE_TICKLESS_IDLE == 1\r
 173         static uint32_t ulTimerCountsForOneTick = 0;\r
 174 #endif /* configUSE_TICKLESS_IDLE */\r
 175 \r
 176 /*\r
 177  * The maximum number of tick periods that can be suppressed is limited by the\r
 178  * 24 bit resolution of the SysTick timer.\r
 179  */\r
 180 #if configUSE_TICKLESS_IDLE == 1\r
 181         static uint32_t xMaximumPossibleSuppressedTicks = 0;\r
 182 #endif /* configUSE_TICKLESS_IDLE */\r
 183 \r
 184 /*\r
 185  * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
 186  * power functionality only.\r
 187  */\r
 188 #if configUSE_TICKLESS_IDLE == 1\r
 189         static uint32_t ulStoppedTimerCompensation = 0;\r
 190 #endif /* configUSE_TICKLESS_IDLE */\r
 191 \r
 192 /*\r
 193  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
 194  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 195  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 196  */\r
 197 #if ( configASSERT_DEFINED == 1 )\r
 198          static uint8_t ucMaxSysCallPriority = 0;\r
 199          static uint32_t ulMaxPRIGROUPValue = 0;\r
 200          static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 201 #endif /* configASSERT_DEFINED */\r
 202 \r
 203 /*-----------------------------------------------------------*/\r
 204 \r
 205 /*\r
 206  * See header file for description.\r
 207  */\r
 208 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
 209 {\r
 210         /* Simulate the stack frame as it would be created by a context switch\r
 211         interrupt. */\r
 212         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 213         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 214         pxTopOfStack--;\r
 215         *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
 216         pxTopOfStack--;\r
 217         *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;        /* LR */\r
 218         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 219         *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
 220         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 221 \r
 222         return pxTopOfStack;\r
 223 }\r
 224 /*-----------------------------------------------------------*/\r
 225 \r
 226 static void prvTaskExitError( void )\r
 227 {\r
 228         /* A function that implements a task must not exit or attempt to return to\r
 229         its caller as there is nothing to return to.  If a task wants to exit it\r
 230         should instead call vTaskDelete( NULL ).\r
 231 \r
 232         Artificially force an assert() to be triggered if configASSERT() is\r
 233         defined, then stop here so application writers can catch the error. */\r
 234         configASSERT( uxCriticalNesting == ~0UL );\r
 235         portDISABLE_INTERRUPTS();\r
 236         for( ;; );\r
 237 }\r
 238 /*-----------------------------------------------------------*/\r
 239 \r
 240 void vPortSVCHandler( void )\r
 241 {\r
 242         __asm volatile (\r
 243                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 244                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 245                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 246                                         "       ldmia r0!, {r4-r11}                             \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 247                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 248                                         "       isb                                                             \n"\r
 249                                         "       mov r0, #0                                              \n"\r
 250                                         "       msr     basepri, r0                                     \n"\r
 251                                         "       orr r14, #0xd                                   \n"\r
 252                                         "       bx r14                                                  \n"\r
 253                                         "                                                                       \n"\r
 254                                         "       .align 2                                                \n"\r
 255                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 256                                 );\r
 257 }\r
 258 /*-----------------------------------------------------------*/\r
 259 \r
 260 static void prvPortStartFirstTask( void )\r
 261 {\r
 262         __asm volatile(\r
 263                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 264                                         " ldr r0, [r0]                  \n"\r
 265                                         " ldr r0, [r0]                  \n"\r
 266                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 267                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 268                                         " cpsie f                               \n"\r
 269                                         " dsb                                   \n"\r
 270                                         " isb                                   \n"\r
 271                                         " svc 0                                 \n" /* System call to start first task. */\r
 272                                         " nop                                   \n"\r
 273                                 );\r
 274 }\r
 275 /*-----------------------------------------------------------*/\r
 276 \r
 277 /*\r
 278  * See header file for description.\r
 279  */\r
 280 BaseType_t xPortStartScheduler( void )\r
 281 {\r
 282         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
 283         See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 284         configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
 285 \r
 286         #if( configASSERT_DEFINED == 1 )\r
 287         {\r
 288                 volatile uint32_t ulOriginalPriority;\r
 289                 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 290                 volatile uint8_t ucMaxPriorityValue;\r
 291 \r
 292                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 293                 functions can be called.  ISR safe functions are those that end in\r
 294                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 295                 ensure interrupt entry is as fast and simple as possible.\r
 296 \r
 297                 Save the interrupt priority value that is about to be clobbered. */\r
 298                 ulOriginalPriority = *pucFirstUserPriorityRegister;\r
 299 \r
 300                 /* Determine the number of priority bits available.  First write to all\r
 301                 possible bits. */\r
 302                 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
 303 \r
 304                 /* Read the value back to see how many bits stuck. */\r
 305                 ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
 306 \r
 307                 /* Use the same mask on the maximum system call priority. */\r
 308                 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
 309 \r
 310                 /* Calculate the maximum acceptable priority group value for the number\r
 311                 of bits read back. */\r
 312                 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
 313                 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
 314                 {\r
 315                         ulMaxPRIGROUPValue--;\r
 316                         ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
 317                 }\r
 318 \r
 319                 /* Shift the priority group value back to its position within the AIRCR\r
 320                 register. */\r
 321                 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
 322                 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
 323 \r
 324                 /* Restore the clobbered interrupt priority register to its original\r
 325                 value. */\r
 326                 *pucFirstUserPriorityRegister = ulOriginalPriority;\r
 327         }\r
 328         #endif /* conifgASSERT_DEFINED */\r
 329 \r
 330         /* Make PendSV and SysTick the lowest priority interrupts. */\r
 331         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 332         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 333 \r
 334         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 335         here already. */\r
 336         vPortSetupTimerInterrupt();\r
 337 \r
 338         /* Initialise the critical nesting count ready for the first task. */\r
 339         uxCriticalNesting = 0;\r
 340 \r
 341         /* Start the first task. */\r
 342         prvPortStartFirstTask();\r
 343 \r
 344         /* Should never get here as the tasks will now be executing!  Call the task\r
 345         exit error function to prevent compiler warnings about a static function\r
 346         not being called in the case that the application writer overrides this\r
 347         functionality by defining configTASK_RETURN_ADDRESS. */\r
 348         prvTaskExitError();\r
 349 \r
 350         /* Should not get here! */\r
 351         return 0;\r
 352 }\r
 353 /*-----------------------------------------------------------*/\r
 354 \r
 355 void vPortEndScheduler( void )\r
 356 {\r
 357         /* Not implemented in ports where there is nothing to return to.\r
 358         Artificially force an assert. */\r
 359         configASSERT( uxCriticalNesting == 1000UL );\r
 360 }\r
 361 /*-----------------------------------------------------------*/\r
 362 \r
 363 void vPortYield( void )\r
 364 {\r
 365         /* Set a PendSV to request a context switch. */\r
 366         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 367 \r
 368         /* Barriers are normally not required but do ensure the code is completely\r
 369         within the specified behaviour for the architecture. */\r
 370         __asm volatile( "dsb" );\r
 371         __asm volatile( "isb" );\r
 372 }\r
 373 /*-----------------------------------------------------------*/\r
 374 \r
 375 void vPortEnterCritical( void )\r
 376 {\r
 377         portDISABLE_INTERRUPTS();\r
 378         uxCriticalNesting++;\r
 379         __asm volatile( "dsb" );\r
 380         __asm volatile( "isb" );\r
 381         \r
 382         /* This is not the interrupt safe version of the enter critical function so\r
 383         assert() if it is being called from an interrupt context.  Only API \r
 384         functions that end in "FromISR" can be used in an interrupt.  Only assert if\r
 385         the critical nesting count is 1 to protect against recursive calls if the\r
 386         assert function also uses a critical section. */\r
 387         if( uxCriticalNesting == 1 )\r
 388         {\r
 389                 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\r
 390         }\r
 391 }\r
 392 /*-----------------------------------------------------------*/\r
 393 \r
 394 void vPortExitCritical( void )\r
 395 {\r
 396         configASSERT( uxCriticalNesting );\r
 397         uxCriticalNesting--;\r
 398         if( uxCriticalNesting == 0 )\r
 399         {\r
 400                 portENABLE_INTERRUPTS();\r
 401         }\r
 402 }\r
 403 /*-----------------------------------------------------------*/\r
 404 \r
 405 __attribute__(( naked )) uint32_t ulPortSetInterruptMask( void )\r
 406 {\r
 407         __asm volatile                                                                                                          \\r
 408         (                                                                                                                                       \\r
 409                 "       mrs r0, basepri                                                                                 \n" \\r
 410                 "       mov r1, %0                                                                                              \n"     \\r
 411                 "       msr basepri, r1                                                                                 \n" \\r
 412                 "       bx lr                                                                                                   \n" \\r
 413                 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1"    \\r
 414         );\r
 415 \r
 416         /* This return will not be reached but is necessary to prevent compiler\r
 417         warnings. */\r
 418         return 0;\r
 419 }\r
 420 /*-----------------------------------------------------------*/\r
 421 \r
 422 __attribute__(( naked )) void vPortClearInterruptMask( uint32_t ulNewMaskValue )\r
 423 {\r
 424         __asm volatile                                                                                                  \\r
 425         (                                                                                                                               \\r
 426                 "       msr basepri, r0                                                                         \n"     \\r
 427                 "       bx lr                                                                                           \n" \\r
 428                 :::"r0"                                                                                                         \\r
 429         );\r
 430 \r
 431         /* Just to avoid compiler warnings. */\r
 432         ( void ) ulNewMaskValue;\r
 433 }\r
 434 /*-----------------------------------------------------------*/\r
 435 \r
 436 void xPortPendSVHandler( void )\r
 437 {\r
 438         /* This is a naked function. */\r
 439 \r
 440         __asm volatile\r
 441         (\r
 442         "       mrs r0, psp                                                     \n"\r
 443         "       isb                                                                     \n"\r
 444         "                                                                               \n"\r
 445         "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 446         "       ldr     r2, [r3]                                                \n"\r
 447         "                                                                               \n"\r
 448         "       stmdb r0!, {r4-r11}                                     \n" /* Save the remaining registers. */\r
 449         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 450         "                                                                               \n"\r
 451         "       stmdb sp!, {r3, r14}                            \n"\r
 452         "       mov r0, %0                                                      \n"\r
 453         "       msr basepri, r0                                         \n"\r
 454         "       bl vTaskSwitchContext                           \n"\r
 455         "       mov r0, #0                                                      \n"\r
 456         "       msr basepri, r0                                         \n"\r
 457         "       ldmia sp!, {r3, r14}                            \n"\r
 458         "                                                                               \n"     /* Restore the context, including the critical nesting count. */\r
 459         "       ldr r1, [r3]                                            \n"\r
 460         "       ldr r0, [r1]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 461         "       ldmia r0!, {r4-r11}                                     \n" /* Pop the registers. */\r
 462         "       msr psp, r0                                                     \n"\r
 463         "       isb                                                                     \n"\r
 464         "       bx r14                                                          \n"\r
 465         "                                                                               \n"\r
 466         "       .align 2                                                        \n"\r
 467         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 468         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 469         );\r
 470 }\r
 471 /*-----------------------------------------------------------*/\r
 472 \r
 473 void xPortSysTickHandler( void )\r
 474 {\r
 475         /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
 476         executes all interrupts must be unmasked.  There is therefore no need to\r
 477         save and then restore the interrupt mask value as its value is already\r
 478         known. */\r
 479         ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
 480         {\r
 481                 /* Increment the RTOS tick. */\r
 482                 if( xTaskIncrementTick() != pdFALSE )\r
 483                 {\r
 484                         /* A context switch is required.  Context switching is performed in\r
 485                         the PendSV interrupt.  Pend the PendSV interrupt. */\r
 486                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 487                 }\r
 488         }\r
 489         portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
 490 }\r
 491 /*-----------------------------------------------------------*/\r
 492 \r
 493 #if configUSE_TICKLESS_IDLE == 1\r
 494 \r
 495         __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\r
 496         {\r
 497         uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;\r
 498         TickType_t xModifiableIdleTime;\r
 499 \r
 500                 /* Make sure the SysTick reload value does not overflow the counter. */\r
 501                 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
 502                 {\r
 503                         xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
 504                 }\r
 505 \r
 506                 /* Stop the SysTick momentarily.  The time the SysTick is stopped for\r
 507                 is accounted for as best it can be, but using the tickless mode will\r
 508                 inevitably result in some tiny drift of the time maintained by the\r
 509                 kernel with respect to calendar time. */\r
 510                 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;\r
 511 \r
 512                 /* Calculate the reload value required to wait xExpectedIdleTime\r
 513                 tick periods.  -1 is used because this code will execute part way\r
 514                 through one of the tick periods. */\r
 515                 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
 516                 if( ulReloadValue > ulStoppedTimerCompensation )\r
 517                 {\r
 518                         ulReloadValue -= ulStoppedTimerCompensation;\r
 519                 }\r
 520 \r
 521                 /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
 522                 method as that will mask interrupts that should exit sleep mode. */\r
 523                 __asm volatile( "cpsid i" );\r
 524 \r
 525                 /* If a context switch is pending or a task is waiting for the scheduler\r
 526                 to be unsuspended then abandon the low power entry. */\r
 527                 if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
 528                 {\r
 529                         /* Restart from whatever is left in the count register to complete\r
 530                         this tick period. */\r
 531                         portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 532 \r
 533                         /* Restart SysTick. */\r
 534                         portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
 535 \r
 536                         /* Reset the reload register to the value required for normal tick\r
 537                         periods. */\r
 538                         portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 539 \r
 540                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 541                         above. */\r
 542                         __asm volatile( "cpsie i" );\r
 543                 }\r
 544                 else\r
 545                 {\r
 546                         /* Set the new reload value. */\r
 547                         portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
 548 \r
 549                         /* Clear the SysTick count flag and set the count value back to\r
 550                         zero. */\r
 551                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 552 \r
 553                         /* Restart SysTick. */\r
 554                         portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
 555 \r
 556                         /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\r
 557                         set its parameter to 0 to indicate that its implementation contains\r
 558                         its own wait for interrupt or wait for event instruction, and so wfi\r
 559                         should not be executed again.  However, the original expected idle\r
 560                         time variable must remain unmodified, so a copy is taken. */\r
 561                         xModifiableIdleTime = xExpectedIdleTime;\r
 562                         configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
 563                         if( xModifiableIdleTime > 0 )\r
 564                         {\r
 565                                 __asm volatile( "dsb" );\r
 566                                 __asm volatile( "wfi" );\r
 567                                 __asm volatile( "isb" );\r
 568                         }\r
 569                         configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 570 \r
 571                         /* Stop SysTick.  Again, the time the SysTick is stopped for is\r
 572                         accounted for as best it can be, but using the tickless mode will\r
 573                         inevitably result in some tiny drift of the time maintained by the\r
 574                         kernel with respect to calendar time. */\r
 575                         ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;\r
 576                         portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );\r
 577 \r
 578                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 579                         above. */\r
 580                         __asm volatile( "cpsie i" );\r
 581 \r
 582                         if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
 583                         {\r
 584                                 uint32_t ulCalculatedLoadValue;\r
 585 \r
 586                                 /* The tick interrupt has already executed, and the SysTick\r
 587                                 count reloaded with ulReloadValue.  Reset the\r
 588                                 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
 589                                 period. */\r
 590                                 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 591 \r
 592                                 /* Don't allow a tiny value, or values that have somehow\r
 593                                 underflowed because the post sleep hook did something\r
 594                                 that took too long. */\r
 595                                 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\r
 596                                 {\r
 597                                         ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\r
 598                                 }\r
 599 \r
 600                                 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\r
 601 \r
 602                                 /* The tick interrupt handler will already have pended the tick\r
 603                                 processing in the kernel.  As the pending tick will be\r
 604                                 processed as soon as this function exits, the tick value\r
 605                                 maintained by the tick is stepped forward by one less than the\r
 606                                 time spent waiting. */\r
 607                                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
 608                         }\r
 609                         else\r
 610                         {\r
 611                                 /* Something other than the tick interrupt ended the sleep.\r
 612                                 Work out how long the sleep lasted rounded to complete tick\r
 613                                 periods (not the ulReload value which accounted for part\r
 614                                 ticks). */\r
 615                                 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 616 \r
 617                                 /* How many complete tick periods passed while the processor\r
 618                                 was waiting? */\r
 619                                 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
 620 \r
 621                                 /* The reload value is set to whatever fraction of a single tick\r
 622                                 period remains. */\r
 623                                 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
 624                         }\r
 625 \r
 626                         /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
 627                         again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
 628                         value.  The critical section is used to ensure the tick interrupt\r
 629                         can only execute once in the case that the reload register is near\r
 630                         zero. */\r
 631                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 632                         portENTER_CRITICAL();\r
 633                         {\r
 634                                 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\r
 635                                 vTaskStepTick( ulCompleteTickPeriods );\r
 636                                 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 637                         }\r
 638                         portEXIT_CRITICAL();\r
 639                 }\r
 640         }\r
 641 \r
 642 #endif /* #if configUSE_TICKLESS_IDLE */\r
 643 /*-----------------------------------------------------------*/\r
 644 \r
 645 /*\r
 646  * Setup the systick timer to generate the tick interrupts at the required\r
 647  * frequency.\r
 648  */\r
 649 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 650 {\r
 651         /* Calculate the constants required to configure the tick interrupt. */\r
 652         #if configUSE_TICKLESS_IDLE == 1\r
 653         {\r
 654                 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
 655                 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
 656                 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
 657         }\r
 658         #endif /* configUSE_TICKLESS_IDLE */\r
 659 \r
 660         /* Configure SysTick to interrupt at the requested rate. */\r
 661         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 662         portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\r
 663 }\r
 664 /*-----------------------------------------------------------*/\r
 665 \r
 666 #if( configASSERT_DEFINED == 1 )\r
 667 \r
 668         void vPortValidateInterruptPriority( void )\r
 669         {\r
 670         uint32_t ulCurrentInterrupt;\r
 671         uint8_t ucCurrentPriority;\r
 672 \r
 673                 /* Obtain the number of the currently executing interrupt. */\r
 674                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
 675 \r
 676                 /* Is the interrupt number a user defined interrupt? */\r
 677                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 678                 {\r
 679                         /* Look up the interrupt's priority. */\r
 680                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 681 \r
 682                         /* The following assertion will fail if a service routine (ISR) for\r
 683                         an interrupt that has been assigned a priority above\r
 684                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 685                         function.  ISR safe FreeRTOS API functions must *only* be called\r
 686                         from interrupts that have been assigned a priority at or below\r
 687                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 688 \r
 689                         Numerically low interrupt priority numbers represent logically high\r
 690                         interrupt priorities, therefore the priority of the interrupt must\r
 691                         be set to a value equal to or numerically *higher* than\r
 692                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 693 \r
 694                         Interrupts that use the FreeRTOS API must not be left at their\r
 695                         default priority of     zero as that is the highest possible priority,\r
 696                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
 697                         and     therefore also guaranteed to be invalid.\r
 698 \r
 699                         FreeRTOS maintains separate thread and ISR API functions to ensure\r
 700                         interrupt entry is as fast and simple as possible.\r
 701 \r
 702                         The following links provide detailed information:\r
 703                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 704                         http://www.freertos.org/FAQHelp.html */\r
 705                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 706                 }\r
 707 \r
 708                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits\r
 709                 that define each interrupt's priority to be split between bits that\r
 710                 define the interrupt's pre-emption priority bits and bits that define\r
 711                 the interrupt's sub-priority.  For simplicity all bits must be defined\r
 712                 to be pre-emption priority bits.  The following assertion will fail if\r
 713                 this is not the case (if some bits represent a sub-priority).\r
 714 \r
 715                 If the application only uses CMSIS libraries for interrupt\r
 716                 configuration then the correct setting can be achieved on all Cortex-M\r
 717                 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
 718                 scheduler.  Note however that some vendor specific peripheral libraries\r
 719                 assume a non-zero priority group setting, in which cases using a value\r
 720                 of zero will result in unpredicable behaviour. */\r
 721                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
 722         }\r
 723 \r
 724 #endif /* configASSERT_DEFINED */\r
 725 \r
 726 \r
 727 \r
 728 \r
 729 \r
 730 \r
 731 \r
 732 \r
 733 \r
 734 \r
 735 \r
 736 \r
 737 \r
 738 \r
 739 \r
 740 \r
 741 \r
 742 \r
 743 \r
 744 \r
 745 \r