2 FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd.
\r
5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
7 This file is part of the FreeRTOS distribution.
\r
9 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
10 the terms of the GNU General Public License (version 2) as published by the
\r
11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
\r
13 ***************************************************************************
\r
14 >>! NOTE: The modification to the GPL is included to allow you to !<<
\r
15 >>! distribute a combined work that includes FreeRTOS without being !<<
\r
16 >>! obliged to provide the source code for proprietary components !<<
\r
17 >>! outside of the FreeRTOS kernel. !<<
\r
18 ***************************************************************************
\r
20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
\r
23 link: http://www.freertos.org/a00114.html
\r
25 ***************************************************************************
\r
27 * FreeRTOS provides completely free yet professionally developed, *
\r
28 * robust, strictly quality controlled, supported, and cross *
\r
29 * platform software that is more than just the market leader, it *
\r
30 * is the industry's de facto standard. *
\r
32 * Help yourself get started quickly while simultaneously helping *
\r
33 * to support the FreeRTOS project by purchasing a FreeRTOS *
\r
34 * tutorial book, reference manual, or both: *
\r
35 * http://www.FreeRTOS.org/Documentation *
\r
37 ***************************************************************************
\r
39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
\r
40 the FAQ page "My application does not run, what could be wrong?". Have you
\r
41 defined configASSERT()?
\r
43 http://www.FreeRTOS.org/support - In return for receiving this top quality
\r
44 embedded software for free we request you assist our global community by
\r
45 participating in the support forum.
\r
47 http://www.FreeRTOS.org/training - Investing in training allows your team to
\r
48 be as productive as possible as early as possible. Now you can receive
\r
49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
\r
50 Ltd, and the world's leading authority on the world's leading RTOS.
\r
52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
\r
57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
\r
59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
\r
60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
61 licenses offer ticketed support, indemnification and commercial middleware.
\r
63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
64 engineered and independently SIL3 certified version for use in safety and
\r
65 mission critical applications that require provable dependability.
\r
70 /*-----------------------------------------------------------
\r
71 * Implementation of functions defined in portable.h for the ARM CM3 port.
\r
72 *----------------------------------------------------------*/
\r
74 /* Scheduler includes. */
\r
75 #include "FreeRTOS.h"
\r
78 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
\r
79 defined. The value should also ensure backward compatibility.
\r
80 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
\r
81 #ifndef configKERNEL_INTERRUPT_PRIORITY
\r
82 #define configKERNEL_INTERRUPT_PRIORITY 255
\r
85 #ifndef configSYSTICK_CLOCK_HZ
\r
86 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
\r
87 /* Ensure the SysTick is clocked at the same frequency as the core. */
\r
88 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
\r
90 /* The way the SysTick is clocked is not modified in case it is not the same
\r
92 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
\r
95 /* Constants required to manipulate the core. Registers first... */
\r
96 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
\r
97 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
\r
98 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
\r
99 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
\r
100 /* ...then bits in the registers. */
\r
101 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
\r
102 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
\r
103 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
\r
104 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
\r
105 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
\r
107 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
\r
108 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
\r
110 /* Constants required to check the validity of an interrupt priority. */
\r
111 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
\r
112 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
\r
113 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
\r
114 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
\r
115 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
\r
116 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
\r
117 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
\r
118 #define portPRIGROUP_SHIFT ( 8UL )
\r
120 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
\r
121 #define portVECTACTIVE_MASK ( 0xFFUL )
\r
123 /* Constants required to set up the initial stack. */
\r
124 #define portINITIAL_XPSR ( 0x01000000UL )
\r
126 /* The systick is a 24-bit counter. */
\r
127 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
\r
129 /* A fiddle factor to estimate the number of SysTick counts that would have
\r
130 occurred while the SysTick counter is stopped during tickless idle
\r
132 #define portMISSED_COUNTS_FACTOR ( 45UL )
\r
134 /* For strict compliance with the Cortex-M spec the task start address should
\r
135 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
\r
136 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
\r
138 /* Let the user override the pre-loading of the initial LR with the address of
\r
139 prvTaskExitError() in case it messes up unwinding of the stack in the
\r
141 #ifdef configTASK_RETURN_ADDRESS
\r
142 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
\r
144 #define portTASK_RETURN_ADDRESS prvTaskExitError
\r
148 * Setup the timer to generate the tick interrupts. The implementation in this
\r
149 * file is weak to allow application writers to change the timer used to
\r
150 * generate the tick interrupt.
\r
152 void vPortSetupTimerInterrupt( void );
\r
155 * Exception handlers.
\r
157 void xPortPendSVHandler( void ) __attribute__ (( naked ));
\r
158 void xPortSysTickHandler( void );
\r
159 void vPortSVCHandler( void ) __attribute__ (( naked ));
\r
162 * Start first task is a separate function so it can be tested in isolation.
\r
164 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
\r
167 * Used to catch tasks that attempt to return from their implementing function.
\r
169 static void prvTaskExitError( void );
\r
171 /*-----------------------------------------------------------*/
\r
173 /* Each task maintains its own interrupt status in the critical nesting
\r
175 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
\r
178 * The number of SysTick increments that make up one tick period.
\r
180 #if( configUSE_TICKLESS_IDLE == 1 )
\r
181 static uint32_t ulTimerCountsForOneTick = 0;
\r
182 #endif /* configUSE_TICKLESS_IDLE */
\r
185 * The maximum number of tick periods that can be suppressed is limited by the
\r
186 * 24 bit resolution of the SysTick timer.
\r
188 #if( configUSE_TICKLESS_IDLE == 1 )
\r
189 static uint32_t xMaximumPossibleSuppressedTicks = 0;
\r
190 #endif /* configUSE_TICKLESS_IDLE */
\r
193 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
\r
194 * power functionality only.
\r
196 #if( configUSE_TICKLESS_IDLE == 1 )
\r
197 static uint32_t ulStoppedTimerCompensation = 0;
\r
198 #endif /* configUSE_TICKLESS_IDLE */
\r
201 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
\r
202 * FreeRTOS API functions are not called from interrupts that have been assigned
\r
203 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
205 #if( configASSERT_DEFINED == 1 )
\r
206 static uint8_t ucMaxSysCallPriority = 0;
\r
207 static uint32_t ulMaxPRIGROUPValue = 0;
\r
208 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
\r
209 #endif /* configASSERT_DEFINED */
\r
211 /*-----------------------------------------------------------*/
\r
214 * See header file for description.
\r
216 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
\r
218 /* Simulate the stack frame as it would be created by a context switch
\r
220 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
\r
221 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
\r
223 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
\r
225 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
\r
226 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
\r
227 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
\r
228 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
\r
230 return pxTopOfStack;
\r
232 /*-----------------------------------------------------------*/
\r
234 static void prvTaskExitError( void )
\r
236 /* A function that implements a task must not exit or attempt to return to
\r
237 its caller as there is nothing to return to. If a task wants to exit it
\r
238 should instead call vTaskDelete( NULL ).
\r
240 Artificially force an assert() to be triggered if configASSERT() is
\r
241 defined, then stop here so application writers can catch the error. */
\r
242 configASSERT( uxCriticalNesting == ~0UL );
\r
243 portDISABLE_INTERRUPTS();
\r
246 /*-----------------------------------------------------------*/
\r
248 void vPortSVCHandler( void )
\r
251 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
\r
252 " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
\r
253 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
\r
254 " ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
\r
255 " msr psp, r0 \n" /* Restore the task stack pointer. */
\r
258 " msr basepri, r0 \n"
\r
259 " orr r14, #0xd \n"
\r
263 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
\r
266 /*-----------------------------------------------------------*/
\r
268 static void prvPortStartFirstTask( void )
\r
271 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
\r
274 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
\r
275 " cpsie i \n" /* Globally enable interrupts. */
\r
279 " svc 0 \n" /* System call to start first task. */
\r
283 /*-----------------------------------------------------------*/
\r
286 * See header file for description.
\r
288 BaseType_t xPortStartScheduler( void )
\r
290 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
\r
291 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
\r
292 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
\r
294 #if( configASSERT_DEFINED == 1 )
\r
296 volatile uint32_t ulOriginalPriority;
\r
297 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
\r
298 volatile uint8_t ucMaxPriorityValue;
\r
300 /* Determine the maximum priority from which ISR safe FreeRTOS API
\r
301 functions can be called. ISR safe functions are those that end in
\r
302 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
\r
303 ensure interrupt entry is as fast and simple as possible.
\r
305 Save the interrupt priority value that is about to be clobbered. */
\r
306 ulOriginalPriority = *pucFirstUserPriorityRegister;
\r
308 /* Determine the number of priority bits available. First write to all
\r
310 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
\r
312 /* Read the value back to see how many bits stuck. */
\r
313 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
\r
315 /* Use the same mask on the maximum system call priority. */
\r
316 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
\r
318 /* Calculate the maximum acceptable priority group value for the number
\r
319 of bits read back. */
\r
320 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
\r
321 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
\r
323 ulMaxPRIGROUPValue--;
\r
324 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
\r
327 #ifdef __NVIC_PRIO_BITS
\r
329 /* Check the CMSIS configuration that defines the number of
\r
330 priority bits matches the number of priority bits actually queried
\r
331 from the hardware. */
\r
332 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
\r
336 #ifdef configPRIO_BITS
\r
338 /* Check the FreeRTOS configuration that defines the number of
\r
339 priority bits matches the number of priority bits actually queried
\r
340 from the hardware. */
\r
341 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
\r
345 /* Shift the priority group value back to its position within the AIRCR
\r
347 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
\r
348 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
\r
350 /* Restore the clobbered interrupt priority register to its original
\r
352 *pucFirstUserPriorityRegister = ulOriginalPriority;
\r
354 #endif /* conifgASSERT_DEFINED */
\r
356 /* Make PendSV and SysTick the lowest priority interrupts. */
\r
357 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
\r
358 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
\r
360 /* Start the timer that generates the tick ISR. Interrupts are disabled
\r
362 vPortSetupTimerInterrupt();
\r
364 /* Initialise the critical nesting count ready for the first task. */
\r
365 uxCriticalNesting = 0;
\r
367 /* Start the first task. */
\r
368 prvPortStartFirstTask();
\r
370 /* Should never get here as the tasks will now be executing! Call the task
\r
371 exit error function to prevent compiler warnings about a static function
\r
372 not being called in the case that the application writer overrides this
\r
373 functionality by defining configTASK_RETURN_ADDRESS. Call
\r
374 vTaskSwitchContext() so link time optimisation does not remove the
\r
376 prvTaskExitError();
\r
377 vTaskSwitchContext();
\r
379 /* Should not get here! */
\r
382 /*-----------------------------------------------------------*/
\r
384 void vPortEndScheduler( void )
\r
386 /* Not implemented in ports where there is nothing to return to.
\r
387 Artificially force an assert. */
\r
388 configASSERT( uxCriticalNesting == 1000UL );
\r
390 /*-----------------------------------------------------------*/
\r
392 void vPortEnterCritical( void )
\r
394 portDISABLE_INTERRUPTS();
\r
395 uxCriticalNesting++;
\r
397 /* This is not the interrupt safe version of the enter critical function so
\r
398 assert() if it is being called from an interrupt context. Only API
\r
399 functions that end in "FromISR" can be used in an interrupt. Only assert if
\r
400 the critical nesting count is 1 to protect against recursive calls if the
\r
401 assert function also uses a critical section. */
\r
402 if( uxCriticalNesting == 1 )
\r
404 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
\r
407 /*-----------------------------------------------------------*/
\r
409 void vPortExitCritical( void )
\r
411 configASSERT( uxCriticalNesting );
\r
412 uxCriticalNesting--;
\r
413 if( uxCriticalNesting == 0 )
\r
415 portENABLE_INTERRUPTS();
\r
418 /*-----------------------------------------------------------*/
\r
420 void xPortPendSVHandler( void )
\r
422 /* This is a naked function. */
\r
429 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
\r
432 " stmdb r0!, {r4-r11} \n" /* Save the remaining registers. */
\r
433 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
\r
435 " stmdb sp!, {r3, r14} \n"
\r
437 " msr basepri, r0 \n"
\r
438 " bl vTaskSwitchContext \n"
\r
440 " msr basepri, r0 \n"
\r
441 " ldmia sp!, {r3, r14} \n"
\r
442 " \n" /* Restore the context, including the critical nesting count. */
\r
444 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
\r
445 " ldmia r0!, {r4-r11} \n" /* Pop the registers. */
\r
451 "pxCurrentTCBConst: .word pxCurrentTCB \n"
\r
452 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
\r
455 /*-----------------------------------------------------------*/
\r
457 void xPortSysTickHandler( void )
\r
459 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
\r
460 executes all interrupts must be unmasked. There is therefore no need to
\r
461 save and then restore the interrupt mask value as its value is already
\r
463 portDISABLE_INTERRUPTS();
\r
465 /* Increment the RTOS tick. */
\r
466 if( xTaskIncrementTick() != pdFALSE )
\r
468 /* A context switch is required. Context switching is performed in
\r
469 the PendSV interrupt. Pend the PendSV interrupt. */
\r
470 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
\r
473 portENABLE_INTERRUPTS();
\r
475 /*-----------------------------------------------------------*/
\r
477 #if( configUSE_TICKLESS_IDLE == 1 )
\r
479 __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
\r
481 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
\r
482 TickType_t xModifiableIdleTime;
\r
484 /* Make sure the SysTick reload value does not overflow the counter. */
\r
485 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
\r
487 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
\r
490 /* Stop the SysTick momentarily. The time the SysTick is stopped for
\r
491 is accounted for as best it can be, but using the tickless mode will
\r
492 inevitably result in some tiny drift of the time maintained by the
\r
493 kernel with respect to calendar time. */
\r
494 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
\r
496 /* Calculate the reload value required to wait xExpectedIdleTime
\r
497 tick periods. -1 is used because this code will execute part way
\r
498 through one of the tick periods. */
\r
499 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
\r
500 if( ulReloadValue > ulStoppedTimerCompensation )
\r
502 ulReloadValue -= ulStoppedTimerCompensation;
\r
505 /* Enter a critical section but don't use the taskENTER_CRITICAL()
\r
506 method as that will mask interrupts that should exit sleep mode. */
\r
507 __asm volatile( "cpsid i" ::: "memory" );
\r
508 __asm volatile( "dsb" );
\r
509 __asm volatile( "isb" );
\r
511 /* If a context switch is pending or a task is waiting for the scheduler
\r
512 to be unsuspended then abandon the low power entry. */
\r
513 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
\r
515 /* Restart from whatever is left in the count register to complete
\r
516 this tick period. */
\r
517 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
519 /* Restart SysTick. */
\r
520 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
522 /* Reset the reload register to the value required for normal tick
\r
524 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
526 /* Re-enable interrupts - see comments above the cpsid instruction()
\r
528 __asm volatile( "cpsie i" ::: "memory" );
\r
532 /* Set the new reload value. */
\r
533 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
\r
535 /* Clear the SysTick count flag and set the count value back to
\r
537 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
539 /* Restart SysTick. */
\r
540 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
542 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
\r
543 set its parameter to 0 to indicate that its implementation contains
\r
544 its own wait for interrupt or wait for event instruction, and so wfi
\r
545 should not be executed again. However, the original expected idle
\r
546 time variable must remain unmodified, so a copy is taken. */
\r
547 xModifiableIdleTime = xExpectedIdleTime;
\r
548 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
\r
549 if( xModifiableIdleTime > 0 )
\r
551 __asm volatile( "dsb" ::: "memory" );
\r
552 __asm volatile( "wfi" );
\r
553 __asm volatile( "isb" );
\r
555 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
\r
557 /* Re-enable interrupts to allow the interrupt that brought the MCU
\r
558 out of sleep mode to execute immediately. see comments above
\r
559 __disable_interrupt() call above. */
\r
560 __asm volatile( "cpsie i" ::: "memory" );
\r
561 __asm volatile( "dsb" );
\r
562 __asm volatile( "isb" );
\r
564 /* Disable interrupts again because the clock is about to be stopped
\r
565 and interrupts that execute while the clock is stopped will increase
\r
566 any slippage between the time maintained by the RTOS and calendar
\r
568 __asm volatile( "cpsid i" ::: "memory" );
\r
569 __asm volatile( "dsb" );
\r
570 __asm volatile( "isb" );
\r
572 /* Disable the SysTick clock without reading the
\r
573 portNVIC_SYSTICK_CTRL_REG register to ensure the
\r
574 portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
\r
575 the time the SysTick is stopped for is accounted for as best it can
\r
576 be, but using the tickless mode will inevitably result in some tiny
\r
577 drift of the time maintained by the kernel with respect to calendar
\r
579 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
\r
581 /* Determine if the SysTick clock has already counted to zero and
\r
582 been set back to the current reload value (the reload back being
\r
583 correct for the entire expected idle time) or if the SysTick is yet
\r
584 to count to zero (in which case an interrupt other than the SysTick
\r
585 must have brought the system out of sleep mode). */
\r
586 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
\r
588 uint32_t ulCalculatedLoadValue;
\r
590 /* The tick interrupt is already pending, and the SysTick count
\r
591 reloaded with ulReloadValue. Reset the
\r
592 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
\r
594 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
\r
596 /* Don't allow a tiny value, or values that have somehow
\r
597 underflowed because the post sleep hook did something
\r
598 that took too long. */
\r
599 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
601 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
\r
604 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
\r
606 /* As the pending tick will be processed as soon as this
\r
607 function exits, the tick value maintained by the tick is stepped
\r
608 forward by one less than the time spent waiting. */
\r
609 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
613 /* Something other than the tick interrupt ended the sleep.
\r
614 Work out how long the sleep lasted rounded to complete tick
\r
615 periods (not the ulReload value which accounted for part
\r
617 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
619 /* How many complete tick periods passed while the processor
\r
621 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
\r
623 /* The reload value is set to whatever fraction of a single tick
\r
625 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
\r
628 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
\r
629 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
\r
631 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
632 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
633 vTaskStepTick( ulCompleteTickPeriods );
\r
634 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
636 /* Exit with interrpts enabled. */
\r
637 __asm volatile( "cpsie i" ::: "memory" );
\r
641 #endif /* configUSE_TICKLESS_IDLE */
\r
642 /*-----------------------------------------------------------*/
\r
645 * Setup the systick timer to generate the tick interrupts at the required
\r
648 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
\r
650 /* Calculate the constants required to configure the tick interrupt. */
\r
651 #if( configUSE_TICKLESS_IDLE == 1 )
\r
653 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
654 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
655 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
657 #endif /* configUSE_TICKLESS_IDLE */
\r
659 /* Stop and clear the SysTick. */
\r
660 portNVIC_SYSTICK_CTRL_REG = 0UL;
\r
661 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
663 /* Configure SysTick to interrupt at the requested rate. */
\r
664 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
\r
665 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
\r
667 /*-----------------------------------------------------------*/
\r
669 #if( configASSERT_DEFINED == 1 )
\r
671 void vPortValidateInterruptPriority( void )
\r
673 uint32_t ulCurrentInterrupt;
\r
674 uint8_t ucCurrentPriority;
\r
676 /* Obtain the number of the currently executing interrupt. */
\r
677 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
\r
679 /* Is the interrupt number a user defined interrupt? */
\r
680 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
682 /* Look up the interrupt's priority. */
\r
683 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
685 /* The following assertion will fail if a service routine (ISR) for
\r
686 an interrupt that has been assigned a priority above
\r
687 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
688 function. ISR safe FreeRTOS API functions must *only* be called
\r
689 from interrupts that have been assigned a priority at or below
\r
690 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
692 Numerically low interrupt priority numbers represent logically high
\r
693 interrupt priorities, therefore the priority of the interrupt must
\r
694 be set to a value equal to or numerically *higher* than
\r
695 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
697 Interrupts that use the FreeRTOS API must not be left at their
\r
698 default priority of zero as that is the highest possible priority,
\r
699 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
700 and therefore also guaranteed to be invalid.
\r
702 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
703 interrupt entry is as fast and simple as possible.
\r
705 The following links provide detailed information:
\r
706 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
707 http://www.freertos.org/FAQHelp.html */
\r
708 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
711 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
712 that define each interrupt's priority to be split between bits that
\r
713 define the interrupt's pre-emption priority bits and bits that define
\r
714 the interrupt's sub-priority. For simplicity all bits must be defined
\r
715 to be pre-emption priority bits. The following assertion will fail if
\r
716 this is not the case (if some bits represent a sub-priority).
\r
718 If the application only uses CMSIS libraries for interrupt
\r
719 configuration then the correct setting can be achieved on all Cortex-M
\r
720 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
721 scheduler. Note however that some vendor specific peripheral libraries
\r
722 assume a non-zero priority group setting, in which cases using a value
\r
723 of zero will result in unpredictable behaviour. */
\r
724 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
727 #endif /* configASSERT_DEFINED */
\r