git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3/port.c

   1 /*\r
   2     FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     ***************************************************************************\r
   8      *                                                                       *\r
   9      *    FreeRTOS provides completely free yet professionally developed,    *\r
  10      *    robust, strictly quality controlled, supported, and cross          *\r
  11      *    platform software that has become a de facto standard.             *\r
  12      *                                                                       *\r
  13      *    Help yourself get started quickly and support the FreeRTOS         *\r
  14      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  15      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  16      *                                                                       *\r
  17      *    Thank you!                                                         *\r
  18      *                                                                       *\r
  19     ***************************************************************************\r
  20 \r
  21     This file is part of the FreeRTOS distribution.\r
  22 \r
  23     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  24     the terms of the GNU General Public License (version 2) as published by the\r
  25     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  26 \r
  27     >>! NOTE: The modification to the GPL is included to allow you to distribute\r
  28     >>! a combined work that includes FreeRTOS without being obliged to provide\r
  29     >>! the source code for proprietary components outside of the FreeRTOS\r
  30     >>! kernel.\r
  31 \r
  32     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  33     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  34     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  35     link: http://www.freertos.org/a00114.html\r
  36 \r
  37     1 tab == 4 spaces!\r
  38 \r
  39     ***************************************************************************\r
  40      *                                                                       *\r
  41      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  42      *    not run, what could be wrong?"                                     *\r
  43      *                                                                       *\r
  44      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  45      *                                                                       *\r
  46     ***************************************************************************\r
  47 \r
  48     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  49     license and Real Time Engineers Ltd. contact details.\r
  50 \r
  51     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  52     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  53     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  54 \r
  55     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  56     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  57     licenses offer ticketed support, indemnification and middleware.\r
  58 \r
  59     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  60     engineered and independently SIL3 certified version for use in safety and\r
  61     mission critical applications that require provable dependability.\r
  62 \r
  63     1 tab == 4 spaces!\r
  64 */\r
  65 \r
  66 /*-----------------------------------------------------------\r
  67  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  68  *----------------------------------------------------------*/\r
  69 \r
  70 /* Scheduler includes. */\r
  71 #include "FreeRTOS.h"\r
  72 #include "task.h"\r
  73 \r
  74 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\r
  75 defined.  The value should also ensure backward compatibility.\r
  76 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */\r
  77 #ifndef configKERNEL_INTERRUPT_PRIORITY\r
  78         #define configKERNEL_INTERRUPT_PRIORITY 255\r
  79 #endif\r
  80 \r
  81 #ifndef configSYSTICK_CLOCK_HZ\r
  82         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  83 #endif\r
  84 \r
  85 /* Constants required to manipulate the core.  Registers first... */\r
  86 #define portNVIC_SYSTICK_CTRL_REG                       ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
  87 #define portNVIC_SYSTICK_LOAD_REG                       ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
  88 #define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
  89 #define portNVIC_SYSPRI2_REG                            ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
  90 /* ...then bits in the registers. */\r
  91 #define portNVIC_SYSTICK_CLK_BIT                        ( 1UL << 2UL )\r
  92 #define portNVIC_SYSTICK_INT_BIT                        ( 1UL << 1UL )\r
  93 #define portNVIC_SYSTICK_ENABLE_BIT                     ( 1UL << 0UL )\r
  94 #define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )\r
  95 #define portNVIC_PENDSVCLEAR_BIT                        ( 1UL << 27UL )\r
  96 #define portNVIC_PEND_SYSTICK_CLEAR_BIT         ( 1UL << 25UL )\r
  97 \r
  98 #define portNVIC_PENDSV_PRI                                     ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
  99 #define portNVIC_SYSTICK_PRI                            ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 100 \r
 101 /* Constants required to check the validity of an interrupt priority. */\r
 102 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
 103 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
 104 #define portAIRCR_REG                                           ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )\r
 105 #define portMAX_8_BIT_VALUE                                     ( ( unsigned char ) 0xff )\r
 106 #define portTOP_BIT_OF_BYTE                                     ( ( unsigned char ) 0x80 )\r
 107 #define portMAX_PRIGROUP_BITS                           ( ( unsigned char ) 7 )\r
 108 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
 109 #define portPRIGROUP_SHIFT                                      ( 8UL )\r
 110 \r
 111 /* Constants required to set up the initial stack. */\r
 112 #define portINITIAL_XPSR                                        ( 0x01000000UL )\r
 113 \r
 114 /* The systick is a 24-bit counter. */\r
 115 #define portMAX_24_BIT_NUMBER                           ( 0xffffffUL )\r
 116 \r
 117 /* A fiddle factor to estimate the number of SysTick counts that would have\r
 118 occurred while the SysTick counter is stopped during tickless idle\r
 119 calculations. */\r
 120 #define portMISSED_COUNTS_FACTOR                        ( 45UL )\r
 121 \r
 122 /* Let the user override the pre-loading of the initial LR with the address of\r
 123 prvTaskExitError() in case is messes up unwinding of the stack in the\r
 124 debugger. */\r
 125 #ifdef configTASK_RETURN_ADDRESS\r
 126         #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS\r
 127 #else\r
 128         #define portTASK_RETURN_ADDRESS prvTaskExitError\r
 129 #endif\r
 130 \r
 131 /* Each task maintains its own interrupt status in the critical nesting\r
 132 variable. */\r
 133 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
 134 \r
 135 /*\r
 136  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 137  * file is weak to allow application writers to change the timer used to\r
 138  * generate the tick interrupt.\r
 139  */\r
 140 void vPortSetupTimerInterrupt( void );\r
 141 \r
 142 /*\r
 143  * Exception handlers.\r
 144  */\r
 145 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 146 void xPortSysTickHandler( void );\r
 147 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 148 \r
 149 /*\r
 150  * Start first task is a separate function so it can be tested in isolation.\r
 151  */\r
 152 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
 153 \r
 154 /*\r
 155  * Used to catch tasks that attempt to return from their implementing function.\r
 156  */\r
 157 static void prvTaskExitError( void );\r
 158 \r
 159 /*-----------------------------------------------------------*/\r
 160 \r
 161 /*\r
 162  * The number of SysTick increments that make up one tick period.\r
 163  */\r
 164 #if configUSE_TICKLESS_IDLE == 1\r
 165         static unsigned long ulTimerCountsForOneTick = 0;\r
 166 #endif /* configUSE_TICKLESS_IDLE */\r
 167 \r
 168 /*\r
 169  * The maximum number of tick periods that can be suppressed is limited by the\r
 170  * 24 bit resolution of the SysTick timer.\r
 171  */\r
 172 #if configUSE_TICKLESS_IDLE == 1\r
 173         static unsigned long xMaximumPossibleSuppressedTicks = 0;\r
 174 #endif /* configUSE_TICKLESS_IDLE */\r
 175 \r
 176 /*\r
 177  * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
 178  * power functionality only.\r
 179  */\r
 180 #if configUSE_TICKLESS_IDLE == 1\r
 181         static unsigned long ulStoppedTimerCompensation = 0;\r
 182 #endif /* configUSE_TICKLESS_IDLE */\r
 183 \r
 184 /*\r
 185  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
 186  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 187  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 188  */\r
 189 #if ( configASSERT_DEFINED == 1 )\r
 190          static unsigned char ucMaxSysCallPriority = 0;\r
 191          static unsigned long ulMaxPRIGROUPValue = 0;\r
 192          static const volatile unsigned char * const pcInterruptPriorityRegisters = ( const volatile unsigned char * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 193 #endif /* configASSERT_DEFINED */\r
 194 \r
 195 /*-----------------------------------------------------------*/\r
 196 \r
 197 /*\r
 198  * See header file for description.\r
 199  */\r
 200 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 201 {\r
 202         /* Simulate the stack frame as it would be created by a context switch\r
 203         interrupt. */\r
 204         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 205         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 206         pxTopOfStack--;\r
 207         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 208         pxTopOfStack--;\r
 209         *pxTopOfStack = ( portSTACK_TYPE ) portTASK_RETURN_ADDRESS;     /* LR */\r
 210         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 211         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 212         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 213 \r
 214         return pxTopOfStack;\r
 215 }\r
 216 /*-----------------------------------------------------------*/\r
 217 \r
 218 static void prvTaskExitError( void )\r
 219 {\r
 220         /* A function that implements a task must not exit or attempt to return to\r
 221         its caller as there is nothing to return to.  If a task wants to exit it\r
 222         should instead call vTaskDelete( NULL ).\r
 223 \r
 224         Artificially force an assert() to be triggered if configASSERT() is\r
 225         defined, then stop here so application writers can catch the error. */\r
 226         configASSERT( uxCriticalNesting == ~0UL );\r
 227         portDISABLE_INTERRUPTS();\r
 228         for( ;; );\r
 229 }\r
 230 /*-----------------------------------------------------------*/\r
 231 \r
 232 void vPortSVCHandler( void )\r
 233 {\r
 234         __asm volatile (\r
 235                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 236                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 237                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 238                                         "       ldmia r0!, {r4-r11}                             \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 239                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 240                                         "       mov r0, #0                                              \n"\r
 241                                         "       msr     basepri, r0                                     \n"\r
 242                                         "       orr r14, #0xd                                   \n"\r
 243                                         "       bx r14                                                  \n"\r
 244                                         "                                                                       \n"\r
 245                                         "       .align 2                                                \n"\r
 246                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 247                                 );\r
 248 }\r
 249 /*-----------------------------------------------------------*/\r
 250 \r
 251 static void prvPortStartFirstTask( void )\r
 252 {\r
 253         __asm volatile(\r
 254                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 255                                         " ldr r0, [r0]                  \n"\r
 256                                         " ldr r0, [r0]                  \n"\r
 257                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 258                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 259                                         " svc 0                                 \n" /* System call to start first task. */\r
 260                                         " nop                                   \n"\r
 261                                 );\r
 262 }\r
 263 /*-----------------------------------------------------------*/\r
 264 \r
 265 /*\r
 266  * See header file for description.\r
 267  */\r
 268 portBASE_TYPE xPortStartScheduler( void )\r
 269 {\r
 270         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
 271         See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 272         configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
 273 \r
 274         #if( configASSERT_DEFINED == 1 )\r
 275         {\r
 276                 volatile unsigned long ulOriginalPriority;\r
 277                 volatile char * const pcFirstUserPriorityRegister = ( volatile char * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 278                 volatile unsigned char ucMaxPriorityValue;\r
 279 \r
 280                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 281                 functions can be called.  ISR safe functions are those that end in\r
 282                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 283                 ensure interrupt entry is as fast and simple as possible.\r
 284 \r
 285                 Save the interrupt priority value that is about to be clobbered. */\r
 286                 ulOriginalPriority = *pcFirstUserPriorityRegister;\r
 287 \r
 288                 /* Determine the number of priority bits available.  First write to all\r
 289                 possible bits. */\r
 290                 *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
 291 \r
 292                 /* Read the value back to see how many bits stuck. */\r
 293                 ucMaxPriorityValue = *pcFirstUserPriorityRegister;\r
 294 \r
 295                 /* Use the same mask on the maximum system call priority. */\r
 296                 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
 297 \r
 298                 /* Calculate the maximum acceptable priority group value for the number\r
 299                 of bits read back. */\r
 300                 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
 301                 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
 302                 {\r
 303                         ulMaxPRIGROUPValue--;\r
 304                         ucMaxPriorityValue <<= ( unsigned char ) 0x01;\r
 305                 }\r
 306 \r
 307                 /* Shift the priority group value back to its position within the AIRCR\r
 308                 register. */\r
 309                 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
 310                 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
 311 \r
 312                 /* Restore the clobbered interrupt priority register to its original\r
 313                 value. */\r
 314                 *pcFirstUserPriorityRegister = ulOriginalPriority;\r
 315         }\r
 316         #endif /* conifgASSERT_DEFINED */\r
 317 \r
 318         /* Make PendSV and SysTick the lowest priority interrupts. */\r
 319         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 320         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 321 \r
 322         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 323         here already. */\r
 324         vPortSetupTimerInterrupt();\r
 325 \r
 326         /* Initialise the critical nesting count ready for the first task. */\r
 327         uxCriticalNesting = 0;\r
 328 \r
 329         /* Start the first task. */\r
 330         prvPortStartFirstTask();\r
 331 \r
 332         /* Should never get here as the tasks will now be executing!  Call the task\r
 333         exit error function to prevent compiler warnings about a static function\r
 334         not being called in the case that the application writer overrides this\r
 335         functionality by defining configTASK_RETURN_ADDRESS. */\r
 336         prvTaskExitError();\r
 337 \r
 338         /* Should not get here! */\r
 339         return 0;\r
 340 }\r
 341 /*-----------------------------------------------------------*/\r
 342 \r
 343 void vPortEndScheduler( void )\r
 344 {\r
 345         /* It is unlikely that the CM3 port will require this function as there\r
 346         is nothing to return to.  */\r
 347 }\r
 348 /*-----------------------------------------------------------*/\r
 349 \r
 350 void vPortYield( void )\r
 351 {\r
 352         /* Set a PendSV to request a context switch. */\r
 353         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 354 \r
 355         /* Barriers are normally not required but do ensure the code is completely\r
 356         within the specified behaviour for the architecture. */\r
 357         __asm volatile( "dsb" );\r
 358         __asm volatile( "isb" );\r
 359 }\r
 360 /*-----------------------------------------------------------*/\r
 361 \r
 362 void vPortEnterCritical( void )\r
 363 {\r
 364         portDISABLE_INTERRUPTS();\r
 365         uxCriticalNesting++;\r
 366         __asm volatile( "dsb" );\r
 367         __asm volatile( "isb" );\r
 368 }\r
 369 /*-----------------------------------------------------------*/\r
 370 \r
 371 void vPortExitCritical( void )\r
 372 {\r
 373         uxCriticalNesting--;\r
 374         if( uxCriticalNesting == 0 )\r
 375         {\r
 376                 portENABLE_INTERRUPTS();\r
 377         }\r
 378 }\r
 379 /*-----------------------------------------------------------*/\r
 380 \r
 381 __attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )\r
 382 {\r
 383         __asm volatile                                                                                                          \\r
 384         (                                                                                                                                       \\r
 385                 "       mrs r0, basepri                                                                                 \n" \\r
 386                 "       mov r1, %0                                                                                              \n"     \\r
 387                 "       msr basepri, r1                                                                                 \n" \\r
 388                 "       bx lr                                                                                                   \n" \\r
 389                 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1"    \\r
 390         );\r
 391 \r
 392         /* This return will not be reached but is necessary to prevent compiler\r
 393         warnings. */\r
 394         return 0;\r
 395 }\r
 396 /*-----------------------------------------------------------*/\r
 397 \r
 398 __attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )\r
 399 {\r
 400         __asm volatile                                                                                                  \\r
 401         (                                                                                                                               \\r
 402                 "       msr basepri, r0                                                                         \n"     \\r
 403                 "       bx lr                                                                                           \n" \\r
 404                 :::"r0"                                                                                                         \\r
 405         );\r
 406 \r
 407         /* Just to avoid compiler warnings. */\r
 408         ( void ) ulNewMaskValue;\r
 409 }\r
 410 /*-----------------------------------------------------------*/\r
 411 \r
 412 void xPortPendSVHandler( void )\r
 413 {\r
 414         /* This is a naked function. */\r
 415 \r
 416         __asm volatile\r
 417         (\r
 418         "       mrs r0, psp                                                     \n"\r
 419         "                                                                               \n"\r
 420         "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 421         "       ldr     r2, [r3]                                                \n"\r
 422         "                                                                               \n"\r
 423         "       stmdb r0!, {r4-r11}                                     \n" /* Save the remaining registers. */\r
 424         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 425         "                                                                               \n"\r
 426         "       stmdb sp!, {r3, r14}                            \n"\r
 427         "       mov r0, %0                                                      \n"\r
 428         "       msr basepri, r0                                         \n"\r
 429         "       bl vTaskSwitchContext                           \n"\r
 430         "       mov r0, #0                                                      \n"\r
 431         "       msr basepri, r0                                         \n"\r
 432         "       ldmia sp!, {r3, r14}                            \n"\r
 433         "                                                                               \n"     /* Restore the context, including the critical nesting count. */\r
 434         "       ldr r1, [r3]                                            \n"\r
 435         "       ldr r0, [r1]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 436         "       ldmia r0!, {r4-r11}                                     \n" /* Pop the registers. */\r
 437         "       msr psp, r0                                                     \n"\r
 438         "       bx r14                                                          \n"\r
 439         "                                                                               \n"\r
 440         "       .align 2                                                        \n"\r
 441         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 442         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 443         );\r
 444 }\r
 445 /*-----------------------------------------------------------*/\r
 446 \r
 447 void xPortSysTickHandler( void )\r
 448 {\r
 449         /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
 450         executes all interrupts must be unmasked.  There is therefore no need to\r
 451         save and then restore the interrupt mask value as its value is already\r
 452         known. */\r
 453         ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
 454         {\r
 455                 /* Increment the RTOS tick. */\r
 456                 if( xTaskIncrementTick() != pdFALSE )\r
 457                 {\r
 458                         /* A context switch is required.  Context switching is performed in\r
 459                         the PendSV interrupt.  Pend the PendSV interrupt. */\r
 460                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 461                 }\r
 462         }\r
 463         portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
 464 }\r
 465 /*-----------------------------------------------------------*/\r
 466 \r
 467 #if configUSE_TICKLESS_IDLE == 1\r
 468 \r
 469         __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
 470         {\r
 471         unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;\r
 472         portTickType xModifiableIdleTime;\r
 473 \r
 474                 /* Make sure the SysTick reload value does not overflow the counter. */\r
 475                 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
 476                 {\r
 477                         xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
 478                 }\r
 479 \r
 480                 /* Stop the SysTick momentarily.  The time the SysTick is stopped for\r
 481                 is accounted for as best it can be, but using the tickless mode will\r
 482                 inevitably result in some tiny drift of the time maintained by the\r
 483                 kernel with respect to calendar time. */\r
 484                 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 485 \r
 486                 /* Calculate the reload value required to wait xExpectedIdleTime\r
 487                 tick periods.  -1 is used because this code will execute part way\r
 488                 through one of the tick periods. */\r
 489                 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
 490                 if( ulReloadValue > ulStoppedTimerCompensation )\r
 491                 {\r
 492                         ulReloadValue -= ulStoppedTimerCompensation;\r
 493                 }\r
 494 \r
 495                 /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
 496                 method as that will mask interrupts that should exit sleep mode. */\r
 497                 __asm volatile( "cpsid i" );\r
 498 \r
 499                 /* If a context switch is pending or a task is waiting for the scheduler\r
 500                 to be unsuspended then abandon the low power entry. */\r
 501                 if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
 502                 {\r
 503                         /* Restart from whatever is left in the count register to complete\r
 504                         this tick period. */\r
 505                         portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 506 \r
 507                         /* Restart SysTick. */\r
 508                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 509 \r
 510                         /* Reset the reload register to the value required for normal tick\r
 511                         periods. */\r
 512                         portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 513 \r
 514                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 515                         above. */\r
 516                         __asm volatile( "cpsie i" );\r
 517                 }\r
 518                 else\r
 519                 {\r
 520                         /* Set the new reload value. */\r
 521                         portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
 522 \r
 523                         /* Clear the SysTick count flag and set the count value back to\r
 524                         zero. */\r
 525                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 526 \r
 527                         /* Restart SysTick. */\r
 528                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 529 \r
 530                         /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\r
 531                         set its parameter to 0 to indicate that its implementation contains\r
 532                         its own wait for interrupt or wait for event instruction, and so wfi\r
 533                         should not be executed again.  However, the original expected idle\r
 534                         time variable must remain unmodified, so a copy is taken. */\r
 535                         xModifiableIdleTime = xExpectedIdleTime;\r
 536                         configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
 537                         if( xModifiableIdleTime > 0 )\r
 538                         {\r
 539                                 __asm volatile( "dsb" );\r
 540                                 __asm volatile( "wfi" );\r
 541                                 __asm volatile( "isb" );\r
 542                         }\r
 543                         configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 544 \r
 545                         /* Stop SysTick.  Again, the time the SysTick is stopped for is\r
 546                         accounted for as best it can be, but using the tickless mode will\r
 547                         inevitably result in some tiny drift of the time maintained by the\r
 548                         kernel with respect to calendar time. */\r
 549                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 550 \r
 551                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 552                         above. */\r
 553                         __asm volatile( "cpsie i" );\r
 554 \r
 555                         if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
 556                         {\r
 557                                 unsigned long ulCalculatedLoadValue;\r
 558 \r
 559                                 /* The tick interrupt has already executed, and the SysTick\r
 560                                 count reloaded with ulReloadValue.  Reset the\r
 561                                 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
 562                                 period. */\r
 563                                 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 564 \r
 565                                 /* Don't allow a tiny value, or values that have somehow\r
 566                                 underflowed because the post sleep hook did something\r
 567                                 that took too long. */\r
 568                                 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\r
 569                                 {\r
 570                                         ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\r
 571                                 }\r
 572 \r
 573                                 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\r
 574 \r
 575                                 /* The tick interrupt handler will already have pended the tick\r
 576                                 processing in the kernel.  As the pending tick will be\r
 577                                 processed as soon as this function exits, the tick value\r
 578                                 maintained by the tick is stepped forward by one less than the\r
 579                                 time spent waiting. */\r
 580                                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
 581                         }\r
 582                         else\r
 583                         {\r
 584                                 /* Something other than the tick interrupt ended the sleep.\r
 585                                 Work out how long the sleep lasted rounded to complete tick\r
 586                                 periods (not the ulReload value which accounted for part\r
 587                                 ticks). */\r
 588                                 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 589 \r
 590                                 /* How many complete tick periods passed while the processor\r
 591                                 was waiting? */\r
 592                                 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
 593 \r
 594                                 /* The reload value is set to whatever fraction of a single tick\r
 595                                 period remains. */\r
 596                                 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
 597                         }\r
 598 \r
 599                         /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
 600                         again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
 601                         value.  The critical section is used to ensure the tick interrupt\r
 602                         can only execute once in the case that the reload register is near\r
 603                         zero. */\r
 604                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 605                         portENTER_CRITICAL();\r
 606                         {\r
 607                                 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 608                                 vTaskStepTick( ulCompleteTickPeriods );\r
 609                                 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 610                         }\r
 611                         portEXIT_CRITICAL();\r
 612                 }\r
 613         }\r
 614 \r
 615 #endif /* #if configUSE_TICKLESS_IDLE */\r
 616 /*-----------------------------------------------------------*/\r
 617 \r
 618 /*\r
 619  * Setup the systick timer to generate the tick interrupts at the required\r
 620  * frequency.\r
 621  */\r
 622 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 623 {\r
 624         /* Calculate the constants required to configure the tick interrupt. */\r
 625         #if configUSE_TICKLESS_IDLE == 1\r
 626         {\r
 627                 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
 628                 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
 629                 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
 630         }\r
 631         #endif /* configUSE_TICKLESS_IDLE */\r
 632 \r
 633         /* Configure SysTick to interrupt at the requested rate. */\r
 634         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
 635         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 636 }\r
 637 /*-----------------------------------------------------------*/\r
 638 \r
 639 #if( configASSERT_DEFINED == 1 )\r
 640 \r
 641         void vPortValidateInterruptPriority( void )\r
 642         {\r
 643         unsigned long ulCurrentInterrupt;\r
 644         unsigned char ucCurrentPriority;\r
 645 \r
 646                 /* Obtain the number of the currently executing interrupt. */\r
 647                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
 648 \r
 649                 /* Is the interrupt number a user defined interrupt? */\r
 650                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 651                 {\r
 652                         /* Look up the interrupt's priority. */\r
 653                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 654 \r
 655                         /* The following assertion will fail if a service routine (ISR) for\r
 656                         an interrupt that has been assigned a priority above\r
 657                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 658                         function.  ISR safe FreeRTOS API functions must *only* be called\r
 659                         from interrupts that have been assigned a priority at or below\r
 660                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 661 \r
 662                         Numerically low interrupt priority numbers represent logically high\r
 663                         interrupt priorities, therefore the priority of the interrupt must\r
 664                         be set to a value equal to or numerically *higher* than\r
 665                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 666 \r
 667                         Interrupts that use the FreeRTOS API must not be left at their\r
 668                         default priority of     zero as that is the highest possible priority,\r
 669                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
 670                         and     therefore also guaranteed to be invalid.\r
 671 \r
 672                         FreeRTOS maintains separate thread and ISR API functions to ensure\r
 673                         interrupt entry is as fast and simple as possible.\r
 674 \r
 675                         The following links provide detailed information:\r
 676                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 677                         http://www.freertos.org/FAQHelp.html */\r
 678                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 679                 }\r
 680 \r
 681                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits\r
 682                 that define each interrupt's priority to be split between bits that\r
 683                 define the interrupt's pre-emption priority bits and bits that define\r
 684                 the interrupt's sub-priority.  For simplicity all bits must be defined\r
 685                 to be pre-emption priority bits.  The following assertion will fail if\r
 686                 this is not the case (if some bits represent a sub-priority).\r
 687 \r
 688                 If the application only uses CMSIS libraries for interrupt\r
 689                 configuration then the correct setting can be achieved on all Cortex-M\r
 690                 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
 691                 scheduler.  Note however that some vendor specific peripheral libraries\r
 692                 assume a non-zero priority group setting, in which cases using a value\r
 693                 of zero will result in unpredicable behaviour. */\r
 694                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
 695         }\r
 696 \r
 697 #endif /* configASSERT_DEFINED */\r
 698 \r
 699 \r
 700 \r
 701 \r
 702 \r
 703 \r
 704 \r
 705 \r
 706 \r
 707 \r
 708 \r
 709 \r
 710 \r
 711 \r
 712 \r
 713 \r
 714 \r
 715 \r
 716 \r
 717 \r
 718 \r