git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3/port.c

   1 /*\r
   2     FreeRTOS V7.5.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
   3 \r
   4     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   5 \r
   6     ***************************************************************************\r
   7      *                                                                       *\r
   8      *    FreeRTOS provides completely free yet professionally developed,    *\r
   9      *    robust, strictly quality controlled, supported, and cross          *\r
  10      *    platform software that has become a de facto standard.             *\r
  11      *                                                                       *\r
  12      *    Help yourself get started quickly and support the FreeRTOS         *\r
  13      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  14      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  15      *                                                                       *\r
  16      *    Thank you!                                                         *\r
  17      *                                                                       *\r
  18     ***************************************************************************\r
  19 \r
  20     This file is part of the FreeRTOS distribution.\r
  21 \r
  22     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  23     the terms of the GNU General Public License (version 2) as published by the\r
  24     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  25 \r
  26     >>! NOTE: The modification to the GPL is included to allow you to distribute\r
  27     >>! a combined work that includes FreeRTOS without being obliged to provide\r
  28     >>! the source code for proprietary components outside of the FreeRTOS\r
  29     >>! kernel.\r
  30 \r
  31     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  32     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  33     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  34     link: http://www.freertos.org/a00114.html\r
  35 \r
  36     1 tab == 4 spaces!\r
  37 \r
  38     ***************************************************************************\r
  39      *                                                                       *\r
  40      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  41      *    not run, what could be wrong?"                                     *\r
  42      *                                                                       *\r
  43      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  44      *                                                                       *\r
  45     ***************************************************************************\r
  46 \r
  47     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  48     license and Real Time Engineers Ltd. contact details.\r
  49 \r
  50     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  51     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  52     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  53 \r
  54     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  55     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  56     licenses offer ticketed support, indemnification and middleware.\r
  57 \r
  58     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  59     engineered and independently SIL3 certified version for use in safety and\r
  60     mission critical applications that require provable dependability.\r
  61 \r
  62     1 tab == 4 spaces!\r
  63 */\r
  64 \r
  65 /*-----------------------------------------------------------\r
  66  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  67  *----------------------------------------------------------*/\r
  68 \r
  69 /* Scheduler includes. */\r
  70 #include "FreeRTOS.h"\r
  71 #include "task.h"\r
  72 \r
  73 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\r
  74 defined.  The value should also ensure backward compatibility.\r
  75 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */\r
  76 #ifndef configKERNEL_INTERRUPT_PRIORITY\r
  77         #define configKERNEL_INTERRUPT_PRIORITY 255\r
  78 #endif\r
  79 \r
  80 #ifndef configSYSTICK_CLOCK_HZ\r
  81         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  82 #endif\r
  83 \r
  84 /* Constants required to manipulate the core.  Registers first... */\r
  85 #define portNVIC_SYSTICK_CTRL_REG                       ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
  86 #define portNVIC_SYSTICK_LOAD_REG                       ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
  87 #define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
  88 #define portNVIC_SYSPRI2_REG                            ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
  89 /* ...then bits in the registers. */\r
  90 #define portNVIC_SYSTICK_CLK_BIT                        ( 1UL << 2UL )\r
  91 #define portNVIC_SYSTICK_INT_BIT                        ( 1UL << 1UL )\r
  92 #define portNVIC_SYSTICK_ENABLE_BIT                     ( 1UL << 0UL )\r
  93 #define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )\r
  94 #define portNVIC_PENDSVCLEAR_BIT                        ( 1UL << 27UL )\r
  95 #define portNVIC_PEND_SYSTICK_CLEAR_BIT         ( 1UL << 25UL )\r
  96 \r
  97 #define portNVIC_PENDSV_PRI                                     ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
  98 #define portNVIC_SYSTICK_PRI                            ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
  99 \r
 100 /* Constants required to check the validity of an interrupt prority. */\r
 101 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
 102 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
 103 #define portAIRCR_REG                                           ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )\r
 104 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
 105 \r
 106 /* Constants required to set up the initial stack. */\r
 107 #define portINITIAL_XPSR                                        ( 0x01000000 )\r
 108 \r
 109 /* The systick is a 24-bit counter. */\r
 110 #define portMAX_24_BIT_NUMBER                           ( 0xffffffUL )\r
 111 \r
 112 /* A fiddle factor to estimate the number of SysTick counts that would have\r
 113 occurred while the SysTick counter is stopped during tickless idle\r
 114 calculations. */\r
 115 #define portMISSED_COUNTS_FACTOR                        ( 45UL )\r
 116 \r
 117 /* Each task maintains its own interrupt status in the critical nesting\r
 118 variable. */\r
 119 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
 120 \r
 121 /*\r
 122  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 123  * file is weak to allow application writers to change the timer used to\r
 124  * generate the tick interrupt.\r
 125  */\r
 126 void vPortSetupTimerInterrupt( void );\r
 127 \r
 128 /*\r
 129  * Exception handlers.\r
 130  */\r
 131 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 132 void xPortSysTickHandler( void );\r
 133 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 134 \r
 135 /*\r
 136  * Start first task is a separate function so it can be tested in isolation.\r
 137  */\r
 138 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
 139 \r
 140 /*-----------------------------------------------------------*/\r
 141 \r
 142 /*\r
 143  * The number of SysTick increments that make up one tick period.\r
 144  */\r
 145 #if configUSE_TICKLESS_IDLE == 1\r
 146         static unsigned long ulTimerCountsForOneTick = 0;\r
 147 #endif /* configUSE_TICKLESS_IDLE */\r
 148 \r
 149 /*\r
 150  * The maximum number of tick periods that can be suppressed is limited by the\r
 151  * 24 bit resolution of the SysTick timer.\r
 152  */\r
 153 #if configUSE_TICKLESS_IDLE == 1\r
 154         static unsigned long xMaximumPossibleSuppressedTicks = 0;\r
 155 #endif /* configUSE_TICKLESS_IDLE */\r
 156 \r
 157 /*\r
 158  * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
 159  * power functionality only.\r
 160  */\r
 161 #if configUSE_TICKLESS_IDLE == 1\r
 162         static unsigned long ulStoppedTimerCompensation = 0;\r
 163 #endif /* configUSE_TICKLESS_IDLE */\r
 164 \r
 165 /*\r
 166  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure \r
 167  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 168  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 169  */\r
 170 #if ( configASSERT_DEFINED == 1 )\r
 171          static unsigned char ucMaxSysCallPriority = 0;\r
 172          static const volatile unsigned char * const pcInterruptPriorityRegisters = ( const volatile unsigned char * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 173 #endif /* configASSERT_DEFINED */\r
 174 \r
 175 /*-----------------------------------------------------------*/\r
 176 \r
 177 /*\r
 178  * See header file for description.\r
 179  */\r
 180 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 181 {\r
 182         /* Simulate the stack frame as it would be created by a context switch\r
 183         interrupt. */\r
 184         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 185         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 186         pxTopOfStack--;\r
 187         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 188         pxTopOfStack--;\r
 189         *pxTopOfStack = 0;      /* LR */\r
 190         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 191         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 192         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 193 \r
 194         return pxTopOfStack;\r
 195 }\r
 196 /*-----------------------------------------------------------*/\r
 197 \r
 198 void vPortSVCHandler( void )\r
 199 {\r
 200         __asm volatile (\r
 201                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 202                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 203                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 204                                         "       ldmia r0!, {r4-r11}                             \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 205                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 206                                         "       mov r0, #0                                              \n"\r
 207                                         "       msr     basepri, r0                                     \n"\r
 208                                         "       orr r14, #0xd                                   \n"\r
 209                                         "       bx r14                                                  \n"\r
 210                                         "                                                                       \n"\r
 211                                         "       .align 2                                                \n"\r
 212                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 213                                 );\r
 214 }\r
 215 /*-----------------------------------------------------------*/\r
 216 \r
 217 static void prvPortStartFirstTask( void )\r
 218 {\r
 219         __asm volatile(\r
 220                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 221                                         " ldr r0, [r0]                  \n"\r
 222                                         " ldr r0, [r0]                  \n"\r
 223                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 224                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 225                                         " svc 0                                 \n" /* System call to start first task. */\r
 226                                         " nop                                   \n"\r
 227                                 );\r
 228 }\r
 229 /*-----------------------------------------------------------*/\r
 230 \r
 231 /*\r
 232  * See header file for description.\r
 233  */\r
 234 portBASE_TYPE xPortStartScheduler( void )\r
 235 {\r
 236         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
 237         See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 238         configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
 239 \r
 240         #if( configASSERT_DEFINED == 1 )\r
 241         {\r
 242                 volatile unsigned long ulOriginalPriority;\r
 243                 volatile char * const pcFirstUserPriorityRegister = ( volatile char * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 244 \r
 245                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 246                 functions can be called.  ISR safe functions are those that end in\r
 247                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 248                 ensure interrupt entry is as fast and simple as possible.\r
 249 \r
 250                 Save the interrupt priority value that is about to be clobbered. */\r
 251                 ulOriginalPriority = *pcFirstUserPriorityRegister;\r
 252 \r
 253                 /* Write the configMAX_SYSCALL_INTERRUPT_PRIORITY value to an interrupt\r
 254                 priority register. */\r
 255                 *pcFirstUserPriorityRegister = configMAX_SYSCALL_INTERRUPT_PRIORITY;\r
 256 \r
 257                 /* Read back the written priority to obtain its value as seen by the\r
 258                 hardware, which will only implement a subset of the priority bits. */\r
 259                 ucMaxSysCallPriority = *pcFirstUserPriorityRegister;\r
 260 \r
 261                 /* Restore the clobbered interrupt priority register to its original\r
 262                 value. */\r
 263                 *pcFirstUserPriorityRegister = ulOriginalPriority;\r
 264         }\r
 265         #endif /* conifgASSERT_DEFINED */\r
 266 \r
 267         /* Make PendSV and SysTick the lowest priority interrupts. */\r
 268         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 269         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 270 \r
 271         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 272         here already. */\r
 273         vPortSetupTimerInterrupt();\r
 274 \r
 275         /* Initialise the critical nesting count ready for the first task. */\r
 276         uxCriticalNesting = 0;\r
 277 \r
 278         /* Start the first task. */\r
 279         prvPortStartFirstTask();\r
 280 \r
 281         /* Should not get here! */\r
 282         return 0;\r
 283 }\r
 284 /*-----------------------------------------------------------*/\r
 285 \r
 286 void vPortEndScheduler( void )\r
 287 {\r
 288         /* It is unlikely that the CM3 port will require this function as there\r
 289         is nothing to return to.  */\r
 290 }\r
 291 /*-----------------------------------------------------------*/\r
 292 \r
 293 void vPortYield( void )\r
 294 {\r
 295         /* Set a PendSV to request a context switch. */\r
 296         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 297 \r
 298         /* Barriers are normally not required but do ensure the code is completely\r
 299         within the specified behaviour for the architecture. */\r
 300         __asm volatile( "dsb" );\r
 301         __asm volatile( "isb" );\r
 302 }\r
 303 /*-----------------------------------------------------------*/\r
 304 \r
 305 void vPortEnterCritical( void )\r
 306 {\r
 307         portDISABLE_INTERRUPTS();\r
 308         uxCriticalNesting++;\r
 309         __asm volatile( "dsb" );\r
 310         __asm volatile( "isb" );\r
 311 }\r
 312 /*-----------------------------------------------------------*/\r
 313 \r
 314 void vPortExitCritical( void )\r
 315 {\r
 316         uxCriticalNesting--;\r
 317         if( uxCriticalNesting == 0 )\r
 318         {\r
 319                 portENABLE_INTERRUPTS();\r
 320         }\r
 321 }\r
 322 /*-----------------------------------------------------------*/\r
 323 \r
 324 __attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )\r
 325 {\r
 326         __asm volatile                                                                                                          \\r
 327         (                                                                                                                                       \\r
 328                 "       mrs r0, basepri                                                                                 \n" \\r
 329                 "       mov r1, %0                                                                                              \n"     \\r
 330                 "       msr basepri, r1                                                                                 \n" \\r
 331                 "       bx lr                                                                                                   \n" \\r
 332                 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1"    \\r
 333         );\r
 334 \r
 335         /* This return will not be reached but is necessary to prevent compiler\r
 336         warnings. */\r
 337         return 0;\r
 338 }\r
 339 /*-----------------------------------------------------------*/\r
 340 \r
 341 __attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )\r
 342 {\r
 343         __asm volatile                                                                                                  \\r
 344         (                                                                                                                               \\r
 345                 "       msr basepri, r0                                                                         \n"     \\r
 346                 "       bx lr                                                                                           \n" \\r
 347                 :::"r0"                                                                                                         \\r
 348         );\r
 349 \r
 350         /* Just to avoid compiler warnings. */\r
 351         ( void ) ulNewMaskValue;\r
 352 }\r
 353 /*-----------------------------------------------------------*/\r
 354 \r
 355 void xPortPendSVHandler( void )\r
 356 {\r
 357         /* This is a naked function. */\r
 358 \r
 359         __asm volatile\r
 360         (\r
 361         "       mrs r0, psp                                                     \n"\r
 362         "                                                                               \n"\r
 363         "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 364         "       ldr     r2, [r3]                                                \n"\r
 365         "                                                                               \n"\r
 366         "       stmdb r0!, {r4-r11}                                     \n" /* Save the remaining registers. */\r
 367         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 368         "                                                                               \n"\r
 369         "       stmdb sp!, {r3, r14}                            \n"\r
 370         "       mov r0, %0                                                      \n"\r
 371         "       msr basepri, r0                                         \n"\r
 372         "       bl vTaskSwitchContext                           \n"\r
 373         "       mov r0, #0                                                      \n"\r
 374         "       msr basepri, r0                                         \n"\r
 375         "       ldmia sp!, {r3, r14}                            \n"\r
 376         "                                                                               \n"     /* Restore the context, including the critical nesting count. */\r
 377         "       ldr r1, [r3]                                            \n"\r
 378         "       ldr r0, [r1]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 379         "       ldmia r0!, {r4-r11}                                     \n" /* Pop the registers. */\r
 380         "       msr psp, r0                                                     \n"\r
 381         "       bx r14                                                          \n"\r
 382         "                                                                               \n"\r
 383         "       .align 2                                                        \n"\r
 384         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 385         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 386         );\r
 387 }\r
 388 /*-----------------------------------------------------------*/\r
 389 \r
 390 void xPortSysTickHandler( void )\r
 391 {\r
 392         /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
 393         executes all interrupts must be unmasked.  There is therefore no need to\r
 394         save and then restore the interrupt mask value as its value is already\r
 395         known. */\r
 396         ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
 397         {\r
 398                 /* Increment the RTOS tick. */\r
 399                 if( xTaskIncrementTick() != pdFALSE )\r
 400                 {\r
 401                         /* A context switch is required.  Context switching is performed in\r
 402                         the PendSV interrupt.  Pend the PendSV interrupt. */\r
 403                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 404                 }\r
 405         }\r
 406         portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
 407 }\r
 408 /*-----------------------------------------------------------*/\r
 409 \r
 410 #if configUSE_TICKLESS_IDLE == 1\r
 411 \r
 412         __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
 413         {\r
 414         unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;\r
 415         portTickType xModifiableIdleTime;\r
 416 \r
 417                 /* Make sure the SysTick reload value does not overflow the counter. */\r
 418                 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
 419                 {\r
 420                         xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
 421                 }\r
 422 \r
 423                 /* Stop the SysTick momentarily.  The time the SysTick is stopped for\r
 424                 is accounted for as best it can be, but using the tickless mode will\r
 425                 inevitably result in some tiny drift of the time maintained by the\r
 426                 kernel with respect to calendar time. */\r
 427                 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 428 \r
 429                 /* Calculate the reload value required to wait xExpectedIdleTime\r
 430                 tick periods.  -1 is used because this code will execute part way\r
 431                 through one of the tick periods. */\r
 432                 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
 433                 if( ulReloadValue > ulStoppedTimerCompensation )\r
 434                 {\r
 435                         ulReloadValue -= ulStoppedTimerCompensation;\r
 436                 }\r
 437 \r
 438                 /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
 439                 method as that will mask interrupts that should exit sleep mode. */\r
 440                 __asm volatile( "cpsid i" );\r
 441 \r
 442                 /* If a context switch is pending or a task is waiting for the scheduler\r
 443                 to be unsuspended then abandon the low power entry. */\r
 444                 if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
 445                 {\r
 446                         /* Restart SysTick. */\r
 447                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 448 \r
 449                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 450                         above. */\r
 451                         __asm volatile( "cpsie i" );\r
 452                 }\r
 453                 else\r
 454                 {\r
 455                         /* Set the new reload value. */\r
 456                         portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
 457 \r
 458                         /* Clear the SysTick count flag and set the count value back to\r
 459                         zero. */\r
 460                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 461 \r
 462                         /* Restart SysTick. */\r
 463                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 464 \r
 465                         /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\r
 466                         set its parameter to 0 to indicate that its implementation contains\r
 467                         its own wait for interrupt or wait for event instruction, and so wfi\r
 468                         should not be executed again.  However, the original expected idle\r
 469                         time variable must remain unmodified, so a copy is taken. */\r
 470                         xModifiableIdleTime = xExpectedIdleTime;\r
 471                         configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
 472                         if( xModifiableIdleTime > 0 )\r
 473                         {\r
 474                                 __asm volatile( "dsb" );\r
 475                                 __asm volatile( "wfi" );\r
 476                                 __asm volatile( "isb" );\r
 477                         }\r
 478                         configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 479 \r
 480                         /* Stop SysTick.  Again, the time the SysTick is stopped for is\r
 481                         accounted for as best it can be, but using the tickless mode will\r
 482                         inevitably result in some tiny drift of the time maintained by the\r
 483                         kernel with respect to calendar time. */\r
 484                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 485 \r
 486                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 487                         above. */\r
 488                         __asm volatile( "cpsie i" );\r
 489 \r
 490                         if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
 491                         {\r
 492                                 /* The tick interrupt has already executed, and the SysTick\r
 493                                 count reloaded with ulReloadValue.  Reset the\r
 494                                 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
 495                                 period. */\r
 496                                 portNVIC_SYSTICK_LOAD_REG = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 497 \r
 498                                 /* The tick interrupt handler will already have pended the tick\r
 499                                 processing in the kernel.  As the pending tick will be\r
 500                                 processed as soon as this function exits, the tick value\r
 501                                 maintained by the tick is stepped forward by one less than the\r
 502                                 time spent waiting. */\r
 503                                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
 504                         }\r
 505                         else\r
 506                         {\r
 507                                 /* Something other than the tick interrupt ended the sleep.\r
 508                                 Work out how long the sleep lasted rounded to complete tick\r
 509                                 periods (not the ulReload value which accounted for part\r
 510                                 ticks). */\r
 511                                 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 512 \r
 513                                 /* How many complete tick periods passed while the processor\r
 514                                 was waiting? */\r
 515                                 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
 516 \r
 517                                 /* The reload value is set to whatever fraction of a single tick\r
 518                                 period remains. */\r
 519                                 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
 520                         }\r
 521 \r
 522                         /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
 523                         again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
 524                         value. */\r
 525                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 526                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 527 \r
 528                         vTaskStepTick( ulCompleteTickPeriods );\r
 529 \r
 530                         /* The counter must start by the time the reload value is reset. */\r
 531                         configASSERT( portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 532                         portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 533                 }\r
 534         }\r
 535 \r
 536 #endif /* #if configUSE_TICKLESS_IDLE */\r
 537 /*-----------------------------------------------------------*/\r
 538 \r
 539 /*\r
 540  * Setup the systick timer to generate the tick interrupts at the required\r
 541  * frequency.\r
 542  */\r
 543 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 544 {\r
 545         /* Calculate the constants required to configure the tick interrupt. */\r
 546         #if configUSE_TICKLESS_IDLE == 1\r
 547         {\r
 548                 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
 549                 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
 550                 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
 551         }\r
 552         #endif /* configUSE_TICKLESS_IDLE */\r
 553 \r
 554         /* Configure SysTick to interrupt at the requested rate. */\r
 555         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
 556         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 557 }\r
 558 /*-----------------------------------------------------------*/\r
 559 \r
 560 #if( configASSERT_DEFINED == 1 )\r
 561 \r
 562         void vPortValidateInterruptPriority( void )\r
 563         {\r
 564         unsigned long ulCurrentInterrupt;\r
 565         unsigned char ucCurrentPriority;\r
 566 \r
 567                 /* Obtain the number of the currently executing interrupt. */\r
 568                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
 569 \r
 570                 /* Is the interrupt number a user defined interrupt? */\r
 571                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 572                 {\r
 573                         /* Look up the interrupt's priority. */\r
 574                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 575 \r
 576                         /* The following assertion will fail if a service routine (ISR) for \r
 577                         an interrupt that has been assigned a priority above\r
 578                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 579                         function.  ISR safe FreeRTOS API functions must *only* be called \r
 580                         from interrupts that have been assigned a priority at or below\r
 581                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 582                         \r
 583                         Numerically low interrupt priority numbers represent logically high\r
 584                         interrupt priorities, therefore the priority of the interrupt must \r
 585                         be set to a value equal to or numerically *higher* than \r
 586                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 587                         \r
 588                         Interrupts that use the FreeRTOS API must not be left at their\r
 589                         default priority of     zero as that is the highest possible priority,\r
 590                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, \r
 591                         and     therefore also guaranteed to be invalid.  \r
 592                         \r
 593                         FreeRTOS maintains separate thread and ISR API functions to ensure \r
 594                         interrupt entry is as fast and simple as possible.\r
 595                         \r
 596                         The following links provide detailed information:\r
 597                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 598                         http://www.freertos.org/FAQHelp.html */\r
 599                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 600                 }\r
 601 \r
 602                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits \r
 603                 that define each interrupt's priority to be split between bits that \r
 604                 define the interrupt's pre-emption priority bits and bits that define\r
 605                 the interrupt's sub-priority.  For simplicity all bits must be defined \r
 606                 to be pre-emption priority bits.  The following assertion will fail if\r
 607                 this is not the case (if some bits represent a sub-priority).  \r
 608                 \r
 609                 If CMSIS libraries are being used then the correct setting can be \r
 610                 achieved by calling     NVIC_SetPriorityGrouping( 0 ); before starting the \r
 611                 scheduler. */\r
 612                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) == 0 );\r
 613         }\r
 614 \r
 615 #endif /* configASSERT_DEFINED */\r
 616 \r
 617 \r
 618 \r
 619 \r
 620 \r
 621 \r
 622 \r
 623 \r
 624 \r
 625 \r
 626 \r
 627 \r
 628 \r
 629 \r
 630 \r
 631 \r
 632 \r
 633 \r
 634 \r
 635 \r
 636 \r