git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3/port.c

   1 /*\r
   2     FreeRTOS V7.5.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
   3 \r
   4     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   5 \r
   6     ***************************************************************************\r
   7      *                                                                       *\r
   8      *    FreeRTOS provides completely free yet professionally developed,    *\r
   9      *    robust, strictly quality controlled, supported, and cross          *\r
  10      *    platform software that has become a de facto standard.             *\r
  11      *                                                                       *\r
  12      *    Help yourself get started quickly and support the FreeRTOS         *\r
  13      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  14      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  15      *                                                                       *\r
  16      *    Thank you!                                                         *\r
  17      *                                                                       *\r
  18     ***************************************************************************\r
  19 \r
  20     This file is part of the FreeRTOS distribution.\r
  21 \r
  22     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  23     the terms of the GNU General Public License (version 2) as published by the\r
  24     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  25 \r
  26     >>! NOTE: The modification to the GPL is included to allow you to distribute\r
  27     >>! a combined work that includes FreeRTOS without being obliged to provide\r
  28     >>! the source code for proprietary components outside of the FreeRTOS\r
  29     >>! kernel.\r
  30 \r
  31     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  32     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  33     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  34     link: http://www.freertos.org/a00114.html\r
  35 \r
  36     1 tab == 4 spaces!\r
  37 \r
  38     ***************************************************************************\r
  39      *                                                                       *\r
  40      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  41      *    not run, what could be wrong?"                                     *\r
  42      *                                                                       *\r
  43      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  44      *                                                                       *\r
  45     ***************************************************************************\r
  46 \r
  47     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  48     license and Real Time Engineers Ltd. contact details.\r
  49 \r
  50     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  51     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  52     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  53 \r
  54     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  55     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  56     licenses offer ticketed support, indemnification and middleware.\r
  57 \r
  58     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  59     engineered and independently SIL3 certified version for use in safety and\r
  60     mission critical applications that require provable dependability.\r
  61 \r
  62     1 tab == 4 spaces!\r
  63 */\r
  64 \r
  65 /*-----------------------------------------------------------\r
  66  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  67  *----------------------------------------------------------*/\r
  68 \r
  69 /* Scheduler includes. */\r
  70 #include "FreeRTOS.h"\r
  71 #include "task.h"\r
  72 \r
  73 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\r
  74 defined.  The value should also ensure backward compatibility.\r
  75 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */\r
  76 #ifndef configKERNEL_INTERRUPT_PRIORITY\r
  77         #define configKERNEL_INTERRUPT_PRIORITY 255\r
  78 #endif\r
  79 \r
  80 #ifndef configSYSTICK_CLOCK_HZ\r
  81         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  82 #endif\r
  83 \r
  84 /* Constants required to manipulate the core.  Registers first... */\r
  85 #define portNVIC_SYSTICK_CTRL_REG                       ( * ( ( volatile unsigned long * ) 0xe000e010 ) )\r
  86 #define portNVIC_SYSTICK_LOAD_REG                       ( * ( ( volatile unsigned long * ) 0xe000e014 ) )\r
  87 #define portNVIC_SYSTICK_CURRENT_VALUE_REG      ( * ( ( volatile unsigned long * ) 0xe000e018 ) )\r
  88 #define portNVIC_SYSPRI2_REG                            ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )\r
  89 /* ...then bits in the registers. */\r
  90 #define portNVIC_SYSTICK_CLK_BIT                        ( 1UL << 2UL )\r
  91 #define portNVIC_SYSTICK_INT_BIT                        ( 1UL << 1UL )\r
  92 #define portNVIC_SYSTICK_ENABLE_BIT                     ( 1UL << 0UL )\r
  93 #define portNVIC_SYSTICK_COUNT_FLAG_BIT         ( 1UL << 16UL )\r
  94 #define portNVIC_PENDSVCLEAR_BIT                        ( 1UL << 27UL )\r
  95 #define portNVIC_PEND_SYSTICK_CLEAR_BIT         ( 1UL << 25UL )\r
  96 \r
  97 #define portNVIC_PENDSV_PRI                                     ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
  98 #define portNVIC_SYSTICK_PRI                            ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
  99 \r
 100 /* Constants required to check the validity of an interrupt priority. */\r
 101 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
 102 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
 103 #define portAIRCR_REG                                           ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )\r
 104 #define portMAX_8_BIT_VALUE                                     ( ( unsigned char ) 0xff )\r
 105 #define portTOP_BIT_OF_BYTE                                     ( ( unsigned char ) 0x80 )\r
 106 #define portMAX_PRIGROUP_BITS                           ( ( unsigned char ) 7 )\r
 107 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
 108 #define portPRIGROUP_SHIFT                                      ( 8UL )\r
 109 \r
 110 /* Constants required to set up the initial stack. */\r
 111 #define portINITIAL_XPSR                                        ( 0x01000000UL )\r
 112 \r
 113 /* The systick is a 24-bit counter. */\r
 114 #define portMAX_24_BIT_NUMBER                           ( 0xffffffUL )\r
 115 \r
 116 /* A fiddle factor to estimate the number of SysTick counts that would have\r
 117 occurred while the SysTick counter is stopped during tickless idle\r
 118 calculations. */\r
 119 #define portMISSED_COUNTS_FACTOR                        ( 45UL )\r
 120 \r
 121 /* Each task maintains its own interrupt status in the critical nesting\r
 122 variable. */\r
 123 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
 124 \r
 125 /*\r
 126  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 127  * file is weak to allow application writers to change the timer used to\r
 128  * generate the tick interrupt.\r
 129  */\r
 130 void vPortSetupTimerInterrupt( void );\r
 131 \r
 132 /*\r
 133  * Exception handlers.\r
 134  */\r
 135 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 136 void xPortSysTickHandler( void );\r
 137 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 138 \r
 139 /*\r
 140  * Start first task is a separate function so it can be tested in isolation.\r
 141  */\r
 142 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));\r
 143 \r
 144 /*-----------------------------------------------------------*/\r
 145 \r
 146 /*\r
 147  * The number of SysTick increments that make up one tick period.\r
 148  */\r
 149 #if configUSE_TICKLESS_IDLE == 1\r
 150         static unsigned long ulTimerCountsForOneTick = 0;\r
 151 #endif /* configUSE_TICKLESS_IDLE */\r
 152 \r
 153 /*\r
 154  * The maximum number of tick periods that can be suppressed is limited by the\r
 155  * 24 bit resolution of the SysTick timer.\r
 156  */\r
 157 #if configUSE_TICKLESS_IDLE == 1\r
 158         static unsigned long xMaximumPossibleSuppressedTicks = 0;\r
 159 #endif /* configUSE_TICKLESS_IDLE */\r
 160 \r
 161 /*\r
 162  * Compensate for the CPU cycles that pass while the SysTick is stopped (low\r
 163  * power functionality only.\r
 164  */\r
 165 #if configUSE_TICKLESS_IDLE == 1\r
 166         static unsigned long ulStoppedTimerCompensation = 0;\r
 167 #endif /* configUSE_TICKLESS_IDLE */\r
 168 \r
 169 /*\r
 170  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
 171  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 172  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 173  */\r
 174 #if ( configASSERT_DEFINED == 1 )\r
 175          static unsigned char ucMaxSysCallPriority = 0;\r
 176          static unsigned long ulMaxPRIGROUPValue = 0;\r
 177          static const volatile unsigned char * const pcInterruptPriorityRegisters = ( const volatile unsigned char * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 178 #endif /* configASSERT_DEFINED */\r
 179 \r
 180 /*-----------------------------------------------------------*/\r
 181 \r
 182 /*\r
 183  * See header file for description.\r
 184  */\r
 185 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 186 {\r
 187         /* Simulate the stack frame as it would be created by a context switch\r
 188         interrupt. */\r
 189         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 190         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 191         pxTopOfStack--;\r
 192         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 193         pxTopOfStack--;\r
 194         *pxTopOfStack = 0;      /* LR */\r
 195         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 196         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 197         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 198 \r
 199         return pxTopOfStack;\r
 200 }\r
 201 /*-----------------------------------------------------------*/\r
 202 \r
 203 void vPortSVCHandler( void )\r
 204 {\r
 205         __asm volatile (\r
 206                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 207                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 208                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 209                                         "       ldmia r0!, {r4-r11}                             \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 210                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 211                                         "       mov r0, #0                                              \n"\r
 212                                         "       msr     basepri, r0                                     \n"\r
 213                                         "       orr r14, #0xd                                   \n"\r
 214                                         "       bx r14                                                  \n"\r
 215                                         "                                                                       \n"\r
 216                                         "       .align 2                                                \n"\r
 217                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 218                                 );\r
 219 }\r
 220 /*-----------------------------------------------------------*/\r
 221 \r
 222 static void prvPortStartFirstTask( void )\r
 223 {\r
 224         __asm volatile(\r
 225                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 226                                         " ldr r0, [r0]                  \n"\r
 227                                         " ldr r0, [r0]                  \n"\r
 228                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 229                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 230                                         " svc 0                                 \n" /* System call to start first task. */\r
 231                                         " nop                                   \n"\r
 232                                 );\r
 233 }\r
 234 /*-----------------------------------------------------------*/\r
 235 \r
 236 /*\r
 237  * See header file for description.\r
 238  */\r
 239 portBASE_TYPE xPortStartScheduler( void )\r
 240 {\r
 241         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\r
 242         See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 243         configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\r
 244 \r
 245         #if( configASSERT_DEFINED == 1 )\r
 246         {\r
 247                 volatile unsigned long ulOriginalPriority;\r
 248                 volatile char * const pcFirstUserPriorityRegister = ( volatile char * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 249                 volatile unsigned char ucMaxPriorityValue;\r
 250 \r
 251                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 252                 functions can be called.  ISR safe functions are those that end in\r
 253                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 254                 ensure interrupt entry is as fast and simple as possible.\r
 255 \r
 256                 Save the interrupt priority value that is about to be clobbered. */\r
 257                 ulOriginalPriority = *pcFirstUserPriorityRegister;\r
 258 \r
 259                 /* Determine the number of priority bits available.  First write to all\r
 260                 possible bits. */\r
 261                 *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
 262 \r
 263                 /* Read the value back to see how many bits stuck. */\r
 264                 ucMaxPriorityValue = *pcFirstUserPriorityRegister;\r
 265 \r
 266                 /* Use the same mask on the maximum system call priority. */\r
 267                 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
 268 \r
 269                 /* Calculate the maximum acceptable priority group value for the number\r
 270                 of bits read back. */\r
 271                 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
 272                 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
 273                 {\r
 274                         ulMaxPRIGROUPValue--;\r
 275                         ucMaxPriorityValue <<= ( unsigned char ) 0x01;\r
 276                 }\r
 277 \r
 278                 /* Shift the priority group value back to its position within the AIRCR\r
 279                 register. */\r
 280                 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
 281                 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
 282 \r
 283                 /* Restore the clobbered interrupt priority register to its original\r
 284                 value. */\r
 285                 *pcFirstUserPriorityRegister = ulOriginalPriority;\r
 286         }\r
 287         #endif /* conifgASSERT_DEFINED */\r
 288 \r
 289         /* Make PendSV and SysTick the lowest priority interrupts. */\r
 290         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 291         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 292 \r
 293         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 294         here already. */\r
 295         vPortSetupTimerInterrupt();\r
 296 \r
 297         /* Initialise the critical nesting count ready for the first task. */\r
 298         uxCriticalNesting = 0;\r
 299 \r
 300         /* Start the first task. */\r
 301         prvPortStartFirstTask();\r
 302 \r
 303         /* Should not get here! */\r
 304         return 0;\r
 305 }\r
 306 /*-----------------------------------------------------------*/\r
 307 \r
 308 void vPortEndScheduler( void )\r
 309 {\r
 310         /* It is unlikely that the CM3 port will require this function as there\r
 311         is nothing to return to.  */\r
 312 }\r
 313 /*-----------------------------------------------------------*/\r
 314 \r
 315 void vPortYield( void )\r
 316 {\r
 317         /* Set a PendSV to request a context switch. */\r
 318         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 319 \r
 320         /* Barriers are normally not required but do ensure the code is completely\r
 321         within the specified behaviour for the architecture. */\r
 322         __asm volatile( "dsb" );\r
 323         __asm volatile( "isb" );\r
 324 }\r
 325 /*-----------------------------------------------------------*/\r
 326 \r
 327 void vPortEnterCritical( void )\r
 328 {\r
 329         portDISABLE_INTERRUPTS();\r
 330         uxCriticalNesting++;\r
 331         __asm volatile( "dsb" );\r
 332         __asm volatile( "isb" );\r
 333 }\r
 334 /*-----------------------------------------------------------*/\r
 335 \r
 336 void vPortExitCritical( void )\r
 337 {\r
 338         uxCriticalNesting--;\r
 339         if( uxCriticalNesting == 0 )\r
 340         {\r
 341                 portENABLE_INTERRUPTS();\r
 342         }\r
 343 }\r
 344 /*-----------------------------------------------------------*/\r
 345 \r
 346 __attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )\r
 347 {\r
 348         __asm volatile                                                                                                          \\r
 349         (                                                                                                                                       \\r
 350                 "       mrs r0, basepri                                                                                 \n" \\r
 351                 "       mov r1, %0                                                                                              \n"     \\r
 352                 "       msr basepri, r1                                                                                 \n" \\r
 353                 "       bx lr                                                                                                   \n" \\r
 354                 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1"    \\r
 355         );\r
 356 \r
 357         /* This return will not be reached but is necessary to prevent compiler\r
 358         warnings. */\r
 359         return 0;\r
 360 }\r
 361 /*-----------------------------------------------------------*/\r
 362 \r
 363 __attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )\r
 364 {\r
 365         __asm volatile                                                                                                  \\r
 366         (                                                                                                                               \\r
 367                 "       msr basepri, r0                                                                         \n"     \\r
 368                 "       bx lr                                                                                           \n" \\r
 369                 :::"r0"                                                                                                         \\r
 370         );\r
 371 \r
 372         /* Just to avoid compiler warnings. */\r
 373         ( void ) ulNewMaskValue;\r
 374 }\r
 375 /*-----------------------------------------------------------*/\r
 376 \r
 377 void xPortPendSVHandler( void )\r
 378 {\r
 379         /* This is a naked function. */\r
 380 \r
 381         __asm volatile\r
 382         (\r
 383         "       mrs r0, psp                                                     \n"\r
 384         "                                                                               \n"\r
 385         "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 386         "       ldr     r2, [r3]                                                \n"\r
 387         "                                                                               \n"\r
 388         "       stmdb r0!, {r4-r11}                                     \n" /* Save the remaining registers. */\r
 389         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 390         "                                                                               \n"\r
 391         "       stmdb sp!, {r3, r14}                            \n"\r
 392         "       mov r0, %0                                                      \n"\r
 393         "       msr basepri, r0                                         \n"\r
 394         "       bl vTaskSwitchContext                           \n"\r
 395         "       mov r0, #0                                                      \n"\r
 396         "       msr basepri, r0                                         \n"\r
 397         "       ldmia sp!, {r3, r14}                            \n"\r
 398         "                                                                               \n"     /* Restore the context, including the critical nesting count. */\r
 399         "       ldr r1, [r3]                                            \n"\r
 400         "       ldr r0, [r1]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 401         "       ldmia r0!, {r4-r11}                                     \n" /* Pop the registers. */\r
 402         "       msr psp, r0                                                     \n"\r
 403         "       bx r14                                                          \n"\r
 404         "                                                                               \n"\r
 405         "       .align 2                                                        \n"\r
 406         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 407         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 408         );\r
 409 }\r
 410 /*-----------------------------------------------------------*/\r
 411 \r
 412 void xPortSysTickHandler( void )\r
 413 {\r
 414         /* The SysTick runs at the lowest interrupt priority, so when this interrupt\r
 415         executes all interrupts must be unmasked.  There is therefore no need to\r
 416         save and then restore the interrupt mask value as its value is already\r
 417         known. */\r
 418         ( void ) portSET_INTERRUPT_MASK_FROM_ISR();\r
 419         {\r
 420                 /* Increment the RTOS tick. */\r
 421                 if( xTaskIncrementTick() != pdFALSE )\r
 422                 {\r
 423                         /* A context switch is required.  Context switching is performed in\r
 424                         the PendSV interrupt.  Pend the PendSV interrupt. */\r
 425                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 426                 }\r
 427         }\r
 428         portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );\r
 429 }\r
 430 /*-----------------------------------------------------------*/\r
 431 \r
 432 #if configUSE_TICKLESS_IDLE == 1\r
 433 \r
 434         __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )\r
 435         {\r
 436         unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;\r
 437         portTickType xModifiableIdleTime;\r
 438 \r
 439                 /* Make sure the SysTick reload value does not overflow the counter. */\r
 440                 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\r
 441                 {\r
 442                         xExpectedIdleTime = xMaximumPossibleSuppressedTicks;\r
 443                 }\r
 444 \r
 445                 /* Stop the SysTick momentarily.  The time the SysTick is stopped for\r
 446                 is accounted for as best it can be, but using the tickless mode will\r
 447                 inevitably result in some tiny drift of the time maintained by the\r
 448                 kernel with respect to calendar time. */\r
 449                 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 450 \r
 451                 /* Calculate the reload value required to wait xExpectedIdleTime\r
 452                 tick periods.  -1 is used because this code will execute part way\r
 453                 through one of the tick periods. */\r
 454                 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\r
 455                 if( ulReloadValue > ulStoppedTimerCompensation )\r
 456                 {\r
 457                         ulReloadValue -= ulStoppedTimerCompensation;\r
 458                 }\r
 459 \r
 460                 /* Enter a critical section but don't use the taskENTER_CRITICAL()\r
 461                 method as that will mask interrupts that should exit sleep mode. */\r
 462                 __asm volatile( "cpsid i" );\r
 463 \r
 464                 /* If a context switch is pending or a task is waiting for the scheduler\r
 465                 to be unsuspended then abandon the low power entry. */\r
 466                 if( eTaskConfirmSleepModeStatus() == eAbortSleep )\r
 467                 {\r
 468                         /* Restart SysTick. */\r
 469                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 470 \r
 471                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 472                         above. */\r
 473                         __asm volatile( "cpsie i" );\r
 474                 }\r
 475                 else\r
 476                 {\r
 477                         /* Set the new reload value. */\r
 478                         portNVIC_SYSTICK_LOAD_REG = ulReloadValue;\r
 479 \r
 480                         /* Clear the SysTick count flag and set the count value back to\r
 481                         zero. */\r
 482                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 483 \r
 484                         /* Restart SysTick. */\r
 485                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 486 \r
 487                         /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\r
 488                         set its parameter to 0 to indicate that its implementation contains\r
 489                         its own wait for interrupt or wait for event instruction, and so wfi\r
 490                         should not be executed again.  However, the original expected idle\r
 491                         time variable must remain unmodified, so a copy is taken. */\r
 492                         xModifiableIdleTime = xExpectedIdleTime;\r
 493                         configPRE_SLEEP_PROCESSING( xModifiableIdleTime );\r
 494                         if( xModifiableIdleTime > 0 )\r
 495                         {\r
 496                                 __asm volatile( "dsb" );\r
 497                                 __asm volatile( "wfi" );\r
 498                                 __asm volatile( "isb" );\r
 499                         }\r
 500                         configPOST_SLEEP_PROCESSING( xExpectedIdleTime );\r
 501 \r
 502                         /* Stop SysTick.  Again, the time the SysTick is stopped for is\r
 503                         accounted for as best it can be, but using the tickless mode will\r
 504                         inevitably result in some tiny drift of the time maintained by the\r
 505                         kernel with respect to calendar time. */\r
 506                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;\r
 507 \r
 508                         /* Re-enable interrupts - see comments above the cpsid instruction()\r
 509                         above. */\r
 510                         __asm volatile( "cpsie i" );\r
 511 \r
 512                         if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\r
 513                         {\r
 514                                 /* The tick interrupt has already executed, and the SysTick\r
 515                                 count reloaded with ulReloadValue.  Reset the\r
 516                                 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\r
 517                                 period. */\r
 518                                 portNVIC_SYSTICK_LOAD_REG = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 519 \r
 520                                 /* The tick interrupt handler will already have pended the tick\r
 521                                 processing in the kernel.  As the pending tick will be\r
 522                                 processed as soon as this function exits, the tick value\r
 523                                 maintained by the tick is stepped forward by one less than the\r
 524                                 time spent waiting. */\r
 525                                 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;\r
 526                         }\r
 527                         else\r
 528                         {\r
 529                                 /* Something other than the tick interrupt ended the sleep.\r
 530                                 Work out how long the sleep lasted rounded to complete tick\r
 531                                 periods (not the ulReload value which accounted for part\r
 532                                 ticks). */\r
 533                                 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\r
 534 \r
 535                                 /* How many complete tick periods passed while the processor\r
 536                                 was waiting? */\r
 537                                 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\r
 538 \r
 539                                 /* The reload value is set to whatever fraction of a single tick\r
 540                                 period remains. */\r
 541                                 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\r
 542                         }\r
 543 \r
 544                         /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\r
 545                         again, then set portNVIC_SYSTICK_LOAD_REG back to its standard\r
 546                         value. */\r
 547                         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 548                         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 549 \r
 550                         vTaskStepTick( ulCompleteTickPeriods );\r
 551 \r
 552                         /* The counter must start by the time the reload value is reset. */\r
 553                         configASSERT( portNVIC_SYSTICK_CURRENT_VALUE_REG );\r
 554                         portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\r
 555                 }\r
 556         }\r
 557 \r
 558 #endif /* #if configUSE_TICKLESS_IDLE */\r
 559 /*-----------------------------------------------------------*/\r
 560 \r
 561 /*\r
 562  * Setup the systick timer to generate the tick interrupts at the required\r
 563  * frequency.\r
 564  */\r
 565 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 566 {\r
 567         /* Calculate the constants required to configure the tick interrupt. */\r
 568         #if configUSE_TICKLESS_IDLE == 1\r
 569         {\r
 570                 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\r
 571                 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\r
 572                 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\r
 573         }\r
 574         #endif /* configUSE_TICKLESS_IDLE */\r
 575 \r
 576         /* Configure SysTick to interrupt at the requested rate. */\r
 577         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;\r
 578         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;\r
 579 }\r
 580 /*-----------------------------------------------------------*/\r
 581 \r
 582 #if( configASSERT_DEFINED == 1 )\r
 583 \r
 584         void vPortValidateInterruptPriority( void )\r
 585         {\r
 586         unsigned long ulCurrentInterrupt;\r
 587         unsigned char ucCurrentPriority;\r
 588 \r
 589                 /* Obtain the number of the currently executing interrupt. */\r
 590                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
 591 \r
 592                 /* Is the interrupt number a user defined interrupt? */\r
 593                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 594                 {\r
 595                         /* Look up the interrupt's priority. */\r
 596                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 597 \r
 598                         /* The following assertion will fail if a service routine (ISR) for\r
 599                         an interrupt that has been assigned a priority above\r
 600                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 601                         function.  ISR safe FreeRTOS API functions must *only* be called\r
 602                         from interrupts that have been assigned a priority at or below\r
 603                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 604 \r
 605                         Numerically low interrupt priority numbers represent logically high\r
 606                         interrupt priorities, therefore the priority of the interrupt must\r
 607                         be set to a value equal to or numerically *higher* than\r
 608                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 609 \r
 610                         Interrupts that use the FreeRTOS API must not be left at their\r
 611                         default priority of     zero as that is the highest possible priority,\r
 612                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
 613                         and     therefore also guaranteed to be invalid.\r
 614 \r
 615                         FreeRTOS maintains separate thread and ISR API functions to ensure\r
 616                         interrupt entry is as fast and simple as possible.\r
 617 \r
 618                         The following links provide detailed information:\r
 619                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 620                         http://www.freertos.org/FAQHelp.html */\r
 621                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 622                 }\r
 623 \r
 624                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits\r
 625                 that define each interrupt's priority to be split between bits that\r
 626                 define the interrupt's pre-emption priority bits and bits that define\r
 627                 the interrupt's sub-priority.  For simplicity all bits must be defined\r
 628                 to be pre-emption priority bits.  The following assertion will fail if\r
 629                 this is not the case (if some bits represent a sub-priority).\r
 630 \r
 631                 If the application only uses CMSIS libraries for interrupt\r
 632                 configuration then the correct setting can be achieved on all Cortex-M\r
 633                 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
 634                 scheduler.  Note however that some vendor specific peripheral libraries\r
 635                 assume a non-zero priority group setting, in which cases using a value\r
 636                 of zero will result in unpredicable behaviour. */\r
 637                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
 638         }\r
 639 \r
 640 #endif /* configASSERT_DEFINED */\r
 641 \r
 642 \r
 643 \r
 644 \r
 645 \r
 646 \r
 647 \r
 648 \r
 649 \r
 650 \r
 651 \r
 652 \r
 653 \r
 654 \r
 655 \r
 656 \r
 657 \r
 658 \r
 659 \r
 660 \r
 661 \r