git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c

   1 /*\r
   2  * FreeRTOS Kernel V10.2.0\r
   3  * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software.\r
  14  *\r
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21  *\r
  22  * http://www.FreeRTOS.org\r
  23  * http://aws.amazon.com/freertos\r
  24  *\r
  25  * 1 tab == 4 spaces!\r
  26  */\r
  27 \r
  28 /* Standard includes. */\r
  29 #include <stdint.h>\r
  30 \r
  31 /* Portasm includes. */\r
  32 #include "portasm.h"\r
  33 \r
  34 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
  35 {\r
  36     __asm volatile\r
  37     (\r
  38     "    .syntax unified                                \n"\r
  39     "                                                   \n"\r
  40     "    ldr  r2, pxCurrentTCBConst2                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
  41     "    ldr  r1, [r2]                                  \n" /* Read pxCurrentTCB. */\r
  42     "    ldr  r0, [r1]                                  \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
  43     "                                                   \n"\r
  44     #if( configENABLE_MPU == 1 )\r
  45     "    adds r1, #4                                    \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
  46     "    ldr  r3, [r1]                                  \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
  47     "    ldr  r2, xMAIR0Const2                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
  48     "    str  r3, [r2]                                  \n" /* Program MAIR0. */\r
  49     "    ldr  r2, xRNRConst2                            \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
  50     "    movs r3, #4                                    \n" /* r3 = 4. */\r
  51     "    str  r3, [r2]                                  \n" /* Program RNR = 4. */\r
  52     "    adds r1, #4                                    \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
  53     "    ldr  r2, xRBARConst2                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
  54     "    ldmia r1!, {r4-r11}                            \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
  55     "    stmia r2!, {r4-r11}                            \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
  56     #endif /* configENABLE_MPU */\r
  57     "                                                   \n"\r
  58     #if( configENABLE_MPU == 1 )\r
  59     "    ldm  r0!, {r1-r3}                              \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
  60     "    msr  psplim, r1                                \n" /* Set this task's PSPLIM value. */\r
  61     "    msr  control, r2                               \n" /* Set this task's CONTROL value. */\r
  62     "    adds r0, #32                                   \n" /* Discard everything up to r0. */\r
  63     "    msr  psp, r0                                   \n" /* This is now the new top of stack to use in the task. */\r
  64     "    isb                                            \n"\r
  65     "    bx   r3                                        \n" /* Finally, branch to EXC_RETURN. */\r
  66     #else /* configENABLE_MPU */\r
  67     "    ldm  r0!, {r1-r2}                              \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
  68     "    msr  psplim, r1                                \n" /* Set this task's PSPLIM value. */\r
  69     "    movs r1, #2                                    \n" /* r1 = 2. */\r
  70     "    msr  CONTROL, r1                               \n" /* Switch to use PSP in the thread mode. */\r
  71     "    adds r0, #32                                   \n" /* Discard everything up to r0. */\r
  72     "    msr  psp, r0                                   \n" /* This is now the new top of stack to use in the task. */\r
  73     "    isb                                            \n"\r
  74     "    bx   r2                                        \n" /* Finally, branch to EXC_RETURN. */\r
  75     #endif /* configENABLE_MPU */\r
  76     "                                                   \n"\r
  77     "    .align 4                                       \n"\r
  78     "pxCurrentTCBConst2: .word pxCurrentTCB             \n"\r
  79     #if( configENABLE_MPU == 1 )\r
  80     "xMAIR0Const2: .word 0xe000edc0                     \n"\r
  81     "xRNRConst2: .word 0xe000ed98                       \n"\r
  82     "xRBARConst2: .word 0xe000ed9c                      \n"\r
  83     #endif /* configENABLE_MPU */\r
  84     );\r
  85 }\r
  86 /*-----------------------------------------------------------*/\r
  87 \r
  88 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
  89 {\r
  90     __asm volatile\r
  91     (\r
  92     "    mrs r0, control                                \n" /* r0 = CONTROL. */\r
  93     "    tst r0, #1                                     \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
  94     "    ite ne                                         \n"\r
  95     "    movne r0, #0                                   \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
  96     "    moveq r0, #1                                   \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
  97     "    bx lr                                          \n" /* Return. */\r
  98     "                                                   \n"\r
  99     "    .align 4                                       \n"\r
 100     ::: "r0", "memory"\r
 101     );\r
 102 }\r
 103 /*-----------------------------------------------------------*/\r
 104 \r
 105 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 106 {\r
 107      __asm volatile\r
 108     (\r
 109     "    mrs  r0, control                               \n" /* Read the CONTROL register. */\r
 110     "    bic r0, #1                                     \n" /* Clear the bit 0. */\r
 111     "    msr  control, r0                               \n" /* Write back the new CONTROL value. */\r
 112     "    bx lr                                          \n" /* Return to the caller. */\r
 113     ::: "r0", "memory"\r
 114     );\r
 115 }\r
 116 /*-----------------------------------------------------------*/\r
 117 \r
 118 void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
 119 {\r
 120     __asm volatile\r
 121     (\r
 122     "    mrs r0, control                                \n" /* r0 = CONTROL. */\r
 123     "    orr r0, #1                                     \n" /* r0 = r0 | 1. */\r
 124     "    msr control, r0                                \n" /* CONTROL = r0. */\r
 125     "    bx lr                                          \n" /* Return to the caller. */\r
 126     :::"r0", "memory"\r
 127     );\r
 128 }\r
 129 /*-----------------------------------------------------------*/\r
 130 \r
 131 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 132 {\r
 133     __asm volatile\r
 134     (\r
 135     "    ldr r0, xVTORConst                             \n" /* Use the NVIC offset register to locate the stack. */\r
 136     "    ldr r0, [r0]                                   \n" /* Read the VTOR register which gives the address of vector table. */\r
 137     "    ldr r0, [r0]                                   \n" /* The first entry in vector table is stack pointer. */\r
 138     "    msr msp, r0                                    \n" /* Set the MSP back to the start of the stack. */\r
 139     "    cpsie i                                        \n" /* Globally enable interrupts. */\r
 140     "    cpsie f                                        \n"\r
 141     "    dsb                                            \n"\r
 142     "    isb                                            \n"\r
 143     "    svc %0                                         \n" /* System call to start the first task. */\r
 144     "    nop                                            \n"\r
 145     "                                                   \n"\r
 146     "   .align 4                                        \n"\r
 147     "xVTORConst: .word 0xe000ed08                       \n"\r
 148     :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
 149     );\r
 150 }\r
 151 /*-----------------------------------------------------------*/\r
 152 \r
 153 uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
 154 {\r
 155     __asm volatile\r
 156     (\r
 157     "    mrs r0, PRIMASK                                \n"\r
 158     "    cpsid i                                        \n"\r
 159     "    bx lr                                          \n"\r
 160     ::: "memory"\r
 161     );\r
 162 \r
 163 #if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
 164     /* To avoid compiler warnings.  The return statement will never be reached,\r
 165      * but some compilers warn if it is not included, while others won't compile\r
 166      * if it is. */\r
 167     return 0;\r
 168 #endif\r
 169 }\r
 170 /*-----------------------------------------------------------*/\r
 171 \r
 172 void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
 173 {\r
 174     __asm volatile\r
 175     (\r
 176     "    msr PRIMASK, r0                                \n"\r
 177     "    bx lr                                          \n"\r
 178     ::: "memory"\r
 179     );\r
 180 \r
 181 #if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
 182     /* Just to avoid compiler warning.  ulMask is used from the asm code but\r
 183      * the compiler can't see that.  Some compilers generate warnings without\r
 184      * the following line, while others generate warnings if the line is\r
 185      * included. */\r
 186     ( void ) ulMask;\r
 187 #endif\r
 188 }\r
 189 /*-----------------------------------------------------------*/\r
 190 \r
 191 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 192 {\r
 193     __asm volatile\r
 194     (\r
 195     "    .syntax unified                                \n"\r
 196     "                                                   \n"\r
 197     "    mrs r0, psp                                    \n" /* Read PSP in r0. */\r
 198     #if( configENABLE_FPU == 1 )\r
 199     "    tst lr, #0x10                                  \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
 200     "    it eq                                          \n"\r
 201     "    vstmdbeq r0!, {s16-s31}                        \n" /* Store the FPU registers which are not saved automatically. */\r
 202     #endif /* configENABLE_FPU */\r
 203     #if( configENABLE_MPU == 1 )\r
 204     "    mrs r1, psplim                                 \n" /* r1 = PSPLIM. */\r
 205     "    mrs r2, control                                \n" /* r2 = CONTROL. */\r
 206     "    mov r3, lr                                     \n" /* r3 = LR/EXC_RETURN. */\r
 207     "    stmdb r0!, {r1-r11}                            \n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
 208     #else /* configENABLE_MPU */\r
 209     "    mrs r2, psplim                                 \n" /* r2 = PSPLIM. */\r
 210     "    mov r3, lr                                     \n" /* r3 = LR/EXC_RETURN. */\r
 211     "    stmdb r0!, {r2-r11}                            \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */\r
 212     #endif /* configENABLE_MPU */\r
 213     "                                                   \n"\r
 214     "    ldr r2, pxCurrentTCBConst                      \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 215     "    ldr r1, [r2]                                   \n" /* Read pxCurrentTCB. */\r
 216     "    str r0, [r1]                                   \n" /* Save the new top of stack in TCB. */\r
 217     "                                                   \n"\r
 218     "    cpsid i                                        \n"\r
 219     "    bl vTaskSwitchContext                          \n"\r
 220     "    cpsie i                                        \n"\r
 221     "                                                   \n"\r
 222     "    ldr r2, pxCurrentTCBConst                      \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 223     "    ldr r1, [r2]                                   \n" /* Read pxCurrentTCB. */\r
 224     "    ldr r0, [r1]                                   \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
 225     "                                                   \n"\r
 226     #if( configENABLE_MPU == 1 )\r
 227     "    adds r1, #4                                    \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
 228     "    ldr r3, [r1]                                   \n" /* r3 = *r1 i.e. r3 = MAIR0. */\r
 229     "    ldr r2, xMAIR0Const                            \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
 230     "    str r3, [r2]                                   \n" /* Program MAIR0. */\r
 231     "    ldr r2, xRNRConst                              \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
 232     "    movs r3, #4                                    \n" /* r3 = 4. */\r
 233     "    str r3, [r2]                                   \n" /* Program RNR = 4. */\r
 234     "    adds r1, #4                                    \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
 235     "    ldr r2, xRBARConst                             \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
 236     "    ldmia r1!, {r4-r11}                            \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
 237     "    stmia r2!, {r4-r11}                            \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
 238     #endif /* configENABLE_MPU */\r
 239     "                                                   \n"\r
 240     #if( configENABLE_MPU == 1 )\r
 241     "    ldmia r0!, {r1-r11}                            \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
 242     #else /* configENABLE_MPU */\r
 243     "    ldmia r0!, {r2-r11}                            \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
 244     #endif /* configENABLE_MPU */\r
 245     "                                                   \n"\r
 246     #if( configENABLE_FPU == 1 )\r
 247     "    tst r3, #0x10                                  \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
 248     "    it eq                                          \n"\r
 249     "    vldmiaeq r0!, {s16-s31}                        \n" /* Restore the FPU registers which are not restored automatically. */\r
 250     #endif /* configENABLE_FPU */\r
 251     "                                                   \n"\r
 252     #if( configENABLE_MPU == 1 )\r
 253     "    msr psplim, r1                                 \n" /* Restore the PSPLIM register value for the task. */\r
 254     "    msr control, r2                                \n" /* Restore the CONTROL register value for the task. */\r
 255     #else /* configENABLE_MPU */\r
 256     "    msr psplim, r2                                 \n" /* Restore the PSPLIM register value for the task. */\r
 257     #endif /* configENABLE_MPU */\r
 258     "    msr psp, r0                                    \n" /* Remember the new top of stack for the task. */\r
 259     "    bx r3                                          \n"\r
 260     "                                                   \n"\r
 261     "    .align 4                                       \n"\r
 262     "pxCurrentTCBConst: .word pxCurrentTCB              \n"\r
 263     "xMAIR0Const: .word 0xe000edc0                      \n"\r
 264     "xRNRConst: .word 0xe000ed98                        \n"\r
 265     "xRBARConst: .word 0xe000ed9c                       \n"\r
 266     );\r
 267 }\r
 268 /*-----------------------------------------------------------*/\r
 269 \r
 270 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 271 {\r
 272     __asm volatile\r
 273     (\r
 274     "     tst lr, #4                                    \n"\r
 275     "     ite eq                                        \n"\r
 276     "     mrseq r0, msp                                 \n"\r
 277     "     mrsne r0, psp                                 \n"\r
 278     "     ldr r1, svchandler_address_const              \n"\r
 279     "     bx r1                                         \n"\r
 280     "                                                   \n"\r
 281     "     .align 4                                      \n"\r
 282     "svchandler_address_const: .word vPortSVCHandler_C  \n"\r
 283     );\r
 284 }\r
 285 /*-----------------------------------------------------------*/\r