git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c

   1 /*\r
   2     FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
   3 \r
   4 \r
   5     ***************************************************************************\r
   6      *                                                                       *\r
   7      *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
   8      *    Complete, revised, and edited pdf reference manuals are also       *\r
   9      *    available.                                                         *\r
  10      *                                                                       *\r
  11      *    Purchasing FreeRTOS documentation will not only help you, by       *\r
  12      *    ensuring you get running as quickly as possible and with an        *\r
  13      *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
  14      *    the FreeRTOS project to continue with its mission of providing     *\r
  15      *    professional grade, cross platform, de facto standard solutions    *\r
  16      *    for microcontrollers - completely free of charge!                  *\r
  17      *                                                                       *\r
  18      *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
  19      *                                                                       *\r
  20      *    Thank you for using FreeRTOS, and thank you for your support!      *\r
  21      *                                                                       *\r
  22     ***************************************************************************\r
  23 \r
  24 \r
  25     This file is part of the FreeRTOS distribution.\r
  26 \r
  27     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  28     the terms of the GNU General Public License (version 2) as published by the\r
  29     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
  30     >>>NOTE<<< The modification to the GPL is included to allow you to\r
  31     distribute a combined work that includes FreeRTOS without being obliged to\r
  32     provide the source code for proprietary components outside of the FreeRTOS\r
  33     kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
  34     WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
  35     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
  36     more details. You should have received a copy of the GNU General Public\r
  37     License and the FreeRTOS license exception along with FreeRTOS; if not it\r
  38     can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
  39     by writing to Richard Barry, contact details for whom are available on the\r
  40     FreeRTOS WEB site.\r
  41 \r
  42     1 tab == 4 spaces!\r
  43 \r
  44     ***************************************************************************\r
  45      *                                                                       *\r
  46      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  47      *    not run, what could be wrong?                                      *\r
  48      *                                                                       *\r
  49      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  50      *                                                                       *\r
  51     ***************************************************************************\r
  52 \r
  53 \r
  54     http://www.FreeRTOS.org - Documentation, training, latest information,\r
  55     license and contact details.\r
  56 \r
  57     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  58     including FreeRTOS+Trace - an indispensable productivity tool.\r
  59 \r
  60     Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell\r
  61     the code with commercial support, indemnification, and middleware, under\r
  62     the OpenRTOS brand: http://www.OpenRTOS.com.  High Integrity Systems also\r
  63     provide a safety engineered and independently SIL3 certified version under\r
  64     the SafeRTOS brand: http://www.SafeRTOS.com.\r
  65 */\r
  66 \r
  67 /*-----------------------------------------------------------\r
  68  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  69  *----------------------------------------------------------*/\r
  70 \r
  71 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
  72 all the API functions to use the MPU wrappers.  That should only be done when\r
  73 task.h is included from an application file. */\r
  74 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  75 \r
  76 /* Scheduler includes. */\r
  77 #include "FreeRTOS.h"\r
  78 #include "task.h"\r
  79 #include "queue.h"\r
  80 \r
  81 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  82 \r
  83 /* Constants required to access and manipulate the NVIC. */\r
  84 #define portNVIC_SYSTICK_CTRL                                   ( ( volatile unsigned long * ) 0xe000e010 )\r
  85 #define portNVIC_SYSTICK_LOAD                                   ( ( volatile unsigned long * ) 0xe000e014 )\r
  86 #define portNVIC_SYSPRI2                                                ( ( volatile unsigned long * ) 0xe000ed20 )\r
  87 #define portNVIC_SYSPRI1                                                ( ( volatile unsigned long * ) 0xe000ed1c )\r
  88 #define portNVIC_SYS_CTRL_STATE                                 ( ( volatile unsigned long * ) 0xe000ed24 )\r
  89 #define portNVIC_MEM_FAULT_ENABLE                               ( 1UL << 16UL )\r
  90 \r
  91 /* Constants required to access and manipulate the MPU. */\r
  92 #define portMPU_TYPE                                                    ( ( volatile unsigned long * ) 0xe000ed90 )\r
  93 #define portMPU_REGION_BASE_ADDRESS                             ( ( volatile unsigned long * ) 0xe000ed9C )\r
  94 #define portMPU_REGION_ATTRIBUTE                                ( ( volatile unsigned long * ) 0xe000edA0 )\r
  95 #define portMPU_CTRL                                                    ( ( volatile unsigned long * ) 0xe000ed94 )\r
  96 #define portEXPECTED_MPU_TYPE_VALUE                             ( 8UL << 8UL ) /* 8 regions, unified. */\r
  97 #define portMPU_ENABLE                                                  ( 0x01UL )\r
  98 #define portMPU_BACKGROUND_ENABLE                               ( 1UL << 2UL )\r
  99 #define portPRIVILEGED_EXECUTION_START_ADDRESS  ( 0UL )\r
 100 #define portMPU_REGION_VALID                                    ( 0x10UL )\r
 101 #define portMPU_REGION_ENABLE                                   ( 0x01UL )\r
 102 #define portPERIPHERALS_START_ADDRESS                   0x40000000UL\r
 103 #define portPERIPHERALS_END_ADDRESS                             0x5FFFFFFFUL\r
 104 \r
 105 /* Constants required to access and manipulate the SysTick. */\r
 106 #define portNVIC_SYSTICK_CLK                                    ( 0x00000004UL )\r
 107 #define portNVIC_SYSTICK_INT                                    ( 0x00000002UL )\r
 108 #define portNVIC_SYSTICK_ENABLE                                 ( 0x00000001UL )\r
 109 #define portNVIC_PENDSV_PRI                                             ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 110 #define portNVIC_SYSTICK_PRI                                    ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 111 #define portNVIC_SVC_PRI                                                ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 112 \r
 113 /* Constants required to set up the initial stack. */\r
 114 #define portINITIAL_XPSR                                                ( 0x01000000 )\r
 115 #define portINITIAL_CONTROL_IF_UNPRIVILEGED             ( 0x03 )\r
 116 #define portINITIAL_CONTROL_IF_PRIVILEGED               ( 0x02 )\r
 117 \r
 118 /* Offsets in the stack to the parameters when inside the SVC handler. */\r
 119 #define portOFFSET_TO_PC                                                ( 6 )\r
 120 \r
 121 /* Set the privilege level to user mode if xRunningPrivileged is false. */\r
 122 #define portRESET_PRIVILEGE( xRunningPrivileged ) if( xRunningPrivileged != pdTRUE ) __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0" :::"r0" )\r
 123 \r
 124 /* Each task maintains its own interrupt status in the critical nesting\r
 125 variable.  Note this is not saved as part of the task context as context\r
 126 switches can only occur when uxCriticalNesting is zero. */\r
 127 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
 128 \r
 129 /*\r
 130  * Setup the timer to generate the tick interrupts.\r
 131  */\r
 132 static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
 133 \r
 134 /*\r
 135  * Configure a number of standard MPU regions that are used by all tasks.\r
 136  */\r
 137 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
 138 \r
 139 /*\r
 140  * Return the smallest MPU region size that a given number of bytes will fit\r
 141  * into.  The region size is returned as the value that should be programmed\r
 142  * into the region attribute register for that region.\r
 143  */\r
 144 static unsigned long prvGetMPURegionSizeSetting( unsigned long ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
 145 \r
 146 /*\r
 147  * Checks to see if being called from the context of an unprivileged task, and\r
 148  * if so raises the privilege level and returns false - otherwise does nothing\r
 149  * other than return true.\r
 150  */\r
 151 static portBASE_TYPE prvRaisePrivilege( void ) __attribute__(( naked ));\r
 152 \r
 153 /*\r
 154  * Standard FreeRTOS exception handlers.\r
 155  */\r
 156 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 157 void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;\r
 158 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 159 \r
 160 /*\r
 161  * Starts the scheduler by restoring the context of the first task to run.\r
 162  */\r
 163 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
 164 \r
 165 /*\r
 166  * C portion of the SVC handler.  The SVC handler is split between an asm entry\r
 167  * and a C wrapper for simplicity of coding and maintenance.\r
 168  */\r
 169 static void prvSVCHandler( unsigned long *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
 170 \r
 171 /*\r
 172  * Prototypes for all the MPU wrappers.\r
 173  */\r
 174 signed portBASE_TYPE MPU_xTaskGenericCreate( pdTASK_CODE pvTaskCode, const signed char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions );\r
 175 void MPU_vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const xRegions );\r
 176 void MPU_vTaskDelete( xTaskHandle pxTaskToDelete );\r
 177 void MPU_vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement );\r
 178 void MPU_vTaskDelay( portTickType xTicksToDelay );\r
 179 unsigned portBASE_TYPE MPU_uxTaskPriorityGet( xTaskHandle pxTask );\r
 180 void MPU_vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );\r
 181 void MPU_vTaskSuspend( xTaskHandle pxTaskToSuspend );\r
 182 signed portBASE_TYPE MPU_xTaskIsTaskSuspended( xTaskHandle xTask );\r
 183 void MPU_vTaskResume( xTaskHandle pxTaskToResume );\r
 184 void MPU_vTaskSuspendAll( void );\r
 185 signed portBASE_TYPE MPU_xTaskResumeAll( void );\r
 186 portTickType MPU_xTaskGetTickCount( void );\r
 187 unsigned portBASE_TYPE MPU_uxTaskGetNumberOfTasks( void );\r
 188 void MPU_vTaskList( signed char *pcWriteBuffer );\r
 189 void MPU_vTaskGetRunTimeStats( signed char *pcWriteBuffer );\r
 190 void MPU_vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxTagValue );\r
 191 pdTASK_HOOK_CODE MPU_xTaskGetApplicationTaskTag( xTaskHandle xTask );\r
 192 portBASE_TYPE MPU_xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter );\r
 193 unsigned portBASE_TYPE MPU_uxTaskGetStackHighWaterMark( xTaskHandle xTask );\r
 194 xTaskHandle MPU_xTaskGetCurrentTaskHandle( void );\r
 195 portBASE_TYPE MPU_xTaskGetSchedulerState( void );\r
 196 xQueueHandle MPU_xQueueGenericCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize, unsigned char ucQueueType );\r
 197 signed portBASE_TYPE MPU_xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition );\r
 198 unsigned portBASE_TYPE MPU_uxQueueMessagesWaiting( const xQueueHandle pxQueue );\r
 199 signed portBASE_TYPE MPU_xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking );\r
 200 xQueueHandle MPU_xQueueCreateMutex( void );\r
 201 xQueueHandle MPU_xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount );\r
 202 portBASE_TYPE MPU_xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime );\r
 203 portBASE_TYPE MPU_xQueueGiveMutexRecursive( xQueueHandle xMutex );\r
 204 signed portBASE_TYPE MPU_xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition );\r
 205 signed portBASE_TYPE MPU_xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking );\r
 206 void MPU_vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcName );\r
 207 void MPU_vQueueDelete( xQueueHandle xQueue );\r
 208 void *MPU_pvPortMalloc( size_t xSize );\r
 209 void MPU_vPortFree( void *pv );\r
 210 void MPU_vPortInitialiseBlocks( void );\r
 211 size_t MPU_xPortGetFreeHeapSize( void );\r
 212 \r
 213 /*-----------------------------------------------------------*/\r
 214 \r
 215 /*\r
 216  * See header file for description.\r
 217  */\r
 218 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters, portBASE_TYPE xRunPrivileged )\r
 219 {\r
 220         /* Simulate the stack frame as it would be created by a context switch\r
 221         interrupt. */\r
 222         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 223         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 224         pxTopOfStack--;\r
 225         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 226         pxTopOfStack--;\r
 227         *pxTopOfStack = 0;      /* LR */\r
 228         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 229         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 230         pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 231 \r
 232         if( xRunPrivileged == pdTRUE )\r
 233         {\r
 234                 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\r
 235         }\r
 236         else\r
 237         {\r
 238                 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\r
 239         }\r
 240 \r
 241         return pxTopOfStack;\r
 242 }\r
 243 /*-----------------------------------------------------------*/\r
 244 \r
 245 void vPortSVCHandler( void )\r
 246 {\r
 247         /* Assumes psp was in use. */\r
 248         __asm volatile\r
 249         (\r
 250                 #ifndef USE_PROCESS_STACK       /* Code should not be required if a main() is using the process stack. */\r
 251                         "       tst lr, #4                                              \n"\r
 252                         "       ite eq                                                  \n"\r
 253                         "       mrseq r0, msp                                   \n"\r
 254                         "       mrsne r0, psp                                   \n"\r
 255                 #else\r
 256                         "       mrs r0, psp                                             \n"\r
 257                 #endif\r
 258                         "       b %0                                                    \n"\r
 259                         ::"i"(prvSVCHandler):"r0"\r
 260         );\r
 261 }\r
 262 /*-----------------------------------------------------------*/\r
 263 \r
 264 static void prvSVCHandler(      unsigned long *pulParam )\r
 265 {\r
 266 unsigned char ucSVCNumber;\r
 267 \r
 268         /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and\r
 269         xPSR.  The first argument (r0) is pulParam[ 0 ]. */\r
 270         ucSVCNumber = ( ( unsigned char * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];\r
 271         switch( ucSVCNumber )\r
 272         {\r
 273                 case portSVC_START_SCHEDULER    :       *(portNVIC_SYSPRI1) |= portNVIC_SVC_PRI;\r
 274                                                                                         prvRestoreContextOfFirstTask();\r
 275                                                                                         break;\r
 276 \r
 277                 case portSVC_YIELD                              :       *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 278                                                                                         break;\r
 279 \r
 280                 case portSVC_RAISE_PRIVILEGE    :       __asm volatile\r
 281                                                                                         (\r
 282                                                                                                 "       mrs r1, control         \n" /* Obtain current control value. */\r
 283                                                                                                 "       bic r1, #1                      \n" /* Set privilege bit. */\r
 284                                                                                                 "       msr control, r1         \n" /* Write back new control value. */\r
 285                                                                                                 :::"r1"\r
 286                                                                                         );\r
 287                                                                                         break;\r
 288 \r
 289                 default                                                 :       /* Unknown SVC call. */\r
 290                                                                                         break;\r
 291         }\r
 292 }\r
 293 /*-----------------------------------------------------------*/\r
 294 \r
 295 static void prvRestoreContextOfFirstTask( void )\r
 296 {\r
 297         __asm volatile\r
 298         (\r
 299                 "       ldr r0, =0xE000ED08                             \n" /* Use the NVIC offset register to locate the stack. */\r
 300                 "       ldr r0, [r0]                                    \n"\r
 301                 "       ldr r0, [r0]                                    \n"\r
 302                 "       msr msp, r0                                             \n" /* Set the msp back to the start of the stack. */\r
 303                 "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 304                 "       ldr r1, [r3]                                    \n"\r
 305                 "       ldr r0, [r1]                                    \n" /* The first item in the TCB is the task top of stack. */\r
 306                 "       add r1, r1, #4                                  \n" /* Move onto the second item in the TCB... */\r
 307                 "       ldr r2, =0xe000ed9c                             \n" /* Region Base Address register. */\r
 308                 "       ldmia r1!, {r4-r11}                             \n" /* Read 4 sets of MPU registers. */\r
 309                 "       stmia r2!, {r4-r11}                             \n" /* Write 4 sets of MPU registers. */\r
 310                 "       ldmia r0!, {r3, r4-r11}                 \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 311                 "       msr control, r3                                 \n"\r
 312                 "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 313                 "       mov r0, #0                                              \n"\r
 314                 "       msr     basepri, r0                                     \n"\r
 315                 "       ldr r14, =0xfffffffd                    \n" /* Load exec return code. */\r
 316                 "       bx r14                                                  \n"\r
 317                 "                                                                       \n"\r
 318                 "       .align 2                                                \n"\r
 319                 "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
 320         );\r
 321 }\r
 322 /*-----------------------------------------------------------*/\r
 323 \r
 324 /*\r
 325  * See header file for description.\r
 326  */\r
 327 portBASE_TYPE xPortStartScheduler( void )\r
 328 {\r
 329         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See\r
 330         http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 331         configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\r
 332 \r
 333         /* Make PendSV and SysTick the same priority as the kernel. */\r
 334         *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
 335         *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
 336 \r
 337         /* Configure the regions in the MPU that are common to all tasks. */\r
 338         prvSetupMPU();\r
 339 \r
 340         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 341         here already. */\r
 342         prvSetupTimerInterrupt();\r
 343 \r
 344         /* Initialise the critical nesting count ready for the first task. */\r
 345         uxCriticalNesting = 0;\r
 346 \r
 347         /* Start the first task. */\r
 348         __asm volatile( "       svc %0                  \n"\r
 349                                         :: "i" (portSVC_START_SCHEDULER) );\r
 350 \r
 351         /* Should not get here! */\r
 352         return 0;\r
 353 }\r
 354 /*-----------------------------------------------------------*/\r
 355 \r
 356 void vPortEndScheduler( void )\r
 357 {\r
 358         /* It is unlikely that the CM3 port will require this function as there\r
 359         is nothing to return to.  */\r
 360 }\r
 361 /*-----------------------------------------------------------*/\r
 362 \r
 363 void vPortEnterCritical( void )\r
 364 {\r
 365 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 366 \r
 367         portDISABLE_INTERRUPTS();\r
 368         uxCriticalNesting++;\r
 369 \r
 370         portRESET_PRIVILEGE( xRunningPrivileged );\r
 371 }\r
 372 /*-----------------------------------------------------------*/\r
 373 \r
 374 void vPortExitCritical( void )\r
 375 {\r
 376 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 377 \r
 378         uxCriticalNesting--;\r
 379         if( uxCriticalNesting == 0 )\r
 380         {\r
 381                 portENABLE_INTERRUPTS();\r
 382         }\r
 383         portRESET_PRIVILEGE( xRunningPrivileged );\r
 384 }\r
 385 /*-----------------------------------------------------------*/\r
 386 \r
 387 void xPortPendSVHandler( void )\r
 388 {\r
 389         /* This is a naked function. */\r
 390 \r
 391         __asm volatile\r
 392         (\r
 393                 "       mrs r0, psp                                                     \n"\r
 394                 "                                                                               \n"\r
 395                 "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 396                 "       ldr     r2, [r3]                                                \n"\r
 397                 "                                                                               \n"\r
 398                 "       mrs r1, control                                         \n"\r
 399                 "       stmdb r0!, {r1, r4-r11}                         \n" /* Save the remaining registers. */\r
 400                 "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 401                 "                                                                               \n"\r
 402                 "       stmdb sp!, {r3, r14}                            \n"\r
 403                 "       mov r0, %0                                                      \n"\r
 404                 "       msr basepri, r0                                         \n"\r
 405                 "       bl vTaskSwitchContext                           \n"\r
 406                 "       mov r0, #0                                                      \n"\r
 407                 "       msr basepri, r0                                         \n"\r
 408                 "       ldmia sp!, {r3, r14}                            \n"\r
 409                 "                                                                               \n"     /* Restore the context. */\r
 410                 "       ldr r1, [r3]                                            \n"\r
 411                 "       ldr r0, [r1]                                            \n" /* The first item in the TCB is the task top of stack. */\r
 412                 "       add r1, r1, #4                                          \n" /* Move onto the second item in the TCB... */\r
 413                 "       ldr r2, =0xe000ed9c                                     \n" /* Region Base Address register. */\r
 414                 "       ldmia r1!, {r4-r11}                                     \n" /* Read 4 sets of MPU registers. */\r
 415                 "       stmia r2!, {r4-r11}                                     \n" /* Write 4 sets of MPU registers. */\r
 416                 "       ldmia r0!, {r3, r4-r11}                         \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 417                 "       msr control, r3                                         \n"\r
 418                 "                                                                               \n"\r
 419                 "       msr psp, r0                                                     \n"\r
 420                 "       bx r14                                                          \n"\r
 421                 "                                                                               \n"\r
 422                 "       .align 2                                                        \n"\r
 423                 "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 424                 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 425         );\r
 426 }\r
 427 /*-----------------------------------------------------------*/\r
 428 \r
 429 void xPortSysTickHandler( void )\r
 430 {\r
 431 unsigned long ulDummy;\r
 432 \r
 433         /* If using preemption, also force a context switch. */\r
 434         #if configUSE_PREEMPTION == 1\r
 435                 *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 436         #endif\r
 437 \r
 438         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
 439         {\r
 440                 vTaskIncrementTick();\r
 441         }\r
 442         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
 443 }\r
 444 /*-----------------------------------------------------------*/\r
 445 \r
 446 /*\r
 447  * Setup the systick timer to generate the tick interrupts at the required\r
 448  * frequency.\r
 449  */\r
 450 static void prvSetupTimerInterrupt( void )\r
 451 {\r
 452         /* Configure SysTick to interrupt at the requested rate. */\r
 453         *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 454         *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
 455 }\r
 456 /*-----------------------------------------------------------*/\r
 457 \r
 458 static void prvSetupMPU( void )\r
 459 {\r
 460 extern unsigned long __privileged_functions_end__[];\r
 461 extern unsigned long __FLASH_segment_start__[];\r
 462 extern unsigned long __FLASH_segment_end__[];\r
 463 extern unsigned long __privileged_data_start__[];\r
 464 extern unsigned long __privileged_data_end__[];\r
 465 \r
 466         /* Check the expected MPU is present. */\r
 467         if( *portMPU_TYPE == portEXPECTED_MPU_TYPE_VALUE )\r
 468         {\r
 469                 /* First setup the entire flash for unprivileged read only access. */\r
 470         *portMPU_REGION_BASE_ADDRESS =  ( ( unsigned long ) __FLASH_segment_start__ ) | /* Base address. */\r
 471                                                                                 ( portMPU_REGION_VALID ) |\r
 472                                                                                 ( portUNPRIVILEGED_FLASH_REGION );\r
 473 \r
 474                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_READ_ONLY ) |\r
 475                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 476                                                                                 ( prvGetMPURegionSizeSetting( ( unsigned long ) __FLASH_segment_end__ - ( unsigned long ) __FLASH_segment_start__ ) ) |\r
 477                                                                                 ( portMPU_REGION_ENABLE );\r
 478 \r
 479                 /* Setup the first 16K for privileged only access (even though less\r
 480                 than 10K is actually being used).  This is where the kernel code is\r
 481                 placed. */\r
 482         *portMPU_REGION_BASE_ADDRESS =  ( ( unsigned long ) __FLASH_segment_start__ ) | /* Base address. */\r
 483                                                                                 ( portMPU_REGION_VALID ) |\r
 484                                                                                 ( portPRIVILEGED_FLASH_REGION );\r
 485 \r
 486                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
 487                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 488                                                                                 ( prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_functions_end__ - ( unsigned long ) __FLASH_segment_start__ ) ) |\r
 489                                                                                 ( portMPU_REGION_ENABLE );\r
 490 \r
 491                 /* Setup the privileged data RAM region.  This is where the kernel data\r
 492                 is placed. */\r
 493                 *portMPU_REGION_BASE_ADDRESS =  ( ( unsigned long ) __privileged_data_start__ ) | /* Base address. */\r
 494                                                                                 ( portMPU_REGION_VALID ) |\r
 495                                                                                 ( portPRIVILEGED_RAM_REGION );\r
 496 \r
 497                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 498                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 499                                                                                 prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_data_end__ - ( unsigned long ) __privileged_data_start__ ) |\r
 500                                                                                 ( portMPU_REGION_ENABLE );\r
 501 \r
 502                 /* By default allow everything to access the general peripherals.  The\r
 503                 system peripherals and registers are protected. */\r
 504                 *portMPU_REGION_BASE_ADDRESS =  ( portPERIPHERALS_START_ADDRESS ) |\r
 505                                                                                 ( portMPU_REGION_VALID ) |\r
 506                                                                                 ( portGENERAL_PERIPHERALS_REGION );\r
 507 \r
 508                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
 509                                                                                 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\r
 510                                                                                 ( portMPU_REGION_ENABLE );\r
 511 \r
 512                 /* Enable the memory fault exception. */\r
 513                 *portNVIC_SYS_CTRL_STATE |= portNVIC_MEM_FAULT_ENABLE;\r
 514 \r
 515                 /* Enable the MPU with the background region configured. */\r
 516                 *portMPU_CTRL |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
 517         }\r
 518 }\r
 519 /*-----------------------------------------------------------*/\r
 520 \r
 521 static unsigned long prvGetMPURegionSizeSetting( unsigned long ulActualSizeInBytes )\r
 522 {\r
 523 unsigned long ulRegionSize, ulReturnValue = 4;\r
 524 \r
 525         /* 32 is the smallest region size, 31 is the largest valid value for\r
 526         ulReturnValue. */\r
 527         for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\r
 528         {\r
 529                 if( ulActualSizeInBytes <= ulRegionSize )\r
 530                 {\r
 531                         break;\r
 532                 }\r
 533                 else\r
 534                 {\r
 535                         ulReturnValue++;\r
 536                 }\r
 537         }\r
 538 \r
 539         /* Shift the code by one before returning so it can be written directly\r
 540         into the the correct bit position of the attribute register. */\r
 541         return ( ulReturnValue << 1UL );\r
 542 }\r
 543 /*-----------------------------------------------------------*/\r
 544 \r
 545 static portBASE_TYPE prvRaisePrivilege( void )\r
 546 {\r
 547         __asm volatile\r
 548         (\r
 549                 "       mrs r0, control                                         \n"\r
 550                 "       tst r0, #1                                                      \n" /* Is the task running privileged? */\r
 551                 "       itte ne                                                         \n"\r
 552                 "       movne r0, #0                                            \n" /* CONTROL[0]!=0, return false. */\r
 553                 "       svcne %0                                                        \n" /* Switch to privileged. */\r
 554                 "       moveq r0, #1                                            \n" /* CONTROL[0]==0, return true. */\r
 555                 "       bx lr                                                           \n"\r
 556                 :: "i" (portSVC_RAISE_PRIVILEGE) : "r0"\r
 557         );\r
 558 \r
 559         return 0;\r
 560 }\r
 561 /*-----------------------------------------------------------*/\r
 562 \r
 563 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, portSTACK_TYPE *pxBottomOfStack, unsigned short usStackDepth )\r
 564 {\r
 565 extern unsigned long __SRAM_segment_start__[];\r
 566 extern unsigned long __SRAM_segment_end__[];\r
 567 extern unsigned long __privileged_data_start__[];\r
 568 extern unsigned long __privileged_data_end__[];\r
 569 long lIndex;\r
 570 unsigned long ul;\r
 571 \r
 572         if( xRegions == NULL )\r
 573         {\r
 574                 /* No MPU regions are specified so allow access to all RAM. */\r
 575         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 576                                 ( ( unsigned long ) __SRAM_segment_start__ ) | /* Base address. */\r
 577                                 ( portMPU_REGION_VALID ) |\r
 578                                 ( portSTACK_REGION );\r
 579 \r
 580                 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 581                                 ( portMPU_REGION_READ_WRITE ) |\r
 582                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 583                                 ( prvGetMPURegionSizeSetting( ( unsigned long ) __SRAM_segment_end__ - ( unsigned long ) __SRAM_segment_start__ ) ) |\r
 584                                 ( portMPU_REGION_ENABLE );\r
 585 \r
 586                 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
 587                 just removed the privileged only parameters. */\r
 588                 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =\r
 589                                 ( ( unsigned long ) __privileged_data_start__ ) | /* Base address. */\r
 590                                 ( portMPU_REGION_VALID ) |\r
 591                                 ( portSTACK_REGION + 1 );\r
 592 \r
 593                 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =\r
 594                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 595                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 596                                 prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_data_end__ - ( unsigned long ) __privileged_data_start__ ) |\r
 597                                 ( portMPU_REGION_ENABLE );\r
 598 \r
 599                 /* Invalidate all other regions. */\r
 600                 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 601                 {\r
 602                         xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 603                         xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 604                 }\r
 605         }\r
 606         else\r
 607         {\r
 608                 /* This function is called automatically when the task is created - in\r
 609                 which case the stack region parameters will be valid.  At all other\r
 610                 times the stack parameters will not be valid and it is assumed that the\r
 611                 stack region has already been configured. */\r
 612                 if( usStackDepth > 0 )\r
 613                 {\r
 614                         /* Define the region that allows access to the stack. */\r
 615                         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 616                                         ( ( unsigned long ) pxBottomOfStack ) |\r
 617                                         ( portMPU_REGION_VALID ) |\r
 618                                         ( portSTACK_REGION ); /* Region number. */\r
 619 \r
 620                         xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 621                                         ( portMPU_REGION_READ_WRITE ) | /* Read and write. */\r
 622                                         ( prvGetMPURegionSizeSetting( ( unsigned long ) usStackDepth * ( unsigned long ) sizeof( portSTACK_TYPE ) ) ) |\r
 623                                         ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 624                                         ( portMPU_REGION_ENABLE );\r
 625                 }\r
 626 \r
 627                 lIndex = 0;\r
 628 \r
 629                 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 630                 {\r
 631                         if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\r
 632                         {\r
 633                                 /* Translate the generic region definition contained in\r
 634                                 xRegions into the CM3 specific MPU settings that are then\r
 635                                 stored in xMPUSettings. */\r
 636                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\r
 637                                                 ( ( unsigned long ) xRegions[ lIndex ].pvBaseAddress ) |\r
 638                                                 ( portMPU_REGION_VALID ) |\r
 639                                                 ( portSTACK_REGION + ul ); /* Region number. */\r
 640 \r
 641                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute =\r
 642                                                 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\r
 643                                                 ( xRegions[ lIndex ].ulParameters ) |\r
 644                                                 ( portMPU_REGION_ENABLE );\r
 645                         }\r
 646                         else\r
 647                         {\r
 648                                 /* Invalidate the region. */\r
 649                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 650                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 651                         }\r
 652 \r
 653                         lIndex++;\r
 654                 }\r
 655         }\r
 656 }\r
 657 /*-----------------------------------------------------------*/\r
 658 \r
 659 signed portBASE_TYPE MPU_xTaskGenericCreate( pdTASK_CODE pvTaskCode, const signed char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions )\r
 660 {\r
 661 signed portBASE_TYPE xReturn;\r
 662 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 663 \r
 664         xReturn = xTaskGenericCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask, puxStackBuffer, xRegions );\r
 665         portRESET_PRIVILEGE( xRunningPrivileged );\r
 666         return xReturn;\r
 667 }\r
 668 /*-----------------------------------------------------------*/\r
 669 \r
 670 void MPU_vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const xRegions )\r
 671 {\r
 672 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 673 \r
 674         vTaskAllocateMPURegions( xTask, xRegions );\r
 675         portRESET_PRIVILEGE( xRunningPrivileged );\r
 676 }\r
 677 /*-----------------------------------------------------------*/\r
 678 \r
 679 #if ( INCLUDE_vTaskDelete == 1 )\r
 680         void MPU_vTaskDelete( xTaskHandle pxTaskToDelete )\r
 681         {\r
 682     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 683 \r
 684                 vTaskDelete( pxTaskToDelete );\r
 685         portRESET_PRIVILEGE( xRunningPrivileged );\r
 686         }\r
 687 #endif\r
 688 /*-----------------------------------------------------------*/\r
 689 \r
 690 #if ( INCLUDE_vTaskDelayUntil == 1 )\r
 691         void MPU_vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement )\r
 692         {\r
 693     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 694 \r
 695                 vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );\r
 696         portRESET_PRIVILEGE( xRunningPrivileged );\r
 697         }\r
 698 #endif\r
 699 /*-----------------------------------------------------------*/\r
 700 \r
 701 #if ( INCLUDE_vTaskDelay == 1 )\r
 702         void MPU_vTaskDelay( portTickType xTicksToDelay )\r
 703         {\r
 704     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 705 \r
 706                 vTaskDelay( xTicksToDelay );\r
 707         portRESET_PRIVILEGE( xRunningPrivileged );\r
 708         }\r
 709 #endif\r
 710 /*-----------------------------------------------------------*/\r
 711 \r
 712 #if ( INCLUDE_uxTaskPriorityGet == 1 )\r
 713         unsigned portBASE_TYPE MPU_uxTaskPriorityGet( xTaskHandle pxTask )\r
 714         {\r
 715         unsigned portBASE_TYPE uxReturn;\r
 716     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 717 \r
 718                 uxReturn = uxTaskPriorityGet( pxTask );\r
 719         portRESET_PRIVILEGE( xRunningPrivileged );\r
 720                 return uxReturn;\r
 721         }\r
 722 #endif\r
 723 /*-----------------------------------------------------------*/\r
 724 \r
 725 #if ( INCLUDE_vTaskPrioritySet == 1 )\r
 726         void MPU_vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority )\r
 727         {\r
 728     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 729 \r
 730                 vTaskPrioritySet( pxTask, uxNewPriority );\r
 731         portRESET_PRIVILEGE( xRunningPrivileged );\r
 732         }\r
 733 #endif\r
 734 /*-----------------------------------------------------------*/\r
 735 \r
 736 #if ( INCLUDE_vTaskSuspend == 1 )\r
 737         void MPU_vTaskSuspend( xTaskHandle pxTaskToSuspend )\r
 738         {\r
 739     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 740 \r
 741                 vTaskSuspend( pxTaskToSuspend );\r
 742         portRESET_PRIVILEGE( xRunningPrivileged );\r
 743         }\r
 744 #endif\r
 745 /*-----------------------------------------------------------*/\r
 746 \r
 747 #if ( INCLUDE_vTaskSuspend == 1 )\r
 748         signed portBASE_TYPE MPU_xTaskIsTaskSuspended( xTaskHandle xTask )\r
 749         {\r
 750         signed portBASE_TYPE xReturn;\r
 751     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 752 \r
 753                 xReturn = xTaskIsTaskSuspended( xTask );\r
 754         portRESET_PRIVILEGE( xRunningPrivileged );\r
 755                 return xReturn;\r
 756         }\r
 757 #endif\r
 758 /*-----------------------------------------------------------*/\r
 759 \r
 760 #if ( INCLUDE_vTaskSuspend == 1 )\r
 761         void MPU_vTaskResume( xTaskHandle pxTaskToResume )\r
 762         {\r
 763     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 764 \r
 765                 vTaskResume( pxTaskToResume );\r
 766         portRESET_PRIVILEGE( xRunningPrivileged );\r
 767         }\r
 768 #endif\r
 769 /*-----------------------------------------------------------*/\r
 770 \r
 771 void MPU_vTaskSuspendAll( void )\r
 772 {\r
 773 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 774 \r
 775         vTaskSuspendAll();\r
 776     portRESET_PRIVILEGE( xRunningPrivileged );\r
 777 }\r
 778 /*-----------------------------------------------------------*/\r
 779 \r
 780 signed portBASE_TYPE MPU_xTaskResumeAll( void )\r
 781 {\r
 782 signed portBASE_TYPE xReturn;\r
 783 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 784 \r
 785         xReturn = xTaskResumeAll();\r
 786     portRESET_PRIVILEGE( xRunningPrivileged );\r
 787     return xReturn;\r
 788 }\r
 789 /*-----------------------------------------------------------*/\r
 790 \r
 791 portTickType MPU_xTaskGetTickCount( void )\r
 792 {\r
 793 portTickType xReturn;\r
 794 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 795 \r
 796         xReturn = xTaskGetTickCount();\r
 797     portRESET_PRIVILEGE( xRunningPrivileged );\r
 798         return xReturn;\r
 799 }\r
 800 /*-----------------------------------------------------------*/\r
 801 \r
 802 unsigned portBASE_TYPE MPU_uxTaskGetNumberOfTasks( void )\r
 803 {\r
 804 unsigned portBASE_TYPE uxReturn;\r
 805 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 806 \r
 807         uxReturn = uxTaskGetNumberOfTasks();\r
 808     portRESET_PRIVILEGE( xRunningPrivileged );\r
 809         return uxReturn;\r
 810 }\r
 811 /*-----------------------------------------------------------*/\r
 812 \r
 813 #if ( configUSE_TRACE_FACILITY == 1 )\r
 814         void MPU_vTaskList( signed char *pcWriteBuffer )\r
 815         {\r
 816         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 817 \r
 818                 vTaskList( pcWriteBuffer );\r
 819                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 820         }\r
 821 #endif\r
 822 /*-----------------------------------------------------------*/\r
 823 \r
 824 #if ( configGENERATE_RUN_TIME_STATS == 1 )\r
 825         void MPU_vTaskGetRunTimeStats( signed char *pcWriteBuffer )\r
 826         {\r
 827     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 828 \r
 829                 vTaskGetRunTimeStats( pcWriteBuffer );\r
 830         portRESET_PRIVILEGE( xRunningPrivileged );\r
 831         }\r
 832 #endif\r
 833 /*-----------------------------------------------------------*/\r
 834 \r
 835 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 836         void MPU_vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxTagValue )\r
 837         {\r
 838     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 839 \r
 840                 vTaskSetApplicationTaskTag( xTask, pxTagValue );\r
 841         portRESET_PRIVILEGE( xRunningPrivileged );\r
 842         }\r
 843 #endif\r
 844 /*-----------------------------------------------------------*/\r
 845 \r
 846 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 847         pdTASK_HOOK_CODE MPU_xTaskGetApplicationTaskTag( xTaskHandle xTask )\r
 848         {\r
 849         pdTASK_HOOK_CODE xReturn;\r
 850     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 851 \r
 852                 xReturn = xTaskGetApplicationTaskTag( xTask );\r
 853         portRESET_PRIVILEGE( xRunningPrivileged );\r
 854                 return xReturn;\r
 855         }\r
 856 #endif\r
 857 /*-----------------------------------------------------------*/\r
 858 \r
 859 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 860         portBASE_TYPE MPU_xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter )\r
 861         {\r
 862         portBASE_TYPE xReturn;\r
 863     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 864 \r
 865                 xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );\r
 866         portRESET_PRIVILEGE( xRunningPrivileged );\r
 867                 return xReturn;\r
 868         }\r
 869 #endif\r
 870 /*-----------------------------------------------------------*/\r
 871 \r
 872 #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )\r
 873         unsigned portBASE_TYPE MPU_uxTaskGetStackHighWaterMark( xTaskHandle xTask )\r
 874         {\r
 875         unsigned portBASE_TYPE uxReturn;\r
 876     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 877 \r
 878                 uxReturn = uxTaskGetStackHighWaterMark( xTask );\r
 879         portRESET_PRIVILEGE( xRunningPrivileged );\r
 880                 return uxReturn;\r
 881         }\r
 882 #endif\r
 883 /*-----------------------------------------------------------*/\r
 884 \r
 885 #if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 )\r
 886         xTaskHandle MPU_xTaskGetCurrentTaskHandle( void )\r
 887         {\r
 888         xTaskHandle xReturn;\r
 889     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 890 \r
 891                 xReturn = xTaskGetCurrentTaskHandle();\r
 892         portRESET_PRIVILEGE( xRunningPrivileged );\r
 893                 return xReturn;\r
 894         }\r
 895 #endif\r
 896 /*-----------------------------------------------------------*/\r
 897 \r
 898 #if ( INCLUDE_xTaskGetSchedulerState == 1 )\r
 899         portBASE_TYPE MPU_xTaskGetSchedulerState( void )\r
 900         {\r
 901         portBASE_TYPE xReturn;\r
 902     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 903 \r
 904                 xReturn = xTaskGetSchedulerState();\r
 905         portRESET_PRIVILEGE( xRunningPrivileged );\r
 906                 return xReturn;\r
 907         }\r
 908 #endif\r
 909 /*-----------------------------------------------------------*/\r
 910 \r
 911 xQueueHandle MPU_xQueueGenericCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize, unsigned char ucQueueType )\r
 912 {\r
 913 xQueueHandle xReturn;\r
 914 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 915 \r
 916         xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );\r
 917         portRESET_PRIVILEGE( xRunningPrivileged );\r
 918         return xReturn;\r
 919 }\r
 920 /*-----------------------------------------------------------*/\r
 921 \r
 922 signed portBASE_TYPE MPU_xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition )\r
 923 {\r
 924 signed portBASE_TYPE xReturn;\r
 925 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 926 \r
 927         xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );\r
 928         portRESET_PRIVILEGE( xRunningPrivileged );\r
 929         return xReturn;\r
 930 }\r
 931 /*-----------------------------------------------------------*/\r
 932 \r
 933 unsigned portBASE_TYPE MPU_uxQueueMessagesWaiting( const xQueueHandle pxQueue )\r
 934 {\r
 935 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 936 unsigned portBASE_TYPE uxReturn;\r
 937 \r
 938         uxReturn = uxQueueMessagesWaiting( pxQueue );\r
 939         portRESET_PRIVILEGE( xRunningPrivileged );\r
 940         return uxReturn;\r
 941 }\r
 942 /*-----------------------------------------------------------*/\r
 943 \r
 944 signed portBASE_TYPE MPU_xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking )\r
 945 {\r
 946 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 947 signed portBASE_TYPE xReturn;\r
 948 \r
 949         xReturn = xQueueGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking );\r
 950         portRESET_PRIVILEGE( xRunningPrivileged );\r
 951         return xReturn;\r
 952 }\r
 953 /*-----------------------------------------------------------*/\r
 954 \r
 955 #if ( configUSE_MUTEXES == 1 )\r
 956         xQueueHandle MPU_xQueueCreateMutex( void )\r
 957         {\r
 958     xQueueHandle xReturn;\r
 959         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 960 \r
 961                 xReturn = xQueueCreateMutex( queueQUEUE_TYPE_MUTEX );\r
 962                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 963                 return xReturn;\r
 964         }\r
 965 #endif\r
 966 /*-----------------------------------------------------------*/\r
 967 \r
 968 #if configUSE_COUNTING_SEMAPHORES == 1\r
 969         xQueueHandle MPU_xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount )\r
 970         {\r
 971     xQueueHandle xReturn;\r
 972         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 973 \r
 974                 xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );\r
 975                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 976                 return xReturn;\r
 977         }\r
 978 #endif\r
 979 /*-----------------------------------------------------------*/\r
 980 \r
 981 #if ( configUSE_MUTEXES == 1 )\r
 982         portBASE_TYPE MPU_xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime )\r
 983         {\r
 984         portBASE_TYPE xReturn;\r
 985         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 986 \r
 987                 xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );\r
 988                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 989                 return xReturn;\r
 990         }\r
 991 #endif\r
 992 /*-----------------------------------------------------------*/\r
 993 \r
 994 #if ( configUSE_MUTEXES == 1 )\r
 995         portBASE_TYPE MPU_xQueueGiveMutexRecursive( xQueueHandle xMutex )\r
 996         {\r
 997         portBASE_TYPE xReturn;\r
 998         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 999 \r
1000                 xReturn = xQueueGiveMutexRecursive( xMutex );\r
1001                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1002                 return xReturn;\r
1003         }\r
1004 #endif\r
1005 /*-----------------------------------------------------------*/\r
1006 \r
1007 #if configUSE_ALTERNATIVE_API == 1\r
1008         signed portBASE_TYPE MPU_xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition )\r
1009         {\r
1010         signed portBASE_TYPE xReturn;\r
1011         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1012 \r
1013                 xReturn =       signed portBASE_TYPE xQueueAltGenericSend( pxQueue, pvItemToQueue, xTicksToWait, xCopyPosition );\r
1014                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1015                 return xReturn;\r
1016         }\r
1017 #endif\r
1018 /*-----------------------------------------------------------*/\r
1019 \r
1020 #if configUSE_ALTERNATIVE_API == 1\r
1021         signed portBASE_TYPE MPU_xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking )\r
1022         {\r
1023     signed portBASE_TYPE xReturn;\r
1024         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1025 \r
1026                 xReturn = xQueueAltGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking );\r
1027                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1028                 return xReturn;\r
1029         }\r
1030 #endif\r
1031 /*-----------------------------------------------------------*/\r
1032 \r
1033 #if configQUEUE_REGISTRY_SIZE > 0\r
1034         void MPU_vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcName )\r
1035         {\r
1036         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1037 \r
1038                 vQueueAddToRegistry( xQueue, pcName );\r
1039 \r
1040                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1041         }\r
1042 #endif\r
1043 /*-----------------------------------------------------------*/\r
1044 \r
1045 void MPU_vQueueDelete( xQueueHandle xQueue )\r
1046 {\r
1047 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1048 \r
1049         vQueueDelete( xQueue );\r
1050 \r
1051         portRESET_PRIVILEGE( xRunningPrivileged );\r
1052 }\r
1053 /*-----------------------------------------------------------*/\r
1054 \r
1055 void *MPU_pvPortMalloc( size_t xSize )\r
1056 {\r
1057 void *pvReturn;\r
1058 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1059 \r
1060         pvReturn = pvPortMalloc( xSize );\r
1061 \r
1062         portRESET_PRIVILEGE( xRunningPrivileged );\r
1063 \r
1064         return pvReturn;\r
1065 }\r
1066 /*-----------------------------------------------------------*/\r
1067 \r
1068 void MPU_vPortFree( void *pv )\r
1069 {\r
1070 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1071 \r
1072         vPortFree( pv );\r
1073 \r
1074         portRESET_PRIVILEGE( xRunningPrivileged );\r
1075 }\r
1076 /*-----------------------------------------------------------*/\r
1077 \r
1078 void MPU_vPortInitialiseBlocks( void )\r
1079 {\r
1080 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1081 \r
1082         vPortInitialiseBlocks();\r
1083 \r
1084         portRESET_PRIVILEGE( xRunningPrivileged );\r
1085 }\r
1086 /*-----------------------------------------------------------*/\r
1087 \r
1088 size_t MPU_xPortGetFreeHeapSize( void )\r
1089 {\r
1090 size_t xReturn;\r
1091 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1092 \r
1093         xReturn = xPortGetFreeHeapSize();\r
1094 \r
1095         portRESET_PRIVILEGE( xRunningPrivileged );\r
1096 \r
1097         return xReturn;\r
1098 }\r
1099 \r