2 FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 /*-----------------------------------------------------------
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71 * Implementation of functions defined in portable.h for the ARM CM3 port.
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72 *----------------------------------------------------------*/
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74 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
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75 all the API functions to use the MPU wrappers. That should only be done when
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76 task.h is included from an application file. */
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77 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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79 /* Scheduler includes. */
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80 #include "FreeRTOS.h"
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84 #include "event_groups.h"
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85 #include "mpu_prototypes.h"
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87 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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89 /* Constants required to access and manipulate the NVIC. */
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90 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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91 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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92 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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93 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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94 #define portNVIC_SYSPRI1_REG ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
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95 #define portNVIC_SYS_CTRL_STATE_REG ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
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96 #define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
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98 /* Constants required to access and manipulate the MPU. */
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99 #define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
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100 #define portMPU_REGION_BASE_ADDRESS_REG ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
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101 #define portMPU_REGION_ATTRIBUTE_REG ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
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102 #define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
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103 #define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
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104 #define portMPU_ENABLE ( 0x01UL )
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105 #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
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106 #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
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107 #define portMPU_REGION_VALID ( 0x10UL )
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108 #define portMPU_REGION_ENABLE ( 0x01UL )
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109 #define portPERIPHERALS_START_ADDRESS 0x40000000UL
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110 #define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
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112 /* Constants required to access and manipulate the SysTick. */
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113 #define portNVIC_SYSTICK_CLK ( 0x00000004UL )
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114 #define portNVIC_SYSTICK_INT ( 0x00000002UL )
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115 #define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
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116 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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117 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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118 #define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
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120 /* Constants required to set up the initial stack. */
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121 #define portINITIAL_XPSR ( 0x01000000 )
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122 #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
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123 #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
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125 /* Constants required to check the validity of an interrupt priority. */
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126 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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127 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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128 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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129 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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130 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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131 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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132 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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133 #define portPRIGROUP_SHIFT ( 8UL )
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135 /* Offsets in the stack to the parameters when inside the SVC handler. */
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136 #define portOFFSET_TO_PC ( 6 )
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138 /* For strict compliance with the Cortex-M spec the task start address should
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139 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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140 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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142 /* Each task maintains its own interrupt status in the critical nesting
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143 variable. Note this is not saved as part of the task context as context
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144 switches can only occur when uxCriticalNesting is zero. */
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145 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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148 * Setup the timer to generate the tick interrupts.
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150 static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
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153 * Configure a number of standard MPU regions that are used by all tasks.
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155 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
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158 * Return the smallest MPU region size that a given number of bytes will fit
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159 * into. The region size is returned as the value that should be programmed
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160 * into the region attribute register for that region.
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162 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
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165 * Checks to see if being called from the context of an unprivileged task, and
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166 * if so raises the privilege level and returns false - otherwise does nothing
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167 * other than return true.
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169 BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));
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172 * Standard FreeRTOS exception handlers.
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174 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
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175 void xPortSysTickHandler( void ) __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;
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176 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
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179 * Starts the scheduler by restoring the context of the first task to run.
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181 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
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184 * C portion of the SVC handler. The SVC handler is split between an asm entry
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185 * and a C wrapper for simplicity of coding and maintenance.
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187 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;
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190 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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191 * FreeRTOS API functions are not called from interrupts that have been assigned
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192 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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194 #if ( configASSERT_DEFINED == 1 )
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195 static uint8_t ucMaxSysCallPriority = 0;
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196 static uint32_t ulMaxPRIGROUPValue = 0;
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197 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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198 #endif /* configASSERT_DEFINED */
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200 /*-----------------------------------------------------------*/
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203 * See header file for description.
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205 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
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207 /* Simulate the stack frame as it would be created by a context switch
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209 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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210 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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212 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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214 *pxTopOfStack = 0; /* LR */
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215 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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216 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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217 pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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219 if( xRunPrivileged == pdTRUE )
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221 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
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225 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
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228 return pxTopOfStack;
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230 /*-----------------------------------------------------------*/
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232 void vPortSVCHandler( void )
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234 /* Assumes psp was in use. */
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237 #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
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240 " mrseq r0, msp \n"
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241 " mrsne r0, psp \n"
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246 ::"i"(prvSVCHandler):"r0"
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249 /*-----------------------------------------------------------*/
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251 static void prvSVCHandler( uint32_t *pulParam )
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253 uint8_t ucSVCNumber;
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255 /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
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256 xPSR. The first argument (r0) is pulParam[ 0 ]. */
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257 ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
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258 switch( ucSVCNumber )
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260 case portSVC_START_SCHEDULER : portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
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261 prvRestoreContextOfFirstTask();
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264 case portSVC_YIELD : portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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265 /* Barriers are normally not required
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266 but do ensure the code is completely
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267 within the specified behaviour for the
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269 __asm volatile( "dsb" );
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270 __asm volatile( "isb" );
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274 case portSVC_RAISE_PRIVILEGE : __asm volatile
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276 " mrs r1, control \n" /* Obtain current control value. */
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277 " bic r1, #1 \n" /* Set privilege bit. */
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278 " msr control, r1 \n" /* Write back new control value. */
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283 default : /* Unknown SVC call. */
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287 /*-----------------------------------------------------------*/
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289 static void prvRestoreContextOfFirstTask( void )
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293 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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296 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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297 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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299 " ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */
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300 " add r1, r1, #4 \n" /* Move onto the second item in the TCB... */
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301 " ldr r2, =0xe000ed9c \n" /* Region Base Address register. */
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302 " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */
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303 " stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */
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304 " ldmia r0!, {r3, r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry. */
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305 " msr control, r3 \n"
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306 " msr psp, r0 \n" /* Restore the task stack pointer. */
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308 " msr basepri, r0 \n"
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309 " ldr r14, =0xfffffffd \n" /* Load exec return code. */
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313 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
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316 /*-----------------------------------------------------------*/
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319 * See header file for description.
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321 BaseType_t xPortStartScheduler( void )
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323 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
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324 http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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325 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
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327 #if( configASSERT_DEFINED == 1 )
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329 volatile uint32_t ulOriginalPriority;
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330 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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331 volatile uint8_t ucMaxPriorityValue;
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333 /* Determine the maximum priority from which ISR safe FreeRTOS API
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334 functions can be called. ISR safe functions are those that end in
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335 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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336 ensure interrupt entry is as fast and simple as possible.
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338 Save the interrupt priority value that is about to be clobbered. */
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339 ulOriginalPriority = *pucFirstUserPriorityRegister;
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341 /* Determine the number of priority bits available. First write to all
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343 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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345 /* Read the value back to see how many bits stuck. */
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346 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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348 /* Use the same mask on the maximum system call priority. */
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349 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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351 /* Calculate the maximum acceptable priority group value for the number
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352 of bits read back. */
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353 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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354 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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356 ulMaxPRIGROUPValue--;
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357 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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360 /* Shift the priority group value back to its position within the AIRCR
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362 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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363 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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365 /* Restore the clobbered interrupt priority register to its original
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367 *pucFirstUserPriorityRegister = ulOriginalPriority;
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369 #endif /* conifgASSERT_DEFINED */
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371 /* Make PendSV and SysTick the same priority as the kernel, and the SVC
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372 handler higher priority so it can be used to exit a critical section (where
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373 lower priorities are masked). */
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374 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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375 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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377 /* Configure the regions in the MPU that are common to all tasks. */
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380 /* Start the timer that generates the tick ISR. Interrupts are disabled
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382 prvSetupTimerInterrupt();
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384 /* Initialise the critical nesting count ready for the first task. */
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385 uxCriticalNesting = 0;
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387 /* Start the first task. */
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389 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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392 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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393 " cpsie i \n" /* Globally enable interrupts. */
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397 " svc %0 \n" /* System call to start first task. */
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399 :: "i" (portSVC_START_SCHEDULER) );
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401 /* Should not get here! */
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404 /*-----------------------------------------------------------*/
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406 void vPortEndScheduler( void )
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408 /* Not implemented in ports where there is nothing to return to.
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409 Artificially force an assert. */
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410 configASSERT( uxCriticalNesting == 1000UL );
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412 /*-----------------------------------------------------------*/
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414 void vPortEnterCritical( void )
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416 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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418 portDISABLE_INTERRUPTS();
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419 uxCriticalNesting++;
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421 vPortResetPrivilege( xRunningPrivileged );
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423 /*-----------------------------------------------------------*/
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425 void vPortExitCritical( void )
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427 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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429 configASSERT( uxCriticalNesting );
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430 uxCriticalNesting--;
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431 if( uxCriticalNesting == 0 )
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433 portENABLE_INTERRUPTS();
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435 vPortResetPrivilege( xRunningPrivileged );
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437 /*-----------------------------------------------------------*/
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439 void xPortPendSVHandler( void )
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441 /* This is a naked function. */
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447 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
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450 " mrs r1, control \n"
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451 " stmdb r0!, {r1, r4-r11} \n" /* Save the remaining registers. */
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452 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
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454 " stmdb sp!, {r3, r14} \n"
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456 " msr basepri, r0 \n"
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457 " bl vTaskSwitchContext \n"
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459 " msr basepri, r0 \n"
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460 " ldmia sp!, {r3, r14} \n"
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461 " \n" /* Restore the context. */
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463 " ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */
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464 " add r1, r1, #4 \n" /* Move onto the second item in the TCB... */
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465 " ldr r2, =0xe000ed9c \n" /* Region Base Address register. */
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466 " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */
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467 " stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */
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468 " ldmia r0!, {r3, r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry. */
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469 " msr control, r3 \n"
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475 "pxCurrentTCBConst: .word pxCurrentTCB \n"
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476 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
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479 /*-----------------------------------------------------------*/
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481 void xPortSysTickHandler( void )
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485 ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
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487 /* Increment the RTOS tick. */
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488 if( xTaskIncrementTick() != pdFALSE )
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490 /* Pend a context switch. */
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491 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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494 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
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496 /*-----------------------------------------------------------*/
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499 * Setup the systick timer to generate the tick interrupts at the required
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502 static void prvSetupTimerInterrupt( void )
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504 /* Reset the SysTick timer. */
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505 portNVIC_SYSTICK_CTRL_REG = 0UL;
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506 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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508 /* Configure SysTick to interrupt at the requested rate. */
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509 portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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510 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
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512 /*-----------------------------------------------------------*/
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514 static void prvSetupMPU( void )
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516 extern uint32_t __privileged_functions_end__[];
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517 extern uint32_t __FLASH_segment_start__[];
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518 extern uint32_t __FLASH_segment_end__[];
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519 extern uint32_t __privileged_data_start__[];
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520 extern uint32_t __privileged_data_end__[];
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522 /* Check the expected MPU is present. */
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523 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
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525 /* First setup the entire flash for unprivileged read only access. */
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526 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
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527 ( portMPU_REGION_VALID ) |
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528 ( portUNPRIVILEGED_FLASH_REGION );
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530 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
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531 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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532 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
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533 ( portMPU_REGION_ENABLE );
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535 /* Setup the first 16K for privileged only access (even though less
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536 than 10K is actually being used). This is where the kernel code is
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538 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
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539 ( portMPU_REGION_VALID ) |
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540 ( portPRIVILEGED_FLASH_REGION );
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542 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
\r
543 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
544 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
\r
545 ( portMPU_REGION_ENABLE );
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547 /* Setup the privileged data RAM region. This is where the kernel data
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549 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
550 ( portMPU_REGION_VALID ) |
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551 ( portPRIVILEGED_RAM_REGION );
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553 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
554 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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555 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
556 ( portMPU_REGION_ENABLE );
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558 /* By default allow everything to access the general peripherals. The
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559 system peripherals and registers are protected. */
\r
560 portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
\r
561 ( portMPU_REGION_VALID ) |
\r
562 ( portGENERAL_PERIPHERALS_REGION );
\r
564 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
\r
565 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
\r
566 ( portMPU_REGION_ENABLE );
\r
568 /* Enable the memory fault exception. */
\r
569 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
\r
571 /* Enable the MPU with the background region configured. */
\r
572 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
\r
575 /*-----------------------------------------------------------*/
\r
577 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
\r
579 uint32_t ulRegionSize, ulReturnValue = 4;
\r
581 /* 32 is the smallest region size, 31 is the largest valid value for
\r
583 for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
\r
585 if( ulActualSizeInBytes <= ulRegionSize )
\r
595 /* Shift the code by one before returning so it can be written directly
\r
596 into the the correct bit position of the attribute register. */
\r
597 return ( ulReturnValue << 1UL );
\r
599 /*-----------------------------------------------------------*/
\r
601 BaseType_t xPortRaisePrivilege( void )
\r
605 " mrs r0, control \n"
\r
606 " tst r0, #1 \n" /* Is the task running privileged? */
\r
608 " movne r0, #0 \n" /* CONTROL[0]!=0, return false. */
\r
609 " svcne %0 \n" /* Switch to privileged. */
\r
610 " moveq r0, #1 \n" /* CONTROL[0]==0, return true. */
\r
612 :: "i" (portSVC_RAISE_PRIVILEGE) : "r0"
\r
617 /*-----------------------------------------------------------*/
\r
619 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
\r
621 extern uint32_t __SRAM_segment_start__[];
\r
622 extern uint32_t __SRAM_segment_end__[];
\r
623 extern uint32_t __privileged_data_start__[];
\r
624 extern uint32_t __privileged_data_end__[];
\r
628 if( xRegions == NULL )
\r
630 /* No MPU regions are specified so allow access to all RAM. */
\r
631 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
632 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
\r
633 ( portMPU_REGION_VALID ) |
\r
634 ( portSTACK_REGION );
\r
636 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
637 ( portMPU_REGION_READ_WRITE ) |
\r
638 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
639 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
\r
640 ( portMPU_REGION_ENABLE );
\r
642 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
\r
643 just removed the privileged only parameters. */
\r
644 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
\r
645 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
646 ( portMPU_REGION_VALID ) |
\r
647 ( portSTACK_REGION + 1 );
\r
649 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
\r
650 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
651 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
652 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
653 ( portMPU_REGION_ENABLE );
\r
655 /* Invalidate all other regions. */
\r
656 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
658 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
659 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
664 /* This function is called automatically when the task is created - in
\r
665 which case the stack region parameters will be valid. At all other
\r
666 times the stack parameters will not be valid and it is assumed that the
\r
667 stack region has already been configured. */
\r
668 if( ulStackDepth > 0 )
\r
670 /* Define the region that allows access to the stack. */
\r
671 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
672 ( ( uint32_t ) pxBottomOfStack ) |
\r
673 ( portMPU_REGION_VALID ) |
\r
674 ( portSTACK_REGION ); /* Region number. */
\r
676 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
677 ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
\r
678 ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
\r
679 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
680 ( portMPU_REGION_ENABLE );
\r
685 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
687 if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
\r
689 /* Translate the generic region definition contained in
\r
690 xRegions into the CM3 specific MPU settings that are then
\r
691 stored in xMPUSettings. */
\r
692 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
\r
693 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
\r
694 ( portMPU_REGION_VALID ) |
\r
695 ( portSTACK_REGION + ul ); /* Region number. */
\r
697 xMPUSettings->xRegion[ ul ].ulRegionAttribute =
\r
698 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
\r
699 ( xRegions[ lIndex ].ulParameters ) |
\r
700 ( portMPU_REGION_ENABLE );
\r
704 /* Invalidate the region. */
\r
705 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
706 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
713 /*-----------------------------------------------------------*/
\r
715 #if( configASSERT_DEFINED == 1 )
\r
717 void vPortValidateInterruptPriority( void )
\r
719 uint32_t ulCurrentInterrupt;
\r
720 uint8_t ucCurrentPriority;
\r
722 /* Obtain the number of the currently executing interrupt. */
\r
723 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
\r
725 /* Is the interrupt number a user defined interrupt? */
\r
726 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
728 /* Look up the interrupt's priority. */
\r
729 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
731 /* The following assertion will fail if a service routine (ISR) for
\r
732 an interrupt that has been assigned a priority above
\r
733 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
734 function. ISR safe FreeRTOS API functions must *only* be called
\r
735 from interrupts that have been assigned a priority at or below
\r
736 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
738 Numerically low interrupt priority numbers represent logically high
\r
739 interrupt priorities, therefore the priority of the interrupt must
\r
740 be set to a value equal to or numerically *higher* than
\r
741 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
743 Interrupts that use the FreeRTOS API must not be left at their
\r
744 default priority of zero as that is the highest possible priority,
\r
745 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
746 and therefore also guaranteed to be invalid.
\r
748 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
749 interrupt entry is as fast and simple as possible.
\r
751 The following links provide detailed information:
\r
752 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
753 http://www.freertos.org/FAQHelp.html */
\r
754 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
757 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
758 that define each interrupt's priority to be split between bits that
\r
759 define the interrupt's pre-emption priority bits and bits that define
\r
760 the interrupt's sub-priority. For simplicity all bits must be defined
\r
761 to be pre-emption priority bits. The following assertion will fail if
\r
762 this is not the case (if some bits represent a sub-priority).
\r
764 If the application only uses CMSIS libraries for interrupt
\r
765 configuration then the correct setting can be achieved on all Cortex-M
\r
766 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
767 scheduler. Note however that some vendor specific peripheral libraries
\r
768 assume a non-zero priority group setting, in which cases using a value
\r
769 of zero will result in unpredicable behaviour. */
\r
770 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
773 #endif /* configASSERT_DEFINED */
\r
774 /*-----------------------------------------------------------*/
\r