git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c

   1 /*\r
   2     FreeRTOS V8.0.0:rc1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     ***************************************************************************\r
   8      *                                                                       *\r
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  10      *    robust, strictly quality controlled, supported, and cross          *\r
  11      *    platform software that has become a de facto standard.             *\r
  12      *                                                                       *\r
  13      *    Help yourself get started quickly and support the FreeRTOS         *\r
  14      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  15      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  16      *                                                                       *\r
  17      *    Thank you!                                                         *\r
  18      *                                                                       *\r
  19     ***************************************************************************\r
  20 \r
  21     This file is part of the FreeRTOS distribution.\r
  22 \r
  23     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  24     the terms of the GNU General Public License (version 2) as published by the\r
  25     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  26 \r
  27     >>! NOTE: The modification to the GPL is included to allow you to distribute\r
  28     >>! a combined work that includes FreeRTOS without being obliged to provide\r
  29     >>! the source code for proprietary components outside of the FreeRTOS\r
  30     >>! kernel.\r
  31 \r
  32     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  33     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  34     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  35     link: http://www.freertos.org/a00114.html\r
  36 \r
  37     1 tab == 4 spaces!\r
  38 \r
  39     ***************************************************************************\r
  40      *                                                                       *\r
  41      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  42      *    not run, what could be wrong?"                                     *\r
  43      *                                                                       *\r
  44      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  45      *                                                                       *\r
  46     ***************************************************************************\r
  47 \r
  48     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  49     license and Real Time Engineers Ltd. contact details.\r
  50 \r
  51     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  52     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  53     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  54 \r
  55     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  56     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  57     licenses offer ticketed support, indemnification and middleware.\r
  58 \r
  59     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  60     engineered and independently SIL3 certified version for use in safety and\r
  61     mission critical applications that require provable dependability.\r
  62 \r
  63     1 tab == 4 spaces!\r
  64 */\r
  65 \r
  66 /*-----------------------------------------------------------\r
  67  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  68  *----------------------------------------------------------*/\r
  69 \r
  70 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
  71 all the API functions to use the MPU wrappers.  That should only be done when\r
  72 task.h is included from an application file. */\r
  73 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  74 \r
  75 /* Scheduler includes. */\r
  76 #include "FreeRTOS.h"\r
  77 #include "task.h"\r
  78 #include "queue.h"\r
  79 \r
  80 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  81 \r
  82 /* Constants required to access and manipulate the NVIC. */\r
  83 #define portNVIC_SYSTICK_CTRL                                   ( ( volatile uint32_t * ) 0xe000e010 )\r
  84 #define portNVIC_SYSTICK_LOAD                                   ( ( volatile uint32_t * ) 0xe000e014 )\r
  85 #define portNVIC_SYSPRI2                                                ( ( volatile uint32_t * ) 0xe000ed20 )\r
  86 #define portNVIC_SYSPRI1                                                ( ( volatile uint32_t * ) 0xe000ed1c )\r
  87 #define portNVIC_SYS_CTRL_STATE                                 ( ( volatile uint32_t * ) 0xe000ed24 )\r
  88 #define portNVIC_MEM_FAULT_ENABLE                               ( 1UL << 16UL )\r
  89 \r
  90 /* Constants required to access and manipulate the MPU. */\r
  91 #define portMPU_TYPE                                                    ( ( volatile uint32_t * ) 0xe000ed90 )\r
  92 #define portMPU_REGION_BASE_ADDRESS                             ( ( volatile uint32_t * ) 0xe000ed9C )\r
  93 #define portMPU_REGION_ATTRIBUTE                                ( ( volatile uint32_t * ) 0xe000edA0 )\r
  94 #define portMPU_CTRL                                                    ( ( volatile uint32_t * ) 0xe000ed94 )\r
  95 #define portEXPECTED_MPU_TYPE_VALUE                             ( 8UL << 8UL ) /* 8 regions, unified. */\r
  96 #define portMPU_ENABLE                                                  ( 0x01UL )\r
  97 #define portMPU_BACKGROUND_ENABLE                               ( 1UL << 2UL )\r
  98 #define portPRIVILEGED_EXECUTION_START_ADDRESS  ( 0UL )\r
  99 #define portMPU_REGION_VALID                                    ( 0x10UL )\r
 100 #define portMPU_REGION_ENABLE                                   ( 0x01UL )\r
 101 #define portPERIPHERALS_START_ADDRESS                   0x40000000UL\r
 102 #define portPERIPHERALS_END_ADDRESS                             0x5FFFFFFFUL\r
 103 \r
 104 /* Constants required to access and manipulate the SysTick. */\r
 105 #define portNVIC_SYSTICK_CLK                                    ( 0x00000004UL )\r
 106 #define portNVIC_SYSTICK_INT                                    ( 0x00000002UL )\r
 107 #define portNVIC_SYSTICK_ENABLE                                 ( 0x00000001UL )\r
 108 #define portNVIC_PENDSV_PRI                                             ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 109 #define portNVIC_SYSTICK_PRI                                    ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 110 #define portNVIC_SVC_PRI                                                ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 111 \r
 112 /* Constants required to set up the initial stack. */\r
 113 #define portINITIAL_XPSR                                                ( 0x01000000 )\r
 114 #define portINITIAL_CONTROL_IF_UNPRIVILEGED             ( 0x03 )\r
 115 #define portINITIAL_CONTROL_IF_PRIVILEGED               ( 0x02 )\r
 116 \r
 117 /* Offsets in the stack to the parameters when inside the SVC handler. */\r
 118 #define portOFFSET_TO_PC                                                ( 6 )\r
 119 \r
 120 /* Set the privilege level to user mode if xRunningPrivileged is false. */\r
 121 #define portRESET_PRIVILEGE( xRunningPrivileged ) if( xRunningPrivileged != pdTRUE ) __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0" :::"r0" )\r
 122 \r
 123 /* Each task maintains its own interrupt status in the critical nesting\r
 124 variable.  Note this is not saved as part of the task context as context\r
 125 switches can only occur when uxCriticalNesting is zero. */\r
 126 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
 127 \r
 128 /*\r
 129  * Setup the timer to generate the tick interrupts.\r
 130  */\r
 131 static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
 132 \r
 133 /*\r
 134  * Configure a number of standard MPU regions that are used by all tasks.\r
 135  */\r
 136 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
 137 \r
 138 /*\r
 139  * Return the smallest MPU region size that a given number of bytes will fit\r
 140  * into.  The region size is returned as the value that should be programmed\r
 141  * into the region attribute register for that region.\r
 142  */\r
 143 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
 144 \r
 145 /*\r
 146  * Checks to see if being called from the context of an unprivileged task, and\r
 147  * if so raises the privilege level and returns false - otherwise does nothing\r
 148  * other than return true.\r
 149  */\r
 150 static BaseType_t prvRaisePrivilege( void ) __attribute__(( naked ));\r
 151 \r
 152 /*\r
 153  * Standard FreeRTOS exception handlers.\r
 154  */\r
 155 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 156 void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;\r
 157 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 158 \r
 159 /*\r
 160  * Starts the scheduler by restoring the context of the first task to run.\r
 161  */\r
 162 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
 163 \r
 164 /*\r
 165  * C portion of the SVC handler.  The SVC handler is split between an asm entry\r
 166  * and a C wrapper for simplicity of coding and maintenance.\r
 167  */\r
 168 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
 169 \r
 170 /*\r
 171  * Prototypes for all the MPU wrappers.\r
 172  */\r
 173 BaseType_t MPU_xTaskGenericCreate( TaskFunction_t pvTaskCode, const char * const pcName, uint16_t usStackDepth, void *pvParameters, UBaseType_t uxPriority, TaskHandle_t *pxCreatedTask, StackType_t *puxStackBuffer, const MemoryRegion_t * const xRegions );\r
 174 void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const xRegions );\r
 175 void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete );\r
 176 void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, TickType_t xTimeIncrement );\r
 177 void MPU_vTaskDelay( TickType_t xTicksToDelay );\r
 178 UBaseType_t MPU_uxTaskPriorityGet( TaskHandle_t pxTask );\r
 179 void MPU_vTaskPrioritySet( TaskHandle_t pxTask, UBaseType_t uxNewPriority );\r
 180 eTaskState MPU_eTaskGetState( TaskHandle_t pxTask );\r
 181 void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend );\r
 182 void MPU_vTaskResume( TaskHandle_t pxTaskToResume );\r
 183 void MPU_vTaskSuspendAll( void );\r
 184 BaseType_t MPU_xTaskResumeAll( void );\r
 185 TickType_t MPU_xTaskGetTickCount( void );\r
 186 UBaseType_t MPU_uxTaskGetNumberOfTasks( void );\r
 187 void MPU_vTaskList( char *pcWriteBuffer );\r
 188 void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer );\r
 189 void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxTagValue );\r
 190 TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask );\r
 191 BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );\r
 192 UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask );\r
 193 TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void );\r
 194 BaseType_t MPU_xTaskGetSchedulerState( void );\r
 195 TaskHandle_t MPU_xTaskGetIdleTaskHandle( void );\r
 196 UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t *pxTaskStatusArray, UBaseType_t uxArraySize, uint32_t *pulTotalRunTime );\r
 197 QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, UBaseType_t uxItemSize, uint8_t ucQueueType );\r
 198 BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition );\r
 199 BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, BaseType_t xNewQueue );\r
 200 UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue );\r
 201 BaseType_t MPU_xQueueGenericReceive( QueueHandle_t pxQueue, void * const pvBuffer, TickType_t xTicksToWait, BaseType_t xJustPeeking );\r
 202 QueueHandle_t MPU_xQueueCreateMutex( void );\r
 203 QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, UBaseType_t uxInitialCount );\r
 204 BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xBlockTime );\r
 205 BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex );\r
 206 BaseType_t MPU_xQueueAltGenericSend( QueueHandle_t pxQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition );\r
 207 BaseType_t MPU_xQueueAltGenericReceive( QueueHandle_t pxQueue, void * const pvBuffer, TickType_t xTicksToWait, BaseType_t xJustPeeking );\r
 208 void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, char *pcName );\r
 209 void MPU_vQueueDelete( QueueHandle_t xQueue );\r
 210 void *MPU_pvPortMalloc( size_t xSize );\r
 211 void MPU_vPortFree( void *pv );\r
 212 void MPU_vPortInitialiseBlocks( void );\r
 213 size_t MPU_xPortGetFreeHeapSize( void );\r
 214 QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength );\r
 215 QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t xBlockTimeTicks );\r
 216 BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );\r
 217 BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );\r
 218 BaseType_t MPU_xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer );\r
 219 \r
 220 /*-----------------------------------------------------------*/\r
 221 \r
 222 /*\r
 223  * See header file for description.\r
 224  */\r
 225 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )\r
 226 {\r
 227         /* Simulate the stack frame as it would be created by a context switch\r
 228         interrupt. */\r
 229         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 230         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 231         pxTopOfStack--;\r
 232         *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
 233         pxTopOfStack--;\r
 234         *pxTopOfStack = 0;      /* LR */\r
 235         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 236         *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
 237         pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 238 \r
 239         if( xRunPrivileged == pdTRUE )\r
 240         {\r
 241                 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\r
 242         }\r
 243         else\r
 244         {\r
 245                 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\r
 246         }\r
 247 \r
 248         return pxTopOfStack;\r
 249 }\r
 250 /*-----------------------------------------------------------*/\r
 251 \r
 252 void vPortSVCHandler( void )\r
 253 {\r
 254         /* Assumes psp was in use. */\r
 255         __asm volatile\r
 256         (\r
 257                 #ifndef USE_PROCESS_STACK       /* Code should not be required if a main() is using the process stack. */\r
 258                         "       tst lr, #4                                              \n"\r
 259                         "       ite eq                                                  \n"\r
 260                         "       mrseq r0, msp                                   \n"\r
 261                         "       mrsne r0, psp                                   \n"\r
 262                 #else\r
 263                         "       mrs r0, psp                                             \n"\r
 264                 #endif\r
 265                         "       b %0                                                    \n"\r
 266                         ::"i"(prvSVCHandler):"r0"\r
 267         );\r
 268 }\r
 269 /*-----------------------------------------------------------*/\r
 270 \r
 271 static void prvSVCHandler(      uint32_t *pulParam )\r
 272 {\r
 273 uint8_t ucSVCNumber;\r
 274 \r
 275         /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and\r
 276         xPSR.  The first argument (r0) is pulParam[ 0 ]. */\r
 277         ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];\r
 278         switch( ucSVCNumber )\r
 279         {\r
 280                 case portSVC_START_SCHEDULER    :       *(portNVIC_SYSPRI1) |= portNVIC_SVC_PRI;\r
 281                                                                                         prvRestoreContextOfFirstTask();\r
 282                                                                                         break;\r
 283 \r
 284                 case portSVC_YIELD                              :       *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 285                                                                                         /* Barriers are normally not required\r
 286                                                                                         but do ensure the code is completely\r
 287                                                                                         within the specified behaviour for the\r
 288                                                                                         architecture. */\r
 289                                                                                         __asm volatile( "dsb" );\r
 290                                                                                         __asm volatile( "isb" );\r
 291 \r
 292                                                                                         break;\r
 293 \r
 294                 case portSVC_RAISE_PRIVILEGE    :       __asm volatile\r
 295                                                                                         (\r
 296                                                                                                 "       mrs r1, control         \n" /* Obtain current control value. */\r
 297                                                                                                 "       bic r1, #1                      \n" /* Set privilege bit. */\r
 298                                                                                                 "       msr control, r1         \n" /* Write back new control value. */\r
 299                                                                                                 :::"r1"\r
 300                                                                                         );\r
 301                                                                                         break;\r
 302 \r
 303                 default                                                 :       /* Unknown SVC call. */\r
 304                                                                                         break;\r
 305         }\r
 306 }\r
 307 /*-----------------------------------------------------------*/\r
 308 \r
 309 static void prvRestoreContextOfFirstTask( void )\r
 310 {\r
 311         __asm volatile\r
 312         (\r
 313                 "       ldr r0, =0xE000ED08                             \n" /* Use the NVIC offset register to locate the stack. */\r
 314                 "       ldr r0, [r0]                                    \n"\r
 315                 "       ldr r0, [r0]                                    \n"\r
 316                 "       msr msp, r0                                             \n" /* Set the msp back to the start of the stack. */\r
 317                 "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 318                 "       ldr r1, [r3]                                    \n"\r
 319                 "       ldr r0, [r1]                                    \n" /* The first item in the TCB is the task top of stack. */\r
 320                 "       add r1, r1, #4                                  \n" /* Move onto the second item in the TCB... */\r
 321                 "       ldr r2, =0xe000ed9c                             \n" /* Region Base Address register. */\r
 322                 "       ldmia r1!, {r4-r11}                             \n" /* Read 4 sets of MPU registers. */\r
 323                 "       stmia r2!, {r4-r11}                             \n" /* Write 4 sets of MPU registers. */\r
 324                 "       ldmia r0!, {r3, r4-r11}                 \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 325                 "       msr control, r3                                 \n"\r
 326                 "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 327                 "       mov r0, #0                                              \n"\r
 328                 "       msr     basepri, r0                                     \n"\r
 329                 "       ldr r14, =0xfffffffd                    \n" /* Load exec return code. */\r
 330                 "       bx r14                                                  \n"\r
 331                 "                                                                       \n"\r
 332                 "       .align 2                                                \n"\r
 333                 "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
 334         );\r
 335 }\r
 336 /*-----------------------------------------------------------*/\r
 337 \r
 338 /*\r
 339  * See header file for description.\r
 340  */\r
 341 BaseType_t xPortStartScheduler( void )\r
 342 {\r
 343         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See\r
 344         http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 345         configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\r
 346 \r
 347         /* Make PendSV and SysTick the same priority as the kernel. */\r
 348         *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
 349         *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
 350 \r
 351         /* Configure the regions in the MPU that are common to all tasks. */\r
 352         prvSetupMPU();\r
 353 \r
 354         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 355         here already. */\r
 356         prvSetupTimerInterrupt();\r
 357 \r
 358         /* Initialise the critical nesting count ready for the first task. */\r
 359         uxCriticalNesting = 0;\r
 360 \r
 361         /* Start the first task. */\r
 362         __asm volatile( "       svc %0                  \n"\r
 363                                         :: "i" (portSVC_START_SCHEDULER) );\r
 364 \r
 365         /* Should not get here! */\r
 366         return 0;\r
 367 }\r
 368 /*-----------------------------------------------------------*/\r
 369 \r
 370 void vPortEndScheduler( void )\r
 371 {\r
 372         /* Not implemented in ports where there is nothing to return to.\r
 373         Artificially force an assert. */\r
 374         configASSERT( uxCriticalNesting == 1000UL );\r
 375 }\r
 376 /*-----------------------------------------------------------*/\r
 377 \r
 378 void vPortEnterCritical( void )\r
 379 {\r
 380 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 381 \r
 382         portDISABLE_INTERRUPTS();\r
 383         uxCriticalNesting++;\r
 384 \r
 385         portRESET_PRIVILEGE( xRunningPrivileged );\r
 386 }\r
 387 /*-----------------------------------------------------------*/\r
 388 \r
 389 void vPortExitCritical( void )\r
 390 {\r
 391 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 392 \r
 393         configASSERT( uxCriticalNesting );\r
 394         uxCriticalNesting--;\r
 395         if( uxCriticalNesting == 0 )\r
 396         {\r
 397                 portENABLE_INTERRUPTS();\r
 398         }\r
 399         portRESET_PRIVILEGE( xRunningPrivileged );\r
 400 }\r
 401 /*-----------------------------------------------------------*/\r
 402 \r
 403 void xPortPendSVHandler( void )\r
 404 {\r
 405         /* This is a naked function. */\r
 406 \r
 407         __asm volatile\r
 408         (\r
 409                 "       mrs r0, psp                                                     \n"\r
 410                 "                                                                               \n"\r
 411                 "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 412                 "       ldr     r2, [r3]                                                \n"\r
 413                 "                                                                               \n"\r
 414                 "       mrs r1, control                                         \n"\r
 415                 "       stmdb r0!, {r1, r4-r11}                         \n" /* Save the remaining registers. */\r
 416                 "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 417                 "                                                                               \n"\r
 418                 "       stmdb sp!, {r3, r14}                            \n"\r
 419                 "       mov r0, %0                                                      \n"\r
 420                 "       msr basepri, r0                                         \n"\r
 421                 "       bl vTaskSwitchContext                           \n"\r
 422                 "       mov r0, #0                                                      \n"\r
 423                 "       msr basepri, r0                                         \n"\r
 424                 "       ldmia sp!, {r3, r14}                            \n"\r
 425                 "                                                                               \n"     /* Restore the context. */\r
 426                 "       ldr r1, [r3]                                            \n"\r
 427                 "       ldr r0, [r1]                                            \n" /* The first item in the TCB is the task top of stack. */\r
 428                 "       add r1, r1, #4                                          \n" /* Move onto the second item in the TCB... */\r
 429                 "       ldr r2, =0xe000ed9c                                     \n" /* Region Base Address register. */\r
 430                 "       ldmia r1!, {r4-r11}                                     \n" /* Read 4 sets of MPU registers. */\r
 431                 "       stmia r2!, {r4-r11}                                     \n" /* Write 4 sets of MPU registers. */\r
 432                 "       ldmia r0!, {r3, r4-r11}                         \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 433                 "       msr control, r3                                         \n"\r
 434                 "                                                                               \n"\r
 435                 "       msr psp, r0                                                     \n"\r
 436                 "       bx r14                                                          \n"\r
 437                 "                                                                               \n"\r
 438                 "       .align 2                                                        \n"\r
 439                 "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 440                 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 441         );\r
 442 }\r
 443 /*-----------------------------------------------------------*/\r
 444 \r
 445 void xPortSysTickHandler( void )\r
 446 {\r
 447 uint32_t ulDummy;\r
 448 \r
 449         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
 450         {\r
 451                 /* Increment the RTOS tick. */\r
 452                 if( xTaskIncrementTick() != pdFALSE )\r
 453                 {\r
 454                         /* Pend a context switch. */\r
 455                         *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 456                 }\r
 457         }\r
 458         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
 459 }\r
 460 /*-----------------------------------------------------------*/\r
 461 \r
 462 /*\r
 463  * Setup the systick timer to generate the tick interrupts at the required\r
 464  * frequency.\r
 465  */\r
 466 static void prvSetupTimerInterrupt( void )\r
 467 {\r
 468         /* Configure SysTick to interrupt at the requested rate. */\r
 469         *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 470         *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
 471 }\r
 472 /*-----------------------------------------------------------*/\r
 473 \r
 474 static void prvSetupMPU( void )\r
 475 {\r
 476 extern uint32_t __privileged_functions_end__[];\r
 477 extern uint32_t __FLASH_segment_start__[];\r
 478 extern uint32_t __FLASH_segment_end__[];\r
 479 extern uint32_t __privileged_data_start__[];\r
 480 extern uint32_t __privileged_data_end__[];\r
 481 \r
 482         /* Check the expected MPU is present. */\r
 483         if( *portMPU_TYPE == portEXPECTED_MPU_TYPE_VALUE )\r
 484         {\r
 485                 /* First setup the entire flash for unprivileged read only access. */\r
 486         *portMPU_REGION_BASE_ADDRESS =  ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 487                                                                                 ( portMPU_REGION_VALID ) |\r
 488                                                                                 ( portUNPRIVILEGED_FLASH_REGION );\r
 489 \r
 490                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_READ_ONLY ) |\r
 491                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 492                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 493                                                                                 ( portMPU_REGION_ENABLE );\r
 494 \r
 495                 /* Setup the first 16K for privileged only access (even though less\r
 496                 than 10K is actually being used).  This is where the kernel code is\r
 497                 placed. */\r
 498         *portMPU_REGION_BASE_ADDRESS =  ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 499                                                                                 ( portMPU_REGION_VALID ) |\r
 500                                                                                 ( portPRIVILEGED_FLASH_REGION );\r
 501 \r
 502                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
 503                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 504                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 505                                                                                 ( portMPU_REGION_ENABLE );\r
 506 \r
 507                 /* Setup the privileged data RAM region.  This is where the kernel data\r
 508                 is placed. */\r
 509                 *portMPU_REGION_BASE_ADDRESS =  ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 510                                                                                 ( portMPU_REGION_VALID ) |\r
 511                                                                                 ( portPRIVILEGED_RAM_REGION );\r
 512 \r
 513                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 514                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 515                                                                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 516                                                                                 ( portMPU_REGION_ENABLE );\r
 517 \r
 518                 /* By default allow everything to access the general peripherals.  The\r
 519                 system peripherals and registers are protected. */\r
 520                 *portMPU_REGION_BASE_ADDRESS =  ( portPERIPHERALS_START_ADDRESS ) |\r
 521                                                                                 ( portMPU_REGION_VALID ) |\r
 522                                                                                 ( portGENERAL_PERIPHERALS_REGION );\r
 523 \r
 524                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
 525                                                                                 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\r
 526                                                                                 ( portMPU_REGION_ENABLE );\r
 527 \r
 528                 /* Enable the memory fault exception. */\r
 529                 *portNVIC_SYS_CTRL_STATE |= portNVIC_MEM_FAULT_ENABLE;\r
 530 \r
 531                 /* Enable the MPU with the background region configured. */\r
 532                 *portMPU_CTRL |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
 533         }\r
 534 }\r
 535 /*-----------------------------------------------------------*/\r
 536 \r
 537 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )\r
 538 {\r
 539 uint32_t ulRegionSize, ulReturnValue = 4;\r
 540 \r
 541         /* 32 is the smallest region size, 31 is the largest valid value for\r
 542         ulReturnValue. */\r
 543         for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\r
 544         {\r
 545                 if( ulActualSizeInBytes <= ulRegionSize )\r
 546                 {\r
 547                         break;\r
 548                 }\r
 549                 else\r
 550                 {\r
 551                         ulReturnValue++;\r
 552                 }\r
 553         }\r
 554 \r
 555         /* Shift the code by one before returning so it can be written directly\r
 556         into the the correct bit position of the attribute register. */\r
 557         return ( ulReturnValue << 1UL );\r
 558 }\r
 559 /*-----------------------------------------------------------*/\r
 560 \r
 561 static BaseType_t prvRaisePrivilege( void )\r
 562 {\r
 563         __asm volatile\r
 564         (\r
 565                 "       mrs r0, control                                         \n"\r
 566                 "       tst r0, #1                                                      \n" /* Is the task running privileged? */\r
 567                 "       itte ne                                                         \n"\r
 568                 "       movne r0, #0                                            \n" /* CONTROL[0]!=0, return false. */\r
 569                 "       svcne %0                                                        \n" /* Switch to privileged. */\r
 570                 "       moveq r0, #1                                            \n" /* CONTROL[0]==0, return true. */\r
 571                 "       bx lr                                                           \n"\r
 572                 :: "i" (portSVC_RAISE_PRIVILEGE) : "r0"\r
 573         );\r
 574 \r
 575         return 0;\r
 576 }\r
 577 /*-----------------------------------------------------------*/\r
 578 \r
 579 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint16_t usStackDepth )\r
 580 {\r
 581 extern uint32_t __SRAM_segment_start__[];\r
 582 extern uint32_t __SRAM_segment_end__[];\r
 583 extern uint32_t __privileged_data_start__[];\r
 584 extern uint32_t __privileged_data_end__[];\r
 585 int32_t lIndex;\r
 586 uint32_t ul;\r
 587 \r
 588         if( xRegions == NULL )\r
 589         {\r
 590                 /* No MPU regions are specified so allow access to all RAM. */\r
 591         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 592                                 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */\r
 593                                 ( portMPU_REGION_VALID ) |\r
 594                                 ( portSTACK_REGION );\r
 595 \r
 596                 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 597                                 ( portMPU_REGION_READ_WRITE ) |\r
 598                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 599                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |\r
 600                                 ( portMPU_REGION_ENABLE );\r
 601 \r
 602                 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
 603                 just removed the privileged only parameters. */\r
 604                 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =\r
 605                                 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 606                                 ( portMPU_REGION_VALID ) |\r
 607                                 ( portSTACK_REGION + 1 );\r
 608 \r
 609                 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =\r
 610                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 611                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 612                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 613                                 ( portMPU_REGION_ENABLE );\r
 614 \r
 615                 /* Invalidate all other regions. */\r
 616                 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 617                 {\r
 618                         xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 619                         xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 620                 }\r
 621         }\r
 622         else\r
 623         {\r
 624                 /* This function is called automatically when the task is created - in\r
 625                 which case the stack region parameters will be valid.  At all other\r
 626                 times the stack parameters will not be valid and it is assumed that the\r
 627                 stack region has already been configured. */\r
 628                 if( usStackDepth > 0 )\r
 629                 {\r
 630                         /* Define the region that allows access to the stack. */\r
 631                         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 632                                         ( ( uint32_t ) pxBottomOfStack ) |\r
 633                                         ( portMPU_REGION_VALID ) |\r
 634                                         ( portSTACK_REGION ); /* Region number. */\r
 635 \r
 636                         xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 637                                         ( portMPU_REGION_READ_WRITE ) | /* Read and write. */\r
 638                                         ( prvGetMPURegionSizeSetting( ( uint32_t ) usStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |\r
 639                                         ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 640                                         ( portMPU_REGION_ENABLE );\r
 641                 }\r
 642 \r
 643                 lIndex = 0;\r
 644 \r
 645                 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 646                 {\r
 647                         if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\r
 648                         {\r
 649                                 /* Translate the generic region definition contained in\r
 650                                 xRegions into the CM3 specific MPU settings that are then\r
 651                                 stored in xMPUSettings. */\r
 652                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\r
 653                                                 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |\r
 654                                                 ( portMPU_REGION_VALID ) |\r
 655                                                 ( portSTACK_REGION + ul ); /* Region number. */\r
 656 \r
 657                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute =\r
 658                                                 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\r
 659                                                 ( xRegions[ lIndex ].ulParameters ) |\r
 660                                                 ( portMPU_REGION_ENABLE );\r
 661                         }\r
 662                         else\r
 663                         {\r
 664                                 /* Invalidate the region. */\r
 665                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 666                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 667                         }\r
 668 \r
 669                         lIndex++;\r
 670                 }\r
 671         }\r
 672 }\r
 673 /*-----------------------------------------------------------*/\r
 674 \r
 675 BaseType_t MPU_xTaskGenericCreate( TaskFunction_t pvTaskCode, const char * const pcName, uint16_t usStackDepth, void *pvParameters, UBaseType_t uxPriority, TaskHandle_t *pxCreatedTask, StackType_t *puxStackBuffer, const MemoryRegion_t * const xRegions )\r
 676 {\r
 677 BaseType_t xReturn;\r
 678 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 679 \r
 680         xReturn = xTaskGenericCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask, puxStackBuffer, xRegions );\r
 681         portRESET_PRIVILEGE( xRunningPrivileged );\r
 682         return xReturn;\r
 683 }\r
 684 /*-----------------------------------------------------------*/\r
 685 \r
 686 void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const xRegions )\r
 687 {\r
 688 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 689 \r
 690         vTaskAllocateMPURegions( xTask, xRegions );\r
 691         portRESET_PRIVILEGE( xRunningPrivileged );\r
 692 }\r
 693 /*-----------------------------------------------------------*/\r
 694 \r
 695 #if ( INCLUDE_vTaskDelete == 1 )\r
 696         void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete )\r
 697         {\r
 698     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 699 \r
 700                 vTaskDelete( pxTaskToDelete );\r
 701         portRESET_PRIVILEGE( xRunningPrivileged );\r
 702         }\r
 703 #endif\r
 704 /*-----------------------------------------------------------*/\r
 705 \r
 706 #if ( INCLUDE_vTaskDelayUntil == 1 )\r
 707         void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, TickType_t xTimeIncrement )\r
 708         {\r
 709     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 710 \r
 711                 vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );\r
 712         portRESET_PRIVILEGE( xRunningPrivileged );\r
 713         }\r
 714 #endif\r
 715 /*-----------------------------------------------------------*/\r
 716 \r
 717 #if ( INCLUDE_vTaskDelay == 1 )\r
 718         void MPU_vTaskDelay( TickType_t xTicksToDelay )\r
 719         {\r
 720     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 721 \r
 722                 vTaskDelay( xTicksToDelay );\r
 723         portRESET_PRIVILEGE( xRunningPrivileged );\r
 724         }\r
 725 #endif\r
 726 /*-----------------------------------------------------------*/\r
 727 \r
 728 #if ( INCLUDE_uxTaskPriorityGet == 1 )\r
 729         UBaseType_t MPU_uxTaskPriorityGet( TaskHandle_t pxTask )\r
 730         {\r
 731         UBaseType_t uxReturn;\r
 732     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 733 \r
 734                 uxReturn = uxTaskPriorityGet( pxTask );\r
 735         portRESET_PRIVILEGE( xRunningPrivileged );\r
 736                 return uxReturn;\r
 737         }\r
 738 #endif\r
 739 /*-----------------------------------------------------------*/\r
 740 \r
 741 #if ( INCLUDE_vTaskPrioritySet == 1 )\r
 742         void MPU_vTaskPrioritySet( TaskHandle_t pxTask, UBaseType_t uxNewPriority )\r
 743         {\r
 744     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 745 \r
 746                 vTaskPrioritySet( pxTask, uxNewPriority );\r
 747         portRESET_PRIVILEGE( xRunningPrivileged );\r
 748         }\r
 749 #endif\r
 750 /*-----------------------------------------------------------*/\r
 751 \r
 752 #if ( INCLUDE_eTaskGetState == 1 )\r
 753         eTaskState MPU_eTaskGetState( TaskHandle_t pxTask )\r
 754         {\r
 755     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 756         eTaskState eReturn;\r
 757 \r
 758                 eReturn = eTaskGetState( pxTask );\r
 759         portRESET_PRIVILEGE( xRunningPrivileged );\r
 760                 return eReturn;\r
 761         }\r
 762 #endif\r
 763 /*-----------------------------------------------------------*/\r
 764 \r
 765 #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\r
 766         TaskHandle_t MPU_xTaskGetIdleTaskHandle( void )\r
 767         {\r
 768         TaskHandle_t xReturn;\r
 769     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 770 \r
 771                 xReturn = xTaskGetIdleTaskHandle();\r
 772         portRESET_PRIVILEGE( xRunningPrivileged );\r
 773                 return eReturn;\r
 774         }\r
 775 #endif\r
 776 /*-----------------------------------------------------------*/\r
 777 \r
 778 #if ( INCLUDE_vTaskSuspend == 1 )\r
 779         void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend )\r
 780         {\r
 781     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 782 \r
 783                 vTaskSuspend( pxTaskToSuspend );\r
 784         portRESET_PRIVILEGE( xRunningPrivileged );\r
 785         }\r
 786 #endif\r
 787 /*-----------------------------------------------------------*/\r
 788 \r
 789 #if ( INCLUDE_vTaskSuspend == 1 )\r
 790         void MPU_vTaskResume( TaskHandle_t pxTaskToResume )\r
 791         {\r
 792     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 793 \r
 794                 vTaskResume( pxTaskToResume );\r
 795         portRESET_PRIVILEGE( xRunningPrivileged );\r
 796         }\r
 797 #endif\r
 798 /*-----------------------------------------------------------*/\r
 799 \r
 800 void MPU_vTaskSuspendAll( void )\r
 801 {\r
 802 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 803 \r
 804         vTaskSuspendAll();\r
 805     portRESET_PRIVILEGE( xRunningPrivileged );\r
 806 }\r
 807 /*-----------------------------------------------------------*/\r
 808 \r
 809 BaseType_t MPU_xTaskResumeAll( void )\r
 810 {\r
 811 BaseType_t xReturn;\r
 812 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 813 \r
 814         xReturn = xTaskResumeAll();\r
 815     portRESET_PRIVILEGE( xRunningPrivileged );\r
 816     return xReturn;\r
 817 }\r
 818 /*-----------------------------------------------------------*/\r
 819 \r
 820 TickType_t MPU_xTaskGetTickCount( void )\r
 821 {\r
 822 TickType_t xReturn;\r
 823 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 824 \r
 825         xReturn = xTaskGetTickCount();\r
 826     portRESET_PRIVILEGE( xRunningPrivileged );\r
 827         return xReturn;\r
 828 }\r
 829 /*-----------------------------------------------------------*/\r
 830 \r
 831 UBaseType_t MPU_uxTaskGetNumberOfTasks( void )\r
 832 {\r
 833 UBaseType_t uxReturn;\r
 834 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 835 \r
 836         uxReturn = uxTaskGetNumberOfTasks();\r
 837     portRESET_PRIVILEGE( xRunningPrivileged );\r
 838         return uxReturn;\r
 839 }\r
 840 /*-----------------------------------------------------------*/\r
 841 \r
 842 #if ( configUSE_TRACE_FACILITY == 1 )\r
 843         void MPU_vTaskList( char *pcWriteBuffer )\r
 844         {\r
 845         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 846 \r
 847                 vTaskList( pcWriteBuffer );\r
 848                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 849         }\r
 850 #endif\r
 851 /*-----------------------------------------------------------*/\r
 852 \r
 853 #if ( configGENERATE_RUN_TIME_STATS == 1 )\r
 854         void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer )\r
 855         {\r
 856     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 857 \r
 858                 vTaskGetRunTimeStats( pcWriteBuffer );\r
 859         portRESET_PRIVILEGE( xRunningPrivileged );\r
 860         }\r
 861 #endif\r
 862 /*-----------------------------------------------------------*/\r
 863 \r
 864 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 865         void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxTagValue )\r
 866         {\r
 867     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 868 \r
 869                 vTaskSetApplicationTaskTag( xTask, pxTagValue );\r
 870         portRESET_PRIVILEGE( xRunningPrivileged );\r
 871         }\r
 872 #endif\r
 873 /*-----------------------------------------------------------*/\r
 874 \r
 875 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 876         TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask )\r
 877         {\r
 878         TaskHookFunction_t xReturn;\r
 879     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 880 \r
 881                 xReturn = xTaskGetApplicationTaskTag( xTask );\r
 882         portRESET_PRIVILEGE( xRunningPrivileged );\r
 883                 return xReturn;\r
 884         }\r
 885 #endif\r
 886 /*-----------------------------------------------------------*/\r
 887 \r
 888 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 889         BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )\r
 890         {\r
 891         BaseType_t xReturn;\r
 892     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 893 \r
 894                 xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );\r
 895         portRESET_PRIVILEGE( xRunningPrivileged );\r
 896                 return xReturn;\r
 897         }\r
 898 #endif\r
 899 /*-----------------------------------------------------------*/\r
 900 \r
 901 #if ( configUSE_TRACE_FACILITY == 1 )\r
 902         UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t *pxTaskStatusArray, UBaseType_t uxArraySize, uint32_t *pulTotalRunTime )\r
 903         {\r
 904         UBaseType_t uxReturn;\r
 905         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 906 \r
 907                 uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );\r
 908                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 909                 return xReturn;\r
 910         }\r
 911 #endif\r
 912 /*-----------------------------------------------------------*/\r
 913 \r
 914 #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )\r
 915         UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask )\r
 916         {\r
 917         UBaseType_t uxReturn;\r
 918     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 919 \r
 920                 uxReturn = uxTaskGetStackHighWaterMark( xTask );\r
 921         portRESET_PRIVILEGE( xRunningPrivileged );\r
 922                 return uxReturn;\r
 923         }\r
 924 #endif\r
 925 /*-----------------------------------------------------------*/\r
 926 \r
 927 #if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 )\r
 928         TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void )\r
 929         {\r
 930         TaskHandle_t xReturn;\r
 931     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 932 \r
 933                 xReturn = xTaskGetCurrentTaskHandle();\r
 934         portRESET_PRIVILEGE( xRunningPrivileged );\r
 935                 return xReturn;\r
 936         }\r
 937 #endif\r
 938 /*-----------------------------------------------------------*/\r
 939 \r
 940 #if ( INCLUDE_xTaskGetSchedulerState == 1 )\r
 941         BaseType_t MPU_xTaskGetSchedulerState( void )\r
 942         {\r
 943         BaseType_t xReturn;\r
 944     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 945 \r
 946                 xReturn = xTaskGetSchedulerState();\r
 947         portRESET_PRIVILEGE( xRunningPrivileged );\r
 948                 return xReturn;\r
 949         }\r
 950 #endif\r
 951 /*-----------------------------------------------------------*/\r
 952 \r
 953 QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, UBaseType_t uxItemSize, uint8_t ucQueueType )\r
 954 {\r
 955 QueueHandle_t xReturn;\r
 956 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 957 \r
 958         xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );\r
 959         portRESET_PRIVILEGE( xRunningPrivileged );\r
 960         return xReturn;\r
 961 }\r
 962 /*-----------------------------------------------------------*/\r
 963 \r
 964 BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, BaseType_t xNewQueue )\r
 965 {\r
 966 BaseType_t xReturn;\r
 967 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 968 \r
 969         xReturn = xQueueGenericReset( pxQueue, xNewQueue );\r
 970         portRESET_PRIVILEGE( xRunningPrivileged );\r
 971         return xReturn;\r
 972 }\r
 973 /*-----------------------------------------------------------*/\r
 974 \r
 975 BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition )\r
 976 {\r
 977 BaseType_t xReturn;\r
 978 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 979 \r
 980         xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );\r
 981         portRESET_PRIVILEGE( xRunningPrivileged );\r
 982         return xReturn;\r
 983 }\r
 984 /*-----------------------------------------------------------*/\r
 985 \r
 986 UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue )\r
 987 {\r
 988 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 989 UBaseType_t uxReturn;\r
 990 \r
 991         uxReturn = uxQueueMessagesWaiting( pxQueue );\r
 992         portRESET_PRIVILEGE( xRunningPrivileged );\r
 993         return uxReturn;\r
 994 }\r
 995 /*-----------------------------------------------------------*/\r
 996 \r
 997 BaseType_t MPU_xQueueGenericReceive( QueueHandle_t pxQueue, void * const pvBuffer, TickType_t xTicksToWait, BaseType_t xJustPeeking )\r
 998 {\r
 999 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1000 BaseType_t xReturn;\r
1001 \r
1002         xReturn = xQueueGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking );\r
1003         portRESET_PRIVILEGE( xRunningPrivileged );\r
1004         return xReturn;\r
1005 }\r
1006 /*-----------------------------------------------------------*/\r
1007 \r
1008 BaseType_t MPU_xQueuePeekFromISR( QueueHandle_t pxQueue, void * const pvBuffer )\r
1009 {\r
1010 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1011 BaseType_t xReturn;\r
1012 \r
1013         xReturn = xQueuePeekFromISR( pxQueue, pvBuffer );\r
1014         portRESET_PRIVILEGE( xRunningPrivileged );\r
1015         return xReturn;\r
1016 }\r
1017 /*-----------------------------------------------------------*/\r
1018 \r
1019 #if ( configUSE_MUTEXES == 1 )\r
1020         QueueHandle_t MPU_xQueueCreateMutex( void )\r
1021         {\r
1022     QueueHandle_t xReturn;\r
1023         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1024 \r
1025                 xReturn = xQueueCreateMutex( queueQUEUE_TYPE_MUTEX );\r
1026                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1027                 return xReturn;\r
1028         }\r
1029 #endif\r
1030 /*-----------------------------------------------------------*/\r
1031 \r
1032 #if configUSE_COUNTING_SEMAPHORES == 1\r
1033         QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, UBaseType_t uxInitialCount )\r
1034         {\r
1035     QueueHandle_t xReturn;\r
1036         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1037 \r
1038                 xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );\r
1039                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1040                 return xReturn;\r
1041         }\r
1042 #endif\r
1043 /*-----------------------------------------------------------*/\r
1044 \r
1045 #if ( configUSE_MUTEXES == 1 )\r
1046         BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xBlockTime )\r
1047         {\r
1048         BaseType_t xReturn;\r
1049         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1050 \r
1051                 xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );\r
1052                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1053                 return xReturn;\r
1054         }\r
1055 #endif\r
1056 /*-----------------------------------------------------------*/\r
1057 \r
1058 #if ( configUSE_MUTEXES == 1 )\r
1059         BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex )\r
1060         {\r
1061         BaseType_t xReturn;\r
1062         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1063 \r
1064                 xReturn = xQueueGiveMutexRecursive( xMutex );\r
1065                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1066                 return xReturn;\r
1067         }\r
1068 #endif\r
1069 /*-----------------------------------------------------------*/\r
1070 \r
1071 #if ( configUSE_QUEUE_SETS == 1 )\r
1072         QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength )\r
1073         {\r
1074         QueueSetHandle_t xReturn;\r
1075         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1076 \r
1077                 xReturn = xQueueCreateSet( uxEventQueueLength );\r
1078                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1079                 return xReturn;\r
1080         }\r
1081 #endif\r
1082 /*-----------------------------------------------------------*/\r
1083 \r
1084 #if ( configUSE_QUEUE_SETS == 1 )\r
1085         QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t xBlockTimeTicks )\r
1086         {\r
1087         QueueSetMemberHandle_t xReturn;\r
1088         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1089 \r
1090                 xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks );\r
1091                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1092                 return xReturn;\r
1093         }\r
1094 #endif\r
1095 /*-----------------------------------------------------------*/\r
1096 \r
1097 #if ( configUSE_QUEUE_SETS == 1 )\r
1098         BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )\r
1099         {\r
1100         BaseType_t xReturn;\r
1101         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1102 \r
1103                 xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet );\r
1104                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1105                 return xReturn;\r
1106         }\r
1107 #endif\r
1108 /*-----------------------------------------------------------*/\r
1109 \r
1110 #if ( configUSE_QUEUE_SETS == 1 )\r
1111         BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )\r
1112         {\r
1113         BaseType_t xReturn;\r
1114         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1115 \r
1116                 xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );\r
1117                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1118                 return xReturn;\r
1119         }\r
1120 #endif\r
1121 /*-----------------------------------------------------------*/\r
1122 \r
1123 #if configUSE_ALTERNATIVE_API == 1\r
1124         BaseType_t MPU_xQueueAltGenericSend( QueueHandle_t pxQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition )\r
1125         {\r
1126         BaseType_t xReturn;\r
1127         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1128 \r
1129                 xReturn =       BaseType_t xQueueAltGenericSend( pxQueue, pvItemToQueue, xTicksToWait, xCopyPosition );\r
1130                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1131                 return xReturn;\r
1132         }\r
1133 #endif\r
1134 /*-----------------------------------------------------------*/\r
1135 \r
1136 #if configUSE_ALTERNATIVE_API == 1\r
1137         BaseType_t MPU_xQueueAltGenericReceive( QueueHandle_t pxQueue, void * const pvBuffer, TickType_t xTicksToWait, BaseType_t xJustPeeking )\r
1138         {\r
1139     BaseType_t xReturn;\r
1140         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1141 \r
1142                 xReturn = xQueueAltGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking );\r
1143                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1144                 return xReturn;\r
1145         }\r
1146 #endif\r
1147 /*-----------------------------------------------------------*/\r
1148 \r
1149 #if configQUEUE_REGISTRY_SIZE > 0\r
1150         void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, char *pcName )\r
1151         {\r
1152         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1153 \r
1154                 vQueueAddToRegistry( xQueue, pcName );\r
1155 \r
1156                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1157         }\r
1158 #endif\r
1159 /*-----------------------------------------------------------*/\r
1160 \r
1161 void MPU_vQueueDelete( QueueHandle_t xQueue )\r
1162 {\r
1163 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1164 \r
1165         vQueueDelete( xQueue );\r
1166 \r
1167         portRESET_PRIVILEGE( xRunningPrivileged );\r
1168 }\r
1169 /*-----------------------------------------------------------*/\r
1170 \r
1171 void *MPU_pvPortMalloc( size_t xSize )\r
1172 {\r
1173 void *pvReturn;\r
1174 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1175 \r
1176         pvReturn = pvPortMalloc( xSize );\r
1177 \r
1178         portRESET_PRIVILEGE( xRunningPrivileged );\r
1179 \r
1180         return pvReturn;\r
1181 }\r
1182 /*-----------------------------------------------------------*/\r
1183 \r
1184 void MPU_vPortFree( void *pv )\r
1185 {\r
1186 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1187 \r
1188         vPortFree( pv );\r
1189 \r
1190         portRESET_PRIVILEGE( xRunningPrivileged );\r
1191 }\r
1192 /*-----------------------------------------------------------*/\r
1193 \r
1194 void MPU_vPortInitialiseBlocks( void )\r
1195 {\r
1196 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1197 \r
1198         vPortInitialiseBlocks();\r
1199 \r
1200         portRESET_PRIVILEGE( xRunningPrivileged );\r
1201 }\r
1202 /*-----------------------------------------------------------*/\r
1203 \r
1204 size_t MPU_xPortGetFreeHeapSize( void )\r
1205 {\r
1206 size_t xReturn;\r
1207 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1208 \r
1209         xReturn = xPortGetFreeHeapSize();\r
1210 \r
1211         portRESET_PRIVILEGE( xRunningPrivileged );\r
1212 \r
1213         return xReturn;\r
1214 }\r
1215 \r
1216 /* Functions that the application writer wants to execute in privileged mode\r
1217 can be defined in application_defined_privileged_functions.h.  The functions\r
1218 must take the same format as those above whereby the privilege state on exit\r
1219 equals the privilege state on entry.  For example:\r
1220 \r
1221 void MPU_FunctionName( [parameters ] )\r
1222 {\r
1223 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1224 \r
1225         FunctionName( [parameters ] );\r
1226 \r
1227         portRESET_PRIVILEGE( xRunningPrivileged );\r
1228 }\r
1229 */\r
1230 \r
1231 #if configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS == 1\r
1232         #include "application_defined_privileged_functions.h"\r
1233 #endif\r
1234 \r