git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c

   1 /*\r
   2     FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     ***************************************************************************\r
   8      *                                                                       *\r
   9      *    FreeRTOS provides completely free yet professionally developed,    *\r
  10      *    robust, strictly quality controlled, supported, and cross          *\r
  11      *    platform software that has become a de facto standard.             *\r
  12      *                                                                       *\r
  13      *    Help yourself get started quickly and support the FreeRTOS         *\r
  14      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  15      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  16      *                                                                       *\r
  17      *    Thank you!                                                         *\r
  18      *                                                                       *\r
  19     ***************************************************************************\r
  20 \r
  21     This file is part of the FreeRTOS distribution.\r
  22 \r
  23     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  24     the terms of the GNU General Public License (version 2) as published by the\r
  25     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  26 \r
  27     >>! NOTE: The modification to the GPL is included to allow you to distribute\r
  28     >>! a combined work that includes FreeRTOS without being obliged to provide\r
  29     >>! the source code for proprietary components outside of the FreeRTOS\r
  30     >>! kernel.\r
  31 \r
  32     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  33     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  34     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  35     link: http://www.freertos.org/a00114.html\r
  36 \r
  37     1 tab == 4 spaces!\r
  38 \r
  39     ***************************************************************************\r
  40      *                                                                       *\r
  41      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  42      *    not run, what could be wrong?"                                     *\r
  43      *                                                                       *\r
  44      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  45      *                                                                       *\r
  46     ***************************************************************************\r
  47 \r
  48     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  49     license and Real Time Engineers Ltd. contact details.\r
  50 \r
  51     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  52     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  53     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  54 \r
  55     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  56     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  57     licenses offer ticketed support, indemnification and middleware.\r
  58 \r
  59     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  60     engineered and independently SIL3 certified version for use in safety and\r
  61     mission critical applications that require provable dependability.\r
  62 \r
  63     1 tab == 4 spaces!\r
  64 */\r
  65 \r
  66 /*-----------------------------------------------------------\r
  67  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  68  *----------------------------------------------------------*/\r
  69 \r
  70 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
  71 all the API functions to use the MPU wrappers.  That should only be done when\r
  72 task.h is included from an application file. */\r
  73 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  74 \r
  75 /* Scheduler includes. */\r
  76 #include "FreeRTOS.h"\r
  77 #include "task.h"\r
  78 #include "queue.h"\r
  79 \r
  80 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  81 \r
  82 /* Constants required to access and manipulate the NVIC. */\r
  83 #define portNVIC_SYSTICK_CTRL                                   ( ( volatile unsigned long * ) 0xe000e010 )\r
  84 #define portNVIC_SYSTICK_LOAD                                   ( ( volatile unsigned long * ) 0xe000e014 )\r
  85 #define portNVIC_SYSPRI2                                                ( ( volatile unsigned long * ) 0xe000ed20 )\r
  86 #define portNVIC_SYSPRI1                                                ( ( volatile unsigned long * ) 0xe000ed1c )\r
  87 #define portNVIC_SYS_CTRL_STATE                                 ( ( volatile unsigned long * ) 0xe000ed24 )\r
  88 #define portNVIC_MEM_FAULT_ENABLE                               ( 1UL << 16UL )\r
  89 \r
  90 /* Constants required to access and manipulate the MPU. */\r
  91 #define portMPU_TYPE                                                    ( ( volatile unsigned long * ) 0xe000ed90 )\r
  92 #define portMPU_REGION_BASE_ADDRESS                             ( ( volatile unsigned long * ) 0xe000ed9C )\r
  93 #define portMPU_REGION_ATTRIBUTE                                ( ( volatile unsigned long * ) 0xe000edA0 )\r
  94 #define portMPU_CTRL                                                    ( ( volatile unsigned long * ) 0xe000ed94 )\r
  95 #define portEXPECTED_MPU_TYPE_VALUE                             ( 8UL << 8UL ) /* 8 regions, unified. */\r
  96 #define portMPU_ENABLE                                                  ( 0x01UL )\r
  97 #define portMPU_BACKGROUND_ENABLE                               ( 1UL << 2UL )\r
  98 #define portPRIVILEGED_EXECUTION_START_ADDRESS  ( 0UL )\r
  99 #define portMPU_REGION_VALID                                    ( 0x10UL )\r
 100 #define portMPU_REGION_ENABLE                                   ( 0x01UL )\r
 101 #define portPERIPHERALS_START_ADDRESS                   0x40000000UL\r
 102 #define portPERIPHERALS_END_ADDRESS                             0x5FFFFFFFUL\r
 103 \r
 104 /* Constants required to access and manipulate the SysTick. */\r
 105 #define portNVIC_SYSTICK_CLK                                    ( 0x00000004UL )\r
 106 #define portNVIC_SYSTICK_INT                                    ( 0x00000002UL )\r
 107 #define portNVIC_SYSTICK_ENABLE                                 ( 0x00000001UL )\r
 108 #define portNVIC_PENDSV_PRI                                             ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 109 #define portNVIC_SYSTICK_PRI                                    ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 110 #define portNVIC_SVC_PRI                                                ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 111 \r
 112 /* Constants required to set up the initial stack. */\r
 113 #define portINITIAL_XPSR                                                ( 0x01000000 )\r
 114 #define portINITIAL_CONTROL_IF_UNPRIVILEGED             ( 0x03 )\r
 115 #define portINITIAL_CONTROL_IF_PRIVILEGED               ( 0x02 )\r
 116 \r
 117 /* Offsets in the stack to the parameters when inside the SVC handler. */\r
 118 #define portOFFSET_TO_PC                                                ( 6 )\r
 119 \r
 120 /* Set the privilege level to user mode if xRunningPrivileged is false. */\r
 121 #define portRESET_PRIVILEGE( xRunningPrivileged ) if( xRunningPrivileged != pdTRUE ) __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0" :::"r0" )\r
 122 \r
 123 /* Each task maintains its own interrupt status in the critical nesting\r
 124 variable.  Note this is not saved as part of the task context as context\r
 125 switches can only occur when uxCriticalNesting is zero. */\r
 126 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
 127 \r
 128 /*\r
 129  * Setup the timer to generate the tick interrupts.\r
 130  */\r
 131 static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
 132 \r
 133 /*\r
 134  * Configure a number of standard MPU regions that are used by all tasks.\r
 135  */\r
 136 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
 137 \r
 138 /*\r
 139  * Return the smallest MPU region size that a given number of bytes will fit\r
 140  * into.  The region size is returned as the value that should be programmed\r
 141  * into the region attribute register for that region.\r
 142  */\r
 143 static unsigned long prvGetMPURegionSizeSetting( unsigned long ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
 144 \r
 145 /*\r
 146  * Checks to see if being called from the context of an unprivileged task, and\r
 147  * if so raises the privilege level and returns false - otherwise does nothing\r
 148  * other than return true.\r
 149  */\r
 150 static portBASE_TYPE prvRaisePrivilege( void ) __attribute__(( naked ));\r
 151 \r
 152 /*\r
 153  * Standard FreeRTOS exception handlers.\r
 154  */\r
 155 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 156 void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;\r
 157 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 158 \r
 159 /*\r
 160  * Starts the scheduler by restoring the context of the first task to run.\r
 161  */\r
 162 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
 163 \r
 164 /*\r
 165  * C portion of the SVC handler.  The SVC handler is split between an asm entry\r
 166  * and a C wrapper for simplicity of coding and maintenance.\r
 167  */\r
 168 static void prvSVCHandler( unsigned long *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
 169 \r
 170 /*\r
 171  * Prototypes for all the MPU wrappers.\r
 172  */\r
 173 signed portBASE_TYPE MPU_xTaskGenericCreate( pdTASK_CODE pvTaskCode, const char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions );\r
 174 void MPU_vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const xRegions );\r
 175 void MPU_vTaskDelete( xTaskHandle pxTaskToDelete );\r
 176 void MPU_vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement );\r
 177 void MPU_vTaskDelay( portTickType xTicksToDelay );\r
 178 unsigned portBASE_TYPE MPU_uxTaskPriorityGet( xTaskHandle pxTask );\r
 179 void MPU_vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );\r
 180 eTaskState MPU_eTaskGetState( xTaskHandle pxTask );\r
 181 void MPU_vTaskSuspend( xTaskHandle pxTaskToSuspend );\r
 182 signed portBASE_TYPE MPU_xTaskIsTaskSuspended( xTaskHandle xTask );\r
 183 void MPU_vTaskResume( xTaskHandle pxTaskToResume );\r
 184 void MPU_vTaskSuspendAll( void );\r
 185 signed portBASE_TYPE MPU_xTaskResumeAll( void );\r
 186 portTickType MPU_xTaskGetTickCount( void );\r
 187 unsigned portBASE_TYPE MPU_uxTaskGetNumberOfTasks( void );\r
 188 void MPU_vTaskList( char *pcWriteBuffer );\r
 189 void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer );\r
 190 void MPU_vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxTagValue );\r
 191 pdTASK_HOOK_CODE MPU_xTaskGetApplicationTaskTag( xTaskHandle xTask );\r
 192 portBASE_TYPE MPU_xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter );\r
 193 unsigned portBASE_TYPE MPU_uxTaskGetStackHighWaterMark( xTaskHandle xTask );\r
 194 xTaskHandle MPU_xTaskGetCurrentTaskHandle( void );\r
 195 portBASE_TYPE MPU_xTaskGetSchedulerState( void );\r
 196 xTaskHandle MPU_xTaskGetIdleTaskHandle( void );\r
 197 unsigned portBASE_TYPE MPU_uxTaskGetSystemState( xTaskStatusType *pxTaskStatusArray, unsigned portBASE_TYPE uxArraySize, unsigned long *pulTotalRunTime );\r
 198 xQueueHandle MPU_xQueueGenericCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize, unsigned char ucQueueType );\r
 199 signed portBASE_TYPE MPU_xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition );\r
 200 portBASE_TYPE MPU_xQueueGenericReset( xQueueHandle pxQueue, portBASE_TYPE xNewQueue );\r
 201 unsigned portBASE_TYPE MPU_uxQueueMessagesWaiting( const xQueueHandle pxQueue );\r
 202 signed portBASE_TYPE MPU_xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking );\r
 203 xQueueHandle MPU_xQueueCreateMutex( void );\r
 204 xQueueHandle MPU_xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount );\r
 205 portBASE_TYPE MPU_xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime );\r
 206 portBASE_TYPE MPU_xQueueGiveMutexRecursive( xQueueHandle xMutex );\r
 207 signed portBASE_TYPE MPU_xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition );\r
 208 signed portBASE_TYPE MPU_xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking );\r
 209 void MPU_vQueueAddToRegistry( xQueueHandle xQueue, char *pcName );\r
 210 void MPU_vQueueDelete( xQueueHandle xQueue );\r
 211 void *MPU_pvPortMalloc( size_t xSize );\r
 212 void MPU_vPortFree( void *pv );\r
 213 void MPU_vPortInitialiseBlocks( void );\r
 214 size_t MPU_xPortGetFreeHeapSize( void );\r
 215 xQueueSetHandle MPU_xQueueCreateSet( unsigned portBASE_TYPE uxEventQueueLength );\r
 216 xQueueSetMemberHandle MPU_xQueueSelectFromSet( xQueueSetHandle xQueueSet, portTickType xBlockTimeTicks );\r
 217 portBASE_TYPE MPU_xQueueAddToSet( xQueueSetMemberHandle xQueueOrSemaphore, xQueueSetHandle xQueueSet );\r
 218 portBASE_TYPE MPU_xQueueRemoveFromSet( xQueueSetMemberHandle xQueueOrSemaphore, xQueueSetHandle xQueueSet );\r
 219 signed portBASE_TYPE MPU_xQueuePeekFromISR( xQueueHandle xQueue, void * const pvBuffer );\r
 220 \r
 221 /*-----------------------------------------------------------*/\r
 222 \r
 223 /*\r
 224  * See header file for description.\r
 225  */\r
 226 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters, portBASE_TYPE xRunPrivileged )\r
 227 {\r
 228         /* Simulate the stack frame as it would be created by a context switch\r
 229         interrupt. */\r
 230         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 231         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 232         pxTopOfStack--;\r
 233         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 234         pxTopOfStack--;\r
 235         *pxTopOfStack = 0;      /* LR */\r
 236         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 237         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 238         pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 239 \r
 240         if( xRunPrivileged == pdTRUE )\r
 241         {\r
 242                 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\r
 243         }\r
 244         else\r
 245         {\r
 246                 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\r
 247         }\r
 248 \r
 249         return pxTopOfStack;\r
 250 }\r
 251 /*-----------------------------------------------------------*/\r
 252 \r
 253 void vPortSVCHandler( void )\r
 254 {\r
 255         /* Assumes psp was in use. */\r
 256         __asm volatile\r
 257         (\r
 258                 #ifndef USE_PROCESS_STACK       /* Code should not be required if a main() is using the process stack. */\r
 259                         "       tst lr, #4                                              \n"\r
 260                         "       ite eq                                                  \n"\r
 261                         "       mrseq r0, msp                                   \n"\r
 262                         "       mrsne r0, psp                                   \n"\r
 263                 #else\r
 264                         "       mrs r0, psp                                             \n"\r
 265                 #endif\r
 266                         "       b %0                                                    \n"\r
 267                         ::"i"(prvSVCHandler):"r0"\r
 268         );\r
 269 }\r
 270 /*-----------------------------------------------------------*/\r
 271 \r
 272 static void prvSVCHandler(      unsigned long *pulParam )\r
 273 {\r
 274 unsigned char ucSVCNumber;\r
 275 \r
 276         /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and\r
 277         xPSR.  The first argument (r0) is pulParam[ 0 ]. */\r
 278         ucSVCNumber = ( ( unsigned char * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];\r
 279         switch( ucSVCNumber )\r
 280         {\r
 281                 case portSVC_START_SCHEDULER    :       *(portNVIC_SYSPRI1) |= portNVIC_SVC_PRI;\r
 282                                                                                         prvRestoreContextOfFirstTask();\r
 283                                                                                         break;\r
 284 \r
 285                 case portSVC_YIELD                              :       *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 286                                                                                         /* Barriers are normally not required\r
 287                                                                                         but do ensure the code is completely\r
 288                                                                                         within the specified behaviour for the\r
 289                                                                                         architecture. */\r
 290                                                                                         __asm volatile( "dsb" );\r
 291                                                                                         __asm volatile( "isb" );\r
 292 \r
 293                                                                                         break;\r
 294 \r
 295                 case portSVC_RAISE_PRIVILEGE    :       __asm volatile\r
 296                                                                                         (\r
 297                                                                                                 "       mrs r1, control         \n" /* Obtain current control value. */\r
 298                                                                                                 "       bic r1, #1                      \n" /* Set privilege bit. */\r
 299                                                                                                 "       msr control, r1         \n" /* Write back new control value. */\r
 300                                                                                                 :::"r1"\r
 301                                                                                         );\r
 302                                                                                         break;\r
 303 \r
 304                 default                                                 :       /* Unknown SVC call. */\r
 305                                                                                         break;\r
 306         }\r
 307 }\r
 308 /*-----------------------------------------------------------*/\r
 309 \r
 310 static void prvRestoreContextOfFirstTask( void )\r
 311 {\r
 312         __asm volatile\r
 313         (\r
 314                 "       ldr r0, =0xE000ED08                             \n" /* Use the NVIC offset register to locate the stack. */\r
 315                 "       ldr r0, [r0]                                    \n"\r
 316                 "       ldr r0, [r0]                                    \n"\r
 317                 "       msr msp, r0                                             \n" /* Set the msp back to the start of the stack. */\r
 318                 "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 319                 "       ldr r1, [r3]                                    \n"\r
 320                 "       ldr r0, [r1]                                    \n" /* The first item in the TCB is the task top of stack. */\r
 321                 "       add r1, r1, #4                                  \n" /* Move onto the second item in the TCB... */\r
 322                 "       ldr r2, =0xe000ed9c                             \n" /* Region Base Address register. */\r
 323                 "       ldmia r1!, {r4-r11}                             \n" /* Read 4 sets of MPU registers. */\r
 324                 "       stmia r2!, {r4-r11}                             \n" /* Write 4 sets of MPU registers. */\r
 325                 "       ldmia r0!, {r3, r4-r11}                 \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 326                 "       msr control, r3                                 \n"\r
 327                 "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 328                 "       mov r0, #0                                              \n"\r
 329                 "       msr     basepri, r0                                     \n"\r
 330                 "       ldr r14, =0xfffffffd                    \n" /* Load exec return code. */\r
 331                 "       bx r14                                                  \n"\r
 332                 "                                                                       \n"\r
 333                 "       .align 2                                                \n"\r
 334                 "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
 335         );\r
 336 }\r
 337 /*-----------------------------------------------------------*/\r
 338 \r
 339 /*\r
 340  * See header file for description.\r
 341  */\r
 342 portBASE_TYPE xPortStartScheduler( void )\r
 343 {\r
 344         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See\r
 345         http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 346         configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\r
 347 \r
 348         /* Make PendSV and SysTick the same priority as the kernel. */\r
 349         *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
 350         *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
 351 \r
 352         /* Configure the regions in the MPU that are common to all tasks. */\r
 353         prvSetupMPU();\r
 354 \r
 355         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 356         here already. */\r
 357         prvSetupTimerInterrupt();\r
 358 \r
 359         /* Initialise the critical nesting count ready for the first task. */\r
 360         uxCriticalNesting = 0;\r
 361 \r
 362         /* Start the first task. */\r
 363         __asm volatile( "       svc %0                  \n"\r
 364                                         :: "i" (portSVC_START_SCHEDULER) );\r
 365 \r
 366         /* Should not get here! */\r
 367         return 0;\r
 368 }\r
 369 /*-----------------------------------------------------------*/\r
 370 \r
 371 void vPortEndScheduler( void )\r
 372 {\r
 373         /* Not implemented in ports where there is nothing to return to.\r
 374         Artificially force an assert. */\r
 375         configASSERT( uxCriticalNesting == 1000UL );\r
 376 }\r
 377 /*-----------------------------------------------------------*/\r
 378 \r
 379 void vPortEnterCritical( void )\r
 380 {\r
 381 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 382 \r
 383         portDISABLE_INTERRUPTS();\r
 384         uxCriticalNesting++;\r
 385 \r
 386         portRESET_PRIVILEGE( xRunningPrivileged );\r
 387 }\r
 388 /*-----------------------------------------------------------*/\r
 389 \r
 390 void vPortExitCritical( void )\r
 391 {\r
 392 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 393 \r
 394         configASSERT( uxCriticalNesting );\r
 395         uxCriticalNesting--;\r
 396         if( uxCriticalNesting == 0 )\r
 397         {\r
 398                 portENABLE_INTERRUPTS();\r
 399         }\r
 400         portRESET_PRIVILEGE( xRunningPrivileged );\r
 401 }\r
 402 /*-----------------------------------------------------------*/\r
 403 \r
 404 void xPortPendSVHandler( void )\r
 405 {\r
 406         /* This is a naked function. */\r
 407 \r
 408         __asm volatile\r
 409         (\r
 410                 "       mrs r0, psp                                                     \n"\r
 411                 "                                                                               \n"\r
 412                 "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 413                 "       ldr     r2, [r3]                                                \n"\r
 414                 "                                                                               \n"\r
 415                 "       mrs r1, control                                         \n"\r
 416                 "       stmdb r0!, {r1, r4-r11}                         \n" /* Save the remaining registers. */\r
 417                 "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 418                 "                                                                               \n"\r
 419                 "       stmdb sp!, {r3, r14}                            \n"\r
 420                 "       mov r0, %0                                                      \n"\r
 421                 "       msr basepri, r0                                         \n"\r
 422                 "       bl vTaskSwitchContext                           \n"\r
 423                 "       mov r0, #0                                                      \n"\r
 424                 "       msr basepri, r0                                         \n"\r
 425                 "       ldmia sp!, {r3, r14}                            \n"\r
 426                 "                                                                               \n"     /* Restore the context. */\r
 427                 "       ldr r1, [r3]                                            \n"\r
 428                 "       ldr r0, [r1]                                            \n" /* The first item in the TCB is the task top of stack. */\r
 429                 "       add r1, r1, #4                                          \n" /* Move onto the second item in the TCB... */\r
 430                 "       ldr r2, =0xe000ed9c                                     \n" /* Region Base Address register. */\r
 431                 "       ldmia r1!, {r4-r11}                                     \n" /* Read 4 sets of MPU registers. */\r
 432                 "       stmia r2!, {r4-r11}                                     \n" /* Write 4 sets of MPU registers. */\r
 433                 "       ldmia r0!, {r3, r4-r11}                         \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 434                 "       msr control, r3                                         \n"\r
 435                 "                                                                               \n"\r
 436                 "       msr psp, r0                                                     \n"\r
 437                 "       bx r14                                                          \n"\r
 438                 "                                                                               \n"\r
 439                 "       .align 2                                                        \n"\r
 440                 "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 441                 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 442         );\r
 443 }\r
 444 /*-----------------------------------------------------------*/\r
 445 \r
 446 void xPortSysTickHandler( void )\r
 447 {\r
 448 unsigned long ulDummy;\r
 449 \r
 450         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
 451         {\r
 452                 /* Increment the RTOS tick. */\r
 453                 if( xTaskIncrementTick() != pdFALSE )\r
 454                 {\r
 455                         /* Pend a context switch. */\r
 456                         *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 457                 }\r
 458         }\r
 459         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
 460 }\r
 461 /*-----------------------------------------------------------*/\r
 462 \r
 463 /*\r
 464  * Setup the systick timer to generate the tick interrupts at the required\r
 465  * frequency.\r
 466  */\r
 467 static void prvSetupTimerInterrupt( void )\r
 468 {\r
 469         /* Configure SysTick to interrupt at the requested rate. */\r
 470         *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 471         *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
 472 }\r
 473 /*-----------------------------------------------------------*/\r
 474 \r
 475 static void prvSetupMPU( void )\r
 476 {\r
 477 extern unsigned long __privileged_functions_end__[];\r
 478 extern unsigned long __FLASH_segment_start__[];\r
 479 extern unsigned long __FLASH_segment_end__[];\r
 480 extern unsigned long __privileged_data_start__[];\r
 481 extern unsigned long __privileged_data_end__[];\r
 482 \r
 483         /* Check the expected MPU is present. */\r
 484         if( *portMPU_TYPE == portEXPECTED_MPU_TYPE_VALUE )\r
 485         {\r
 486                 /* First setup the entire flash for unprivileged read only access. */\r
 487         *portMPU_REGION_BASE_ADDRESS =  ( ( unsigned long ) __FLASH_segment_start__ ) | /* Base address. */\r
 488                                                                                 ( portMPU_REGION_VALID ) |\r
 489                                                                                 ( portUNPRIVILEGED_FLASH_REGION );\r
 490 \r
 491                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_READ_ONLY ) |\r
 492                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 493                                                                                 ( prvGetMPURegionSizeSetting( ( unsigned long ) __FLASH_segment_end__ - ( unsigned long ) __FLASH_segment_start__ ) ) |\r
 494                                                                                 ( portMPU_REGION_ENABLE );\r
 495 \r
 496                 /* Setup the first 16K for privileged only access (even though less\r
 497                 than 10K is actually being used).  This is where the kernel code is\r
 498                 placed. */\r
 499         *portMPU_REGION_BASE_ADDRESS =  ( ( unsigned long ) __FLASH_segment_start__ ) | /* Base address. */\r
 500                                                                                 ( portMPU_REGION_VALID ) |\r
 501                                                                                 ( portPRIVILEGED_FLASH_REGION );\r
 502 \r
 503                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
 504                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 505                                                                                 ( prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_functions_end__ - ( unsigned long ) __FLASH_segment_start__ ) ) |\r
 506                                                                                 ( portMPU_REGION_ENABLE );\r
 507 \r
 508                 /* Setup the privileged data RAM region.  This is where the kernel data\r
 509                 is placed. */\r
 510                 *portMPU_REGION_BASE_ADDRESS =  ( ( unsigned long ) __privileged_data_start__ ) | /* Base address. */\r
 511                                                                                 ( portMPU_REGION_VALID ) |\r
 512                                                                                 ( portPRIVILEGED_RAM_REGION );\r
 513 \r
 514                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 515                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 516                                                                                 prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_data_end__ - ( unsigned long ) __privileged_data_start__ ) |\r
 517                                                                                 ( portMPU_REGION_ENABLE );\r
 518 \r
 519                 /* By default allow everything to access the general peripherals.  The\r
 520                 system peripherals and registers are protected. */\r
 521                 *portMPU_REGION_BASE_ADDRESS =  ( portPERIPHERALS_START_ADDRESS ) |\r
 522                                                                                 ( portMPU_REGION_VALID ) |\r
 523                                                                                 ( portGENERAL_PERIPHERALS_REGION );\r
 524 \r
 525                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
 526                                                                                 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\r
 527                                                                                 ( portMPU_REGION_ENABLE );\r
 528 \r
 529                 /* Enable the memory fault exception. */\r
 530                 *portNVIC_SYS_CTRL_STATE |= portNVIC_MEM_FAULT_ENABLE;\r
 531 \r
 532                 /* Enable the MPU with the background region configured. */\r
 533                 *portMPU_CTRL |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
 534         }\r
 535 }\r
 536 /*-----------------------------------------------------------*/\r
 537 \r
 538 static unsigned long prvGetMPURegionSizeSetting( unsigned long ulActualSizeInBytes )\r
 539 {\r
 540 unsigned long ulRegionSize, ulReturnValue = 4;\r
 541 \r
 542         /* 32 is the smallest region size, 31 is the largest valid value for\r
 543         ulReturnValue. */\r
 544         for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\r
 545         {\r
 546                 if( ulActualSizeInBytes <= ulRegionSize )\r
 547                 {\r
 548                         break;\r
 549                 }\r
 550                 else\r
 551                 {\r
 552                         ulReturnValue++;\r
 553                 }\r
 554         }\r
 555 \r
 556         /* Shift the code by one before returning so it can be written directly\r
 557         into the the correct bit position of the attribute register. */\r
 558         return ( ulReturnValue << 1UL );\r
 559 }\r
 560 /*-----------------------------------------------------------*/\r
 561 \r
 562 static portBASE_TYPE prvRaisePrivilege( void )\r
 563 {\r
 564         __asm volatile\r
 565         (\r
 566                 "       mrs r0, control                                         \n"\r
 567                 "       tst r0, #1                                                      \n" /* Is the task running privileged? */\r
 568                 "       itte ne                                                         \n"\r
 569                 "       movne r0, #0                                            \n" /* CONTROL[0]!=0, return false. */\r
 570                 "       svcne %0                                                        \n" /* Switch to privileged. */\r
 571                 "       moveq r0, #1                                            \n" /* CONTROL[0]==0, return true. */\r
 572                 "       bx lr                                                           \n"\r
 573                 :: "i" (portSVC_RAISE_PRIVILEGE) : "r0"\r
 574         );\r
 575 \r
 576         return 0;\r
 577 }\r
 578 /*-----------------------------------------------------------*/\r
 579 \r
 580 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, portSTACK_TYPE *pxBottomOfStack, unsigned short usStackDepth )\r
 581 {\r
 582 extern unsigned long __SRAM_segment_start__[];\r
 583 extern unsigned long __SRAM_segment_end__[];\r
 584 extern unsigned long __privileged_data_start__[];\r
 585 extern unsigned long __privileged_data_end__[];\r
 586 long lIndex;\r
 587 unsigned long ul;\r
 588 \r
 589         if( xRegions == NULL )\r
 590         {\r
 591                 /* No MPU regions are specified so allow access to all RAM. */\r
 592         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 593                                 ( ( unsigned long ) __SRAM_segment_start__ ) | /* Base address. */\r
 594                                 ( portMPU_REGION_VALID ) |\r
 595                                 ( portSTACK_REGION );\r
 596 \r
 597                 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 598                                 ( portMPU_REGION_READ_WRITE ) |\r
 599                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 600                                 ( prvGetMPURegionSizeSetting( ( unsigned long ) __SRAM_segment_end__ - ( unsigned long ) __SRAM_segment_start__ ) ) |\r
 601                                 ( portMPU_REGION_ENABLE );\r
 602 \r
 603                 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
 604                 just removed the privileged only parameters. */\r
 605                 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =\r
 606                                 ( ( unsigned long ) __privileged_data_start__ ) | /* Base address. */\r
 607                                 ( portMPU_REGION_VALID ) |\r
 608                                 ( portSTACK_REGION + 1 );\r
 609 \r
 610                 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =\r
 611                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 612                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 613                                 prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_data_end__ - ( unsigned long ) __privileged_data_start__ ) |\r
 614                                 ( portMPU_REGION_ENABLE );\r
 615 \r
 616                 /* Invalidate all other regions. */\r
 617                 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 618                 {\r
 619                         xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 620                         xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 621                 }\r
 622         }\r
 623         else\r
 624         {\r
 625                 /* This function is called automatically when the task is created - in\r
 626                 which case the stack region parameters will be valid.  At all other\r
 627                 times the stack parameters will not be valid and it is assumed that the\r
 628                 stack region has already been configured. */\r
 629                 if( usStackDepth > 0 )\r
 630                 {\r
 631                         /* Define the region that allows access to the stack. */\r
 632                         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 633                                         ( ( unsigned long ) pxBottomOfStack ) |\r
 634                                         ( portMPU_REGION_VALID ) |\r
 635                                         ( portSTACK_REGION ); /* Region number. */\r
 636 \r
 637                         xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 638                                         ( portMPU_REGION_READ_WRITE ) | /* Read and write. */\r
 639                                         ( prvGetMPURegionSizeSetting( ( unsigned long ) usStackDepth * ( unsigned long ) sizeof( portSTACK_TYPE ) ) ) |\r
 640                                         ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 641                                         ( portMPU_REGION_ENABLE );\r
 642                 }\r
 643 \r
 644                 lIndex = 0;\r
 645 \r
 646                 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 647                 {\r
 648                         if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\r
 649                         {\r
 650                                 /* Translate the generic region definition contained in\r
 651                                 xRegions into the CM3 specific MPU settings that are then\r
 652                                 stored in xMPUSettings. */\r
 653                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\r
 654                                                 ( ( unsigned long ) xRegions[ lIndex ].pvBaseAddress ) |\r
 655                                                 ( portMPU_REGION_VALID ) |\r
 656                                                 ( portSTACK_REGION + ul ); /* Region number. */\r
 657 \r
 658                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute =\r
 659                                                 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\r
 660                                                 ( xRegions[ lIndex ].ulParameters ) |\r
 661                                                 ( portMPU_REGION_ENABLE );\r
 662                         }\r
 663                         else\r
 664                         {\r
 665                                 /* Invalidate the region. */\r
 666                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 667                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 668                         }\r
 669 \r
 670                         lIndex++;\r
 671                 }\r
 672         }\r
 673 }\r
 674 /*-----------------------------------------------------------*/\r
 675 \r
 676 signed portBASE_TYPE MPU_xTaskGenericCreate( pdTASK_CODE pvTaskCode, const char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions )\r
 677 {\r
 678 signed portBASE_TYPE xReturn;\r
 679 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 680 \r
 681         xReturn = xTaskGenericCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask, puxStackBuffer, xRegions );\r
 682         portRESET_PRIVILEGE( xRunningPrivileged );\r
 683         return xReturn;\r
 684 }\r
 685 /*-----------------------------------------------------------*/\r
 686 \r
 687 void MPU_vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const xRegions )\r
 688 {\r
 689 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 690 \r
 691         vTaskAllocateMPURegions( xTask, xRegions );\r
 692         portRESET_PRIVILEGE( xRunningPrivileged );\r
 693 }\r
 694 /*-----------------------------------------------------------*/\r
 695 \r
 696 #if ( INCLUDE_vTaskDelete == 1 )\r
 697         void MPU_vTaskDelete( xTaskHandle pxTaskToDelete )\r
 698         {\r
 699     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 700 \r
 701                 vTaskDelete( pxTaskToDelete );\r
 702         portRESET_PRIVILEGE( xRunningPrivileged );\r
 703         }\r
 704 #endif\r
 705 /*-----------------------------------------------------------*/\r
 706 \r
 707 #if ( INCLUDE_vTaskDelayUntil == 1 )\r
 708         void MPU_vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement )\r
 709         {\r
 710     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 711 \r
 712                 vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );\r
 713         portRESET_PRIVILEGE( xRunningPrivileged );\r
 714         }\r
 715 #endif\r
 716 /*-----------------------------------------------------------*/\r
 717 \r
 718 #if ( INCLUDE_vTaskDelay == 1 )\r
 719         void MPU_vTaskDelay( portTickType xTicksToDelay )\r
 720         {\r
 721     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 722 \r
 723                 vTaskDelay( xTicksToDelay );\r
 724         portRESET_PRIVILEGE( xRunningPrivileged );\r
 725         }\r
 726 #endif\r
 727 /*-----------------------------------------------------------*/\r
 728 \r
 729 #if ( INCLUDE_uxTaskPriorityGet == 1 )\r
 730         unsigned portBASE_TYPE MPU_uxTaskPriorityGet( xTaskHandle pxTask )\r
 731         {\r
 732         unsigned portBASE_TYPE uxReturn;\r
 733     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 734 \r
 735                 uxReturn = uxTaskPriorityGet( pxTask );\r
 736         portRESET_PRIVILEGE( xRunningPrivileged );\r
 737                 return uxReturn;\r
 738         }\r
 739 #endif\r
 740 /*-----------------------------------------------------------*/\r
 741 \r
 742 #if ( INCLUDE_vTaskPrioritySet == 1 )\r
 743         void MPU_vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority )\r
 744         {\r
 745     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 746 \r
 747                 vTaskPrioritySet( pxTask, uxNewPriority );\r
 748         portRESET_PRIVILEGE( xRunningPrivileged );\r
 749         }\r
 750 #endif\r
 751 /*-----------------------------------------------------------*/\r
 752 \r
 753 #if ( INCLUDE_eTaskGetState == 1 )\r
 754         eTaskState MPU_eTaskGetState( xTaskHandle pxTask )\r
 755         {\r
 756     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 757         eTaskState eReturn;\r
 758 \r
 759                 eReturn = eTaskGetState( pxTask );\r
 760         portRESET_PRIVILEGE( xRunningPrivileged );\r
 761                 return eReturn;\r
 762         }\r
 763 #endif\r
 764 /*-----------------------------------------------------------*/\r
 765 \r
 766 #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\r
 767         xTaskHandle MPU_xTaskGetIdleTaskHandle( void )\r
 768         {\r
 769         xTaskHandle xReturn;\r
 770     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 771 \r
 772                 xReturn = xTaskGetIdleTaskHandle();\r
 773         portRESET_PRIVILEGE( xRunningPrivileged );\r
 774                 return eReturn;\r
 775         }\r
 776 #endif\r
 777 /*-----------------------------------------------------------*/\r
 778 \r
 779 #if ( INCLUDE_vTaskSuspend == 1 )\r
 780         void MPU_vTaskSuspend( xTaskHandle pxTaskToSuspend )\r
 781         {\r
 782     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 783 \r
 784                 vTaskSuspend( pxTaskToSuspend );\r
 785         portRESET_PRIVILEGE( xRunningPrivileged );\r
 786         }\r
 787 #endif\r
 788 /*-----------------------------------------------------------*/\r
 789 \r
 790 #if ( INCLUDE_vTaskSuspend == 1 )\r
 791         signed portBASE_TYPE MPU_xTaskIsTaskSuspended( xTaskHandle xTask )\r
 792         {\r
 793         signed portBASE_TYPE xReturn;\r
 794     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 795 \r
 796                 xReturn = xTaskIsTaskSuspended( xTask );\r
 797         portRESET_PRIVILEGE( xRunningPrivileged );\r
 798                 return xReturn;\r
 799         }\r
 800 #endif\r
 801 /*-----------------------------------------------------------*/\r
 802 \r
 803 #if ( INCLUDE_vTaskSuspend == 1 )\r
 804         void MPU_vTaskResume( xTaskHandle pxTaskToResume )\r
 805         {\r
 806     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 807 \r
 808                 vTaskResume( pxTaskToResume );\r
 809         portRESET_PRIVILEGE( xRunningPrivileged );\r
 810         }\r
 811 #endif\r
 812 /*-----------------------------------------------------------*/\r
 813 \r
 814 void MPU_vTaskSuspendAll( void )\r
 815 {\r
 816 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 817 \r
 818         vTaskSuspendAll();\r
 819     portRESET_PRIVILEGE( xRunningPrivileged );\r
 820 }\r
 821 /*-----------------------------------------------------------*/\r
 822 \r
 823 signed portBASE_TYPE MPU_xTaskResumeAll( void )\r
 824 {\r
 825 signed portBASE_TYPE xReturn;\r
 826 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 827 \r
 828         xReturn = xTaskResumeAll();\r
 829     portRESET_PRIVILEGE( xRunningPrivileged );\r
 830     return xReturn;\r
 831 }\r
 832 /*-----------------------------------------------------------*/\r
 833 \r
 834 portTickType MPU_xTaskGetTickCount( void )\r
 835 {\r
 836 portTickType xReturn;\r
 837 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 838 \r
 839         xReturn = xTaskGetTickCount();\r
 840     portRESET_PRIVILEGE( xRunningPrivileged );\r
 841         return xReturn;\r
 842 }\r
 843 /*-----------------------------------------------------------*/\r
 844 \r
 845 unsigned portBASE_TYPE MPU_uxTaskGetNumberOfTasks( void )\r
 846 {\r
 847 unsigned portBASE_TYPE uxReturn;\r
 848 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 849 \r
 850         uxReturn = uxTaskGetNumberOfTasks();\r
 851     portRESET_PRIVILEGE( xRunningPrivileged );\r
 852         return uxReturn;\r
 853 }\r
 854 /*-----------------------------------------------------------*/\r
 855 \r
 856 #if ( configUSE_TRACE_FACILITY == 1 )\r
 857         void MPU_vTaskList( char *pcWriteBuffer )\r
 858         {\r
 859         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 860 \r
 861                 vTaskList( pcWriteBuffer );\r
 862                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 863         }\r
 864 #endif\r
 865 /*-----------------------------------------------------------*/\r
 866 \r
 867 #if ( configGENERATE_RUN_TIME_STATS == 1 )\r
 868         void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer )\r
 869         {\r
 870     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 871 \r
 872                 vTaskGetRunTimeStats( pcWriteBuffer );\r
 873         portRESET_PRIVILEGE( xRunningPrivileged );\r
 874         }\r
 875 #endif\r
 876 /*-----------------------------------------------------------*/\r
 877 \r
 878 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 879         void MPU_vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxTagValue )\r
 880         {\r
 881     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 882 \r
 883                 vTaskSetApplicationTaskTag( xTask, pxTagValue );\r
 884         portRESET_PRIVILEGE( xRunningPrivileged );\r
 885         }\r
 886 #endif\r
 887 /*-----------------------------------------------------------*/\r
 888 \r
 889 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 890         pdTASK_HOOK_CODE MPU_xTaskGetApplicationTaskTag( xTaskHandle xTask )\r
 891         {\r
 892         pdTASK_HOOK_CODE xReturn;\r
 893     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 894 \r
 895                 xReturn = xTaskGetApplicationTaskTag( xTask );\r
 896         portRESET_PRIVILEGE( xRunningPrivileged );\r
 897                 return xReturn;\r
 898         }\r
 899 #endif\r
 900 /*-----------------------------------------------------------*/\r
 901 \r
 902 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 903         portBASE_TYPE MPU_xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter )\r
 904         {\r
 905         portBASE_TYPE xReturn;\r
 906     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 907 \r
 908                 xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );\r
 909         portRESET_PRIVILEGE( xRunningPrivileged );\r
 910                 return xReturn;\r
 911         }\r
 912 #endif\r
 913 /*-----------------------------------------------------------*/\r
 914 \r
 915 #if ( configUSE_TRACE_FACILITY == 1 )\r
 916         unsigned portBASE_TYPE MPU_uxTaskGetSystemState( xTaskStatusType *pxTaskStatusArray, unsigned portBASE_TYPE uxArraySize, unsigned long *pulTotalRunTime )\r
 917         {\r
 918         unsigned portBASE_TYPE uxReturn;\r
 919         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 920 \r
 921                 uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );\r
 922                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 923                 return xReturn;\r
 924         }\r
 925 #endif\r
 926 /*-----------------------------------------------------------*/\r
 927 \r
 928 #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )\r
 929         unsigned portBASE_TYPE MPU_uxTaskGetStackHighWaterMark( xTaskHandle xTask )\r
 930         {\r
 931         unsigned portBASE_TYPE uxReturn;\r
 932     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 933 \r
 934                 uxReturn = uxTaskGetStackHighWaterMark( xTask );\r
 935         portRESET_PRIVILEGE( xRunningPrivileged );\r
 936                 return uxReturn;\r
 937         }\r
 938 #endif\r
 939 /*-----------------------------------------------------------*/\r
 940 \r
 941 #if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 )\r
 942         xTaskHandle MPU_xTaskGetCurrentTaskHandle( void )\r
 943         {\r
 944         xTaskHandle xReturn;\r
 945     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 946 \r
 947                 xReturn = xTaskGetCurrentTaskHandle();\r
 948         portRESET_PRIVILEGE( xRunningPrivileged );\r
 949                 return xReturn;\r
 950         }\r
 951 #endif\r
 952 /*-----------------------------------------------------------*/\r
 953 \r
 954 #if ( INCLUDE_xTaskGetSchedulerState == 1 )\r
 955         portBASE_TYPE MPU_xTaskGetSchedulerState( void )\r
 956         {\r
 957         portBASE_TYPE xReturn;\r
 958     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 959 \r
 960                 xReturn = xTaskGetSchedulerState();\r
 961         portRESET_PRIVILEGE( xRunningPrivileged );\r
 962                 return xReturn;\r
 963         }\r
 964 #endif\r
 965 /*-----------------------------------------------------------*/\r
 966 \r
 967 xQueueHandle MPU_xQueueGenericCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize, unsigned char ucQueueType )\r
 968 {\r
 969 xQueueHandle xReturn;\r
 970 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 971 \r
 972         xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );\r
 973         portRESET_PRIVILEGE( xRunningPrivileged );\r
 974         return xReturn;\r
 975 }\r
 976 /*-----------------------------------------------------------*/\r
 977 \r
 978 portBASE_TYPE MPU_xQueueGenericReset( xQueueHandle pxQueue, portBASE_TYPE xNewQueue )\r
 979 {\r
 980 portBASE_TYPE xReturn;\r
 981 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 982 \r
 983         xReturn = xQueueGenericReset( pxQueue, xNewQueue );\r
 984         portRESET_PRIVILEGE( xRunningPrivileged );\r
 985         return xReturn;\r
 986 }\r
 987 /*-----------------------------------------------------------*/\r
 988 \r
 989 signed portBASE_TYPE MPU_xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition )\r
 990 {\r
 991 signed portBASE_TYPE xReturn;\r
 992 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 993 \r
 994         xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );\r
 995         portRESET_PRIVILEGE( xRunningPrivileged );\r
 996         return xReturn;\r
 997 }\r
 998 /*-----------------------------------------------------------*/\r
 999 \r
1000 unsigned portBASE_TYPE MPU_uxQueueMessagesWaiting( const xQueueHandle pxQueue )\r
1001 {\r
1002 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1003 unsigned portBASE_TYPE uxReturn;\r
1004 \r
1005         uxReturn = uxQueueMessagesWaiting( pxQueue );\r
1006         portRESET_PRIVILEGE( xRunningPrivileged );\r
1007         return uxReturn;\r
1008 }\r
1009 /*-----------------------------------------------------------*/\r
1010 \r
1011 signed portBASE_TYPE MPU_xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking )\r
1012 {\r
1013 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1014 signed portBASE_TYPE xReturn;\r
1015 \r
1016         xReturn = xQueueGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking );\r
1017         portRESET_PRIVILEGE( xRunningPrivileged );\r
1018         return xReturn;\r
1019 }\r
1020 /*-----------------------------------------------------------*/\r
1021 \r
1022 signed portBASE_TYPE MPU_xQueuePeekFromISR( xQueueHandle pxQueue, void * const pvBuffer )\r
1023 {\r
1024 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1025 signed portBASE_TYPE xReturn;\r
1026 \r
1027         xReturn = xQueuePeekFromISR( pxQueue, pvBuffer );\r
1028         portRESET_PRIVILEGE( xRunningPrivileged );\r
1029         return xReturn;\r
1030 }\r
1031 /*-----------------------------------------------------------*/\r
1032 \r
1033 #if ( configUSE_MUTEXES == 1 )\r
1034         xQueueHandle MPU_xQueueCreateMutex( void )\r
1035         {\r
1036     xQueueHandle xReturn;\r
1037         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1038 \r
1039                 xReturn = xQueueCreateMutex( queueQUEUE_TYPE_MUTEX );\r
1040                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1041                 return xReturn;\r
1042         }\r
1043 #endif\r
1044 /*-----------------------------------------------------------*/\r
1045 \r
1046 #if configUSE_COUNTING_SEMAPHORES == 1\r
1047         xQueueHandle MPU_xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount )\r
1048         {\r
1049     xQueueHandle xReturn;\r
1050         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1051 \r
1052                 xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );\r
1053                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1054                 return xReturn;\r
1055         }\r
1056 #endif\r
1057 /*-----------------------------------------------------------*/\r
1058 \r
1059 #if ( configUSE_MUTEXES == 1 )\r
1060         portBASE_TYPE MPU_xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime )\r
1061         {\r
1062         portBASE_TYPE xReturn;\r
1063         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1064 \r
1065                 xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );\r
1066                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1067                 return xReturn;\r
1068         }\r
1069 #endif\r
1070 /*-----------------------------------------------------------*/\r
1071 \r
1072 #if ( configUSE_MUTEXES == 1 )\r
1073         portBASE_TYPE MPU_xQueueGiveMutexRecursive( xQueueHandle xMutex )\r
1074         {\r
1075         portBASE_TYPE xReturn;\r
1076         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1077 \r
1078                 xReturn = xQueueGiveMutexRecursive( xMutex );\r
1079                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1080                 return xReturn;\r
1081         }\r
1082 #endif\r
1083 /*-----------------------------------------------------------*/\r
1084 \r
1085 #if ( configUSE_QUEUE_SETS == 1 )\r
1086         xQueueSetHandle MPU_xQueueCreateSet( unsigned portBASE_TYPE uxEventQueueLength )\r
1087         {\r
1088         xQueueSetHandle xReturn;\r
1089         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1090 \r
1091                 xReturn = xQueueCreateSet( uxEventQueueLength );\r
1092                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1093                 return xReturn;\r
1094         }\r
1095 #endif\r
1096 /*-----------------------------------------------------------*/\r
1097 \r
1098 #if ( configUSE_QUEUE_SETS == 1 )\r
1099         xQueueSetMemberHandle MPU_xQueueSelectFromSet( xQueueSetHandle xQueueSet, portTickType xBlockTimeTicks )\r
1100         {\r
1101         xQueueSetMemberHandle xReturn;\r
1102         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1103 \r
1104                 xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks );\r
1105                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1106                 return xReturn;\r
1107         }\r
1108 #endif\r
1109 /*-----------------------------------------------------------*/\r
1110 \r
1111 #if ( configUSE_QUEUE_SETS == 1 )\r
1112         portBASE_TYPE MPU_xQueueAddToSet( xQueueSetMemberHandle xQueueOrSemaphore, xQueueSetHandle xQueueSet )\r
1113         {\r
1114         portBASE_TYPE xReturn;\r
1115         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1116 \r
1117                 xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet );\r
1118                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1119                 return xReturn;\r
1120         }\r
1121 #endif\r
1122 /*-----------------------------------------------------------*/\r
1123 \r
1124 #if ( configUSE_QUEUE_SETS == 1 )\r
1125         portBASE_TYPE MPU_xQueueRemoveFromSet( xQueueSetMemberHandle xQueueOrSemaphore, xQueueSetHandle xQueueSet )\r
1126         {\r
1127         portBASE_TYPE xReturn;\r
1128         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1129 \r
1130                 xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );\r
1131                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1132                 return xReturn;\r
1133         }\r
1134 #endif\r
1135 /*-----------------------------------------------------------*/\r
1136 \r
1137 #if configUSE_ALTERNATIVE_API == 1\r
1138         signed portBASE_TYPE MPU_xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition )\r
1139         {\r
1140         signed portBASE_TYPE xReturn;\r
1141         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1142 \r
1143                 xReturn =       signed portBASE_TYPE xQueueAltGenericSend( pxQueue, pvItemToQueue, xTicksToWait, xCopyPosition );\r
1144                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1145                 return xReturn;\r
1146         }\r
1147 #endif\r
1148 /*-----------------------------------------------------------*/\r
1149 \r
1150 #if configUSE_ALTERNATIVE_API == 1\r
1151         signed portBASE_TYPE MPU_xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking )\r
1152         {\r
1153     signed portBASE_TYPE xReturn;\r
1154         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1155 \r
1156                 xReturn = xQueueAltGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking );\r
1157                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1158                 return xReturn;\r
1159         }\r
1160 #endif\r
1161 /*-----------------------------------------------------------*/\r
1162 \r
1163 #if configQUEUE_REGISTRY_SIZE > 0\r
1164         void MPU_vQueueAddToRegistry( xQueueHandle xQueue, char *pcName )\r
1165         {\r
1166         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1167 \r
1168                 vQueueAddToRegistry( xQueue, pcName );\r
1169 \r
1170                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1171         }\r
1172 #endif\r
1173 /*-----------------------------------------------------------*/\r
1174 \r
1175 void MPU_vQueueDelete( xQueueHandle xQueue )\r
1176 {\r
1177 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1178 \r
1179         vQueueDelete( xQueue );\r
1180 \r
1181         portRESET_PRIVILEGE( xRunningPrivileged );\r
1182 }\r
1183 /*-----------------------------------------------------------*/\r
1184 \r
1185 void *MPU_pvPortMalloc( size_t xSize )\r
1186 {\r
1187 void *pvReturn;\r
1188 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1189 \r
1190         pvReturn = pvPortMalloc( xSize );\r
1191 \r
1192         portRESET_PRIVILEGE( xRunningPrivileged );\r
1193 \r
1194         return pvReturn;\r
1195 }\r
1196 /*-----------------------------------------------------------*/\r
1197 \r
1198 void MPU_vPortFree( void *pv )\r
1199 {\r
1200 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1201 \r
1202         vPortFree( pv );\r
1203 \r
1204         portRESET_PRIVILEGE( xRunningPrivileged );\r
1205 }\r
1206 /*-----------------------------------------------------------*/\r
1207 \r
1208 void MPU_vPortInitialiseBlocks( void )\r
1209 {\r
1210 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1211 \r
1212         vPortInitialiseBlocks();\r
1213 \r
1214         portRESET_PRIVILEGE( xRunningPrivileged );\r
1215 }\r
1216 /*-----------------------------------------------------------*/\r
1217 \r
1218 size_t MPU_xPortGetFreeHeapSize( void )\r
1219 {\r
1220 size_t xReturn;\r
1221 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1222 \r
1223         xReturn = xPortGetFreeHeapSize();\r
1224 \r
1225         portRESET_PRIVILEGE( xRunningPrivileged );\r
1226 \r
1227         return xReturn;\r
1228 }\r
1229 \r
1230 /* Functions that the application writer wants to execute in privileged mode\r
1231 can be defined in application_defined_privileged_functions.h.  The functions\r
1232 must take the same format as those above whereby the privilege state on exit\r
1233 equals the privilege state on entry.  For example:\r
1234 \r
1235 void MPU_FunctionName( [parameters ] )\r
1236 {\r
1237 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1238 \r
1239         FunctionName( [parameters ] );\r
1240 \r
1241         portRESET_PRIVILEGE( xRunningPrivileged );\r
1242 }\r
1243 */\r
1244 \r
1245 #if configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS == 1\r
1246         #include "application_defined_privileged_functions.h"\r
1247 #endif\r
1248 \r