git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c

   1 /*\r
   2     FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
   3 \r
   4 \r
   5     ***************************************************************************\r
   6      *                                                                       *\r
   7      *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
   8      *    Complete, revised, and edited pdf reference manuals are also       *\r
   9      *    available.                                                         *\r
  10      *                                                                       *\r
  11      *    Purchasing FreeRTOS documentation will not only help you, by       *\r
  12      *    ensuring you get running as quickly as possible and with an        *\r
  13      *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
  14      *    the FreeRTOS project to continue with its mission of providing     *\r
  15      *    professional grade, cross platform, de facto standard solutions    *\r
  16      *    for microcontrollers - completely free of charge!                  *\r
  17      *                                                                       *\r
  18      *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
  19      *                                                                       *\r
  20      *    Thank you for using FreeRTOS, and thank you for your support!      *\r
  21      *                                                                       *\r
  22     ***************************************************************************\r
  23 \r
  24 \r
  25     This file is part of the FreeRTOS distribution.\r
  26 \r
  27     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  28     the terms of the GNU General Public License (version 2) as published by the\r
  29     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
  30     >>>NOTE<<< The modification to the GPL is included to allow you to\r
  31     distribute a combined work that includes FreeRTOS without being obliged to\r
  32     provide the source code for proprietary components outside of the FreeRTOS\r
  33     kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
  34     WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
  35     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
  36     more details. You should have received a copy of the GNU General Public\r
  37     License and the FreeRTOS license exception along with FreeRTOS; if not it\r
  38     can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
  39     by writing to Richard Barry, contact details for whom are available on the\r
  40     FreeRTOS WEB site.\r
  41 \r
  42     1 tab == 4 spaces!\r
  43 \r
  44     ***************************************************************************\r
  45      *                                                                       *\r
  46      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  47      *    not run, what could be wrong?                                      *\r
  48      *                                                                       *\r
  49      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  50      *                                                                       *\r
  51     ***************************************************************************\r
  52 \r
  53 \r
  54     http://www.FreeRTOS.org - Documentation, training, latest information,\r
  55     license and contact details.\r
  56 \r
  57     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  58     including FreeRTOS+Trace - an indispensable productivity tool.\r
  59 \r
  60     Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell\r
  61     the code with commercial support, indemnification, and middleware, under\r
  62     the OpenRTOS brand: http://www.OpenRTOS.com.  High Integrity Systems also\r
  63     provide a safety engineered and independently SIL3 certified version under\r
  64     the SafeRTOS brand: http://www.SafeRTOS.com.\r
  65 */\r
  66 \r
  67 /*-----------------------------------------------------------\r
  68  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  69  *----------------------------------------------------------*/\r
  70 \r
  71 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
  72 all the API functions to use the MPU wrappers.  That should only be done when\r
  73 task.h is included from an application file. */\r
  74 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  75 \r
  76 /* Scheduler includes. */\r
  77 #include "FreeRTOS.h"\r
  78 #include "task.h"\r
  79 #include "queue.h"\r
  80 \r
  81 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  82 \r
  83 /* Constants required to access and manipulate the NVIC. */\r
  84 #define portNVIC_SYSTICK_CTRL                                   ( ( volatile unsigned long * ) 0xe000e010 )\r
  85 #define portNVIC_SYSTICK_LOAD                                   ( ( volatile unsigned long * ) 0xe000e014 )\r
  86 #define portNVIC_SYSPRI2                                                ( ( volatile unsigned long * ) 0xe000ed20 )\r
  87 #define portNVIC_SYSPRI1                                                ( ( volatile unsigned long * ) 0xe000ed1c )\r
  88 #define portNVIC_SYS_CTRL_STATE                                 ( ( volatile unsigned long * ) 0xe000ed24 )\r
  89 #define portNVIC_MEM_FAULT_ENABLE                               ( 1UL << 16UL )\r
  90 \r
  91 /* Constants required to access and manipulate the MPU. */\r
  92 #define portMPU_TYPE                                                    ( ( volatile unsigned long * ) 0xe000ed90 )\r
  93 #define portMPU_REGION_BASE_ADDRESS                             ( ( volatile unsigned long * ) 0xe000ed9C )\r
  94 #define portMPU_REGION_ATTRIBUTE                                ( ( volatile unsigned long * ) 0xe000edA0 )\r
  95 #define portMPU_CTRL                                                    ( ( volatile unsigned long * ) 0xe000ed94 )\r
  96 #define portEXPECTED_MPU_TYPE_VALUE                             ( 8UL << 8UL ) /* 8 regions, unified. */\r
  97 #define portMPU_ENABLE                                                  ( 0x01UL )\r
  98 #define portMPU_BACKGROUND_ENABLE                               ( 1UL << 2UL )\r
  99 #define portPRIVILEGED_EXECUTION_START_ADDRESS  ( 0UL )\r
 100 #define portMPU_REGION_VALID                                    ( 0x10UL )\r
 101 #define portMPU_REGION_ENABLE                                   ( 0x01UL )\r
 102 #define portPERIPHERALS_START_ADDRESS                   0x40000000UL\r
 103 #define portPERIPHERALS_END_ADDRESS                             0x5FFFFFFFUL\r
 104 \r
 105 /* Constants required to access and manipulate the SysTick. */\r
 106 #define portNVIC_SYSTICK_CLK                                    ( 0x00000004UL )\r
 107 #define portNVIC_SYSTICK_INT                                    ( 0x00000002UL )\r
 108 #define portNVIC_SYSTICK_ENABLE                                 ( 0x00000001UL )\r
 109 #define portNVIC_PENDSV_PRI                                             ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 110 #define portNVIC_SYSTICK_PRI                                    ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 111 #define portNVIC_SVC_PRI                                                ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 112 \r
 113 /* Constants required to set up the initial stack. */\r
 114 #define portINITIAL_XPSR                                                ( 0x01000000 )\r
 115 #define portINITIAL_CONTROL_IF_UNPRIVILEGED             ( 0x03 )\r
 116 #define portINITIAL_CONTROL_IF_PRIVILEGED               ( 0x02 )\r
 117 \r
 118 /* Offsets in the stack to the parameters when inside the SVC handler. */\r
 119 #define portOFFSET_TO_PC                                                ( 6 )\r
 120 \r
 121 /* Set the privilege level to user mode if xRunningPrivileged is false. */\r
 122 #define portRESET_PRIVILEGE( xRunningPrivileged ) if( xRunningPrivileged != pdTRUE ) __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0" :::"r0" )\r
 123 \r
 124 /* Each task maintains its own interrupt status in the critical nesting\r
 125 variable.  Note this is not saved as part of the task context as context\r
 126 switches can only occur when uxCriticalNesting is zero. */\r
 127 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
 128 \r
 129 /*\r
 130  * Setup the timer to generate the tick interrupts.\r
 131  */\r
 132 static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
 133 \r
 134 /*\r
 135  * Configure a number of standard MPU regions that are used by all tasks.\r
 136  */\r
 137 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
 138 \r
 139 /*\r
 140  * Return the smallest MPU region size that a given number of bytes will fit\r
 141  * into.  The region size is returned as the value that should be programmed\r
 142  * into the region attribute register for that region.\r
 143  */\r
 144 static unsigned long prvGetMPURegionSizeSetting( unsigned long ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
 145 \r
 146 /*\r
 147  * Checks to see if being called from the context of an unprivileged task, and\r
 148  * if so raises the privilege level and returns false - otherwise does nothing\r
 149  * other than return true.\r
 150  */\r
 151 static portBASE_TYPE prvRaisePrivilege( void ) __attribute__(( naked ));\r
 152 \r
 153 /*\r
 154  * Standard FreeRTOS exception handlers.\r
 155  */\r
 156 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 157 void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;\r
 158 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 159 \r
 160 /*\r
 161  * Starts the scheduler by restoring the context of the first task to run.\r
 162  */\r
 163 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
 164 \r
 165 /*\r
 166  * C portion of the SVC handler.  The SVC handler is split between an asm entry\r
 167  * and a C wrapper for simplicity of coding and maintenance.\r
 168  */\r
 169 static void prvSVCHandler( unsigned long *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
 170 \r
 171 /*\r
 172  * Prototypes for all the MPU wrappers.\r
 173  */\r
 174 signed portBASE_TYPE MPU_xTaskGenericCreate( pdTASK_CODE pvTaskCode, const signed char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions );\r
 175 void MPU_vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const xRegions );\r
 176 void MPU_vTaskDelete( xTaskHandle pxTaskToDelete );\r
 177 void MPU_vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement );\r
 178 void MPU_vTaskDelay( portTickType xTicksToDelay );\r
 179 unsigned portBASE_TYPE MPU_uxTaskPriorityGet( xTaskHandle pxTask );\r
 180 void MPU_vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority );\r
 181 eTaskState MPU_eTaskStateGet( xTaskHandle pxTask );\r
 182 void MPU_vTaskSuspend( xTaskHandle pxTaskToSuspend );\r
 183 signed portBASE_TYPE MPU_xTaskIsTaskSuspended( xTaskHandle xTask );\r
 184 void MPU_vTaskResume( xTaskHandle pxTaskToResume );\r
 185 void MPU_vTaskSuspendAll( void );\r
 186 signed portBASE_TYPE MPU_xTaskResumeAll( void );\r
 187 portTickType MPU_xTaskGetTickCount( void );\r
 188 unsigned portBASE_TYPE MPU_uxTaskGetNumberOfTasks( void );\r
 189 void MPU_vTaskList( signed char *pcWriteBuffer );\r
 190 void MPU_vTaskGetRunTimeStats( signed char *pcWriteBuffer );\r
 191 void MPU_vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxTagValue );\r
 192 pdTASK_HOOK_CODE MPU_xTaskGetApplicationTaskTag( xTaskHandle xTask );\r
 193 portBASE_TYPE MPU_xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter );\r
 194 unsigned portBASE_TYPE MPU_uxTaskGetStackHighWaterMark( xTaskHandle xTask );\r
 195 xTaskHandle MPU_xTaskGetCurrentTaskHandle( void );\r
 196 portBASE_TYPE MPU_xTaskGetSchedulerState( void );\r
 197 xQueueHandle MPU_xQueueGenericCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize, unsigned char ucQueueType );\r
 198 signed portBASE_TYPE MPU_xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition );\r
 199 unsigned portBASE_TYPE MPU_uxQueueMessagesWaiting( const xQueueHandle pxQueue );\r
 200 signed portBASE_TYPE MPU_xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking );\r
 201 xQueueHandle MPU_xQueueCreateMutex( void );\r
 202 xQueueHandle MPU_xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount );\r
 203 portBASE_TYPE MPU_xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime );\r
 204 portBASE_TYPE MPU_xQueueGiveMutexRecursive( xQueueHandle xMutex );\r
 205 signed portBASE_TYPE MPU_xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition );\r
 206 signed portBASE_TYPE MPU_xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking );\r
 207 void MPU_vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcName );\r
 208 void MPU_vQueueDelete( xQueueHandle xQueue );\r
 209 void *MPU_pvPortMalloc( size_t xSize );\r
 210 void MPU_vPortFree( void *pv );\r
 211 void MPU_vPortInitialiseBlocks( void );\r
 212 size_t MPU_xPortGetFreeHeapSize( void );\r
 213 \r
 214 /*-----------------------------------------------------------*/\r
 215 \r
 216 /*\r
 217  * See header file for description.\r
 218  */\r
 219 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters, portBASE_TYPE xRunPrivileged )\r
 220 {\r
 221         /* Simulate the stack frame as it would be created by a context switch\r
 222         interrupt. */\r
 223         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 224         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 225         pxTopOfStack--;\r
 226         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 227         pxTopOfStack--;\r
 228         *pxTopOfStack = 0;      /* LR */\r
 229         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 230         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 231         pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 232 \r
 233         if( xRunPrivileged == pdTRUE )\r
 234         {\r
 235                 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\r
 236         }\r
 237         else\r
 238         {\r
 239                 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\r
 240         }\r
 241 \r
 242         return pxTopOfStack;\r
 243 }\r
 244 /*-----------------------------------------------------------*/\r
 245 \r
 246 void vPortSVCHandler( void )\r
 247 {\r
 248         /* Assumes psp was in use. */\r
 249         __asm volatile\r
 250         (\r
 251                 #ifndef USE_PROCESS_STACK       /* Code should not be required if a main() is using the process stack. */\r
 252                         "       tst lr, #4                                              \n"\r
 253                         "       ite eq                                                  \n"\r
 254                         "       mrseq r0, msp                                   \n"\r
 255                         "       mrsne r0, psp                                   \n"\r
 256                 #else\r
 257                         "       mrs r0, psp                                             \n"\r
 258                 #endif\r
 259                         "       b %0                                                    \n"\r
 260                         ::"i"(prvSVCHandler):"r0"\r
 261         );\r
 262 }\r
 263 /*-----------------------------------------------------------*/\r
 264 \r
 265 static void prvSVCHandler(      unsigned long *pulParam )\r
 266 {\r
 267 unsigned char ucSVCNumber;\r
 268 \r
 269         /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and\r
 270         xPSR.  The first argument (r0) is pulParam[ 0 ]. */\r
 271         ucSVCNumber = ( ( unsigned char * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];\r
 272         switch( ucSVCNumber )\r
 273         {\r
 274                 case portSVC_START_SCHEDULER    :       *(portNVIC_SYSPRI1) |= portNVIC_SVC_PRI;\r
 275                                                                                         prvRestoreContextOfFirstTask();\r
 276                                                                                         break;\r
 277 \r
 278                 case portSVC_YIELD                              :       *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 279                                                                                         break;\r
 280 \r
 281                 case portSVC_RAISE_PRIVILEGE    :       __asm volatile\r
 282                                                                                         (\r
 283                                                                                                 "       mrs r1, control         \n" /* Obtain current control value. */\r
 284                                                                                                 "       bic r1, #1                      \n" /* Set privilege bit. */\r
 285                                                                                                 "       msr control, r1         \n" /* Write back new control value. */\r
 286                                                                                                 :::"r1"\r
 287                                                                                         );\r
 288                                                                                         break;\r
 289 \r
 290                 default                                                 :       /* Unknown SVC call. */\r
 291                                                                                         break;\r
 292         }\r
 293 }\r
 294 /*-----------------------------------------------------------*/\r
 295 \r
 296 static void prvRestoreContextOfFirstTask( void )\r
 297 {\r
 298         __asm volatile\r
 299         (\r
 300                 "       ldr r0, =0xE000ED08                             \n" /* Use the NVIC offset register to locate the stack. */\r
 301                 "       ldr r0, [r0]                                    \n"\r
 302                 "       ldr r0, [r0]                                    \n"\r
 303                 "       msr msp, r0                                             \n" /* Set the msp back to the start of the stack. */\r
 304                 "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 305                 "       ldr r1, [r3]                                    \n"\r
 306                 "       ldr r0, [r1]                                    \n" /* The first item in the TCB is the task top of stack. */\r
 307                 "       add r1, r1, #4                                  \n" /* Move onto the second item in the TCB... */\r
 308                 "       ldr r2, =0xe000ed9c                             \n" /* Region Base Address register. */\r
 309                 "       ldmia r1!, {r4-r11}                             \n" /* Read 4 sets of MPU registers. */\r
 310                 "       stmia r2!, {r4-r11}                             \n" /* Write 4 sets of MPU registers. */\r
 311                 "       ldmia r0!, {r3, r4-r11}                 \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 312                 "       msr control, r3                                 \n"\r
 313                 "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 314                 "       mov r0, #0                                              \n"\r
 315                 "       msr     basepri, r0                                     \n"\r
 316                 "       ldr r14, =0xfffffffd                    \n" /* Load exec return code. */\r
 317                 "       bx r14                                                  \n"\r
 318                 "                                                                       \n"\r
 319                 "       .align 2                                                \n"\r
 320                 "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
 321         );\r
 322 }\r
 323 /*-----------------------------------------------------------*/\r
 324 \r
 325 /*\r
 326  * See header file for description.\r
 327  */\r
 328 portBASE_TYPE xPortStartScheduler( void )\r
 329 {\r
 330         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See\r
 331         http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 332         configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\r
 333 \r
 334         /* Make PendSV and SysTick the same priority as the kernel. */\r
 335         *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
 336         *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
 337 \r
 338         /* Configure the regions in the MPU that are common to all tasks. */\r
 339         prvSetupMPU();\r
 340 \r
 341         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 342         here already. */\r
 343         prvSetupTimerInterrupt();\r
 344 \r
 345         /* Initialise the critical nesting count ready for the first task. */\r
 346         uxCriticalNesting = 0;\r
 347 \r
 348         /* Start the first task. */\r
 349         __asm volatile( "       svc %0                  \n"\r
 350                                         :: "i" (portSVC_START_SCHEDULER) );\r
 351 \r
 352         /* Should not get here! */\r
 353         return 0;\r
 354 }\r
 355 /*-----------------------------------------------------------*/\r
 356 \r
 357 void vPortEndScheduler( void )\r
 358 {\r
 359         /* It is unlikely that the CM3 port will require this function as there\r
 360         is nothing to return to.  */\r
 361 }\r
 362 /*-----------------------------------------------------------*/\r
 363 \r
 364 void vPortEnterCritical( void )\r
 365 {\r
 366 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 367 \r
 368         portDISABLE_INTERRUPTS();\r
 369         uxCriticalNesting++;\r
 370 \r
 371         portRESET_PRIVILEGE( xRunningPrivileged );\r
 372 }\r
 373 /*-----------------------------------------------------------*/\r
 374 \r
 375 void vPortExitCritical( void )\r
 376 {\r
 377 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 378 \r
 379         uxCriticalNesting--;\r
 380         if( uxCriticalNesting == 0 )\r
 381         {\r
 382                 portENABLE_INTERRUPTS();\r
 383         }\r
 384         portRESET_PRIVILEGE( xRunningPrivileged );\r
 385 }\r
 386 /*-----------------------------------------------------------*/\r
 387 \r
 388 void xPortPendSVHandler( void )\r
 389 {\r
 390         /* This is a naked function. */\r
 391 \r
 392         __asm volatile\r
 393         (\r
 394                 "       mrs r0, psp                                                     \n"\r
 395                 "                                                                               \n"\r
 396                 "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 397                 "       ldr     r2, [r3]                                                \n"\r
 398                 "                                                                               \n"\r
 399                 "       mrs r1, control                                         \n"\r
 400                 "       stmdb r0!, {r1, r4-r11}                         \n" /* Save the remaining registers. */\r
 401                 "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 402                 "                                                                               \n"\r
 403                 "       stmdb sp!, {r3, r14}                            \n"\r
 404                 "       mov r0, %0                                                      \n"\r
 405                 "       msr basepri, r0                                         \n"\r
 406                 "       bl vTaskSwitchContext                           \n"\r
 407                 "       mov r0, #0                                                      \n"\r
 408                 "       msr basepri, r0                                         \n"\r
 409                 "       ldmia sp!, {r3, r14}                            \n"\r
 410                 "                                                                               \n"     /* Restore the context. */\r
 411                 "       ldr r1, [r3]                                            \n"\r
 412                 "       ldr r0, [r1]                                            \n" /* The first item in the TCB is the task top of stack. */\r
 413                 "       add r1, r1, #4                                          \n" /* Move onto the second item in the TCB... */\r
 414                 "       ldr r2, =0xe000ed9c                                     \n" /* Region Base Address register. */\r
 415                 "       ldmia r1!, {r4-r11}                                     \n" /* Read 4 sets of MPU registers. */\r
 416                 "       stmia r2!, {r4-r11}                                     \n" /* Write 4 sets of MPU registers. */\r
 417                 "       ldmia r0!, {r3, r4-r11}                         \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 418                 "       msr control, r3                                         \n"\r
 419                 "                                                                               \n"\r
 420                 "       msr psp, r0                                                     \n"\r
 421                 "       bx r14                                                          \n"\r
 422                 "                                                                               \n"\r
 423                 "       .align 2                                                        \n"\r
 424                 "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 425                 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 426         );\r
 427 }\r
 428 /*-----------------------------------------------------------*/\r
 429 \r
 430 void xPortSysTickHandler( void )\r
 431 {\r
 432 unsigned long ulDummy;\r
 433 \r
 434         /* If using preemption, also force a context switch. */\r
 435         #if configUSE_PREEMPTION == 1\r
 436                 *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 437         #endif\r
 438 \r
 439         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
 440         {\r
 441                 vTaskIncrementTick();\r
 442         }\r
 443         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
 444 }\r
 445 /*-----------------------------------------------------------*/\r
 446 \r
 447 /*\r
 448  * Setup the systick timer to generate the tick interrupts at the required\r
 449  * frequency.\r
 450  */\r
 451 static void prvSetupTimerInterrupt( void )\r
 452 {\r
 453         /* Configure SysTick to interrupt at the requested rate. */\r
 454         *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 455         *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
 456 }\r
 457 /*-----------------------------------------------------------*/\r
 458 \r
 459 static void prvSetupMPU( void )\r
 460 {\r
 461 extern unsigned long __privileged_functions_end__[];\r
 462 extern unsigned long __FLASH_segment_start__[];\r
 463 extern unsigned long __FLASH_segment_end__[];\r
 464 extern unsigned long __privileged_data_start__[];\r
 465 extern unsigned long __privileged_data_end__[];\r
 466 \r
 467         /* Check the expected MPU is present. */\r
 468         if( *portMPU_TYPE == portEXPECTED_MPU_TYPE_VALUE )\r
 469         {\r
 470                 /* First setup the entire flash for unprivileged read only access. */\r
 471         *portMPU_REGION_BASE_ADDRESS =  ( ( unsigned long ) __FLASH_segment_start__ ) | /* Base address. */\r
 472                                                                                 ( portMPU_REGION_VALID ) |\r
 473                                                                                 ( portUNPRIVILEGED_FLASH_REGION );\r
 474 \r
 475                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_READ_ONLY ) |\r
 476                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 477                                                                                 ( prvGetMPURegionSizeSetting( ( unsigned long ) __FLASH_segment_end__ - ( unsigned long ) __FLASH_segment_start__ ) ) |\r
 478                                                                                 ( portMPU_REGION_ENABLE );\r
 479 \r
 480                 /* Setup the first 16K for privileged only access (even though less\r
 481                 than 10K is actually being used).  This is where the kernel code is\r
 482                 placed. */\r
 483         *portMPU_REGION_BASE_ADDRESS =  ( ( unsigned long ) __FLASH_segment_start__ ) | /* Base address. */\r
 484                                                                                 ( portMPU_REGION_VALID ) |\r
 485                                                                                 ( portPRIVILEGED_FLASH_REGION );\r
 486 \r
 487                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
 488                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 489                                                                                 ( prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_functions_end__ - ( unsigned long ) __FLASH_segment_start__ ) ) |\r
 490                                                                                 ( portMPU_REGION_ENABLE );\r
 491 \r
 492                 /* Setup the privileged data RAM region.  This is where the kernel data\r
 493                 is placed. */\r
 494                 *portMPU_REGION_BASE_ADDRESS =  ( ( unsigned long ) __privileged_data_start__ ) | /* Base address. */\r
 495                                                                                 ( portMPU_REGION_VALID ) |\r
 496                                                                                 ( portPRIVILEGED_RAM_REGION );\r
 497 \r
 498                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 499                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 500                                                                                 prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_data_end__ - ( unsigned long ) __privileged_data_start__ ) |\r
 501                                                                                 ( portMPU_REGION_ENABLE );\r
 502 \r
 503                 /* By default allow everything to access the general peripherals.  The\r
 504                 system peripherals and registers are protected. */\r
 505                 *portMPU_REGION_BASE_ADDRESS =  ( portPERIPHERALS_START_ADDRESS ) |\r
 506                                                                                 ( portMPU_REGION_VALID ) |\r
 507                                                                                 ( portGENERAL_PERIPHERALS_REGION );\r
 508 \r
 509                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
 510                                                                                 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\r
 511                                                                                 ( portMPU_REGION_ENABLE );\r
 512 \r
 513                 /* Enable the memory fault exception. */\r
 514                 *portNVIC_SYS_CTRL_STATE |= portNVIC_MEM_FAULT_ENABLE;\r
 515 \r
 516                 /* Enable the MPU with the background region configured. */\r
 517                 *portMPU_CTRL |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
 518         }\r
 519 }\r
 520 /*-----------------------------------------------------------*/\r
 521 \r
 522 static unsigned long prvGetMPURegionSizeSetting( unsigned long ulActualSizeInBytes )\r
 523 {\r
 524 unsigned long ulRegionSize, ulReturnValue = 4;\r
 525 \r
 526         /* 32 is the smallest region size, 31 is the largest valid value for\r
 527         ulReturnValue. */\r
 528         for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\r
 529         {\r
 530                 if( ulActualSizeInBytes <= ulRegionSize )\r
 531                 {\r
 532                         break;\r
 533                 }\r
 534                 else\r
 535                 {\r
 536                         ulReturnValue++;\r
 537                 }\r
 538         }\r
 539 \r
 540         /* Shift the code by one before returning so it can be written directly\r
 541         into the the correct bit position of the attribute register. */\r
 542         return ( ulReturnValue << 1UL );\r
 543 }\r
 544 /*-----------------------------------------------------------*/\r
 545 \r
 546 static portBASE_TYPE prvRaisePrivilege( void )\r
 547 {\r
 548         __asm volatile\r
 549         (\r
 550                 "       mrs r0, control                                         \n"\r
 551                 "       tst r0, #1                                                      \n" /* Is the task running privileged? */\r
 552                 "       itte ne                                                         \n"\r
 553                 "       movne r0, #0                                            \n" /* CONTROL[0]!=0, return false. */\r
 554                 "       svcne %0                                                        \n" /* Switch to privileged. */\r
 555                 "       moveq r0, #1                                            \n" /* CONTROL[0]==0, return true. */\r
 556                 "       bx lr                                                           \n"\r
 557                 :: "i" (portSVC_RAISE_PRIVILEGE) : "r0"\r
 558         );\r
 559 \r
 560         return 0;\r
 561 }\r
 562 /*-----------------------------------------------------------*/\r
 563 \r
 564 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, portSTACK_TYPE *pxBottomOfStack, unsigned short usStackDepth )\r
 565 {\r
 566 extern unsigned long __SRAM_segment_start__[];\r
 567 extern unsigned long __SRAM_segment_end__[];\r
 568 extern unsigned long __privileged_data_start__[];\r
 569 extern unsigned long __privileged_data_end__[];\r
 570 long lIndex;\r
 571 unsigned long ul;\r
 572 \r
 573         if( xRegions == NULL )\r
 574         {\r
 575                 /* No MPU regions are specified so allow access to all RAM. */\r
 576         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 577                                 ( ( unsigned long ) __SRAM_segment_start__ ) | /* Base address. */\r
 578                                 ( portMPU_REGION_VALID ) |\r
 579                                 ( portSTACK_REGION );\r
 580 \r
 581                 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 582                                 ( portMPU_REGION_READ_WRITE ) |\r
 583                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 584                                 ( prvGetMPURegionSizeSetting( ( unsigned long ) __SRAM_segment_end__ - ( unsigned long ) __SRAM_segment_start__ ) ) |\r
 585                                 ( portMPU_REGION_ENABLE );\r
 586 \r
 587                 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
 588                 just removed the privileged only parameters. */\r
 589                 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =\r
 590                                 ( ( unsigned long ) __privileged_data_start__ ) | /* Base address. */\r
 591                                 ( portMPU_REGION_VALID ) |\r
 592                                 ( portSTACK_REGION + 1 );\r
 593 \r
 594                 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =\r
 595                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 596                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 597                                 prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_data_end__ - ( unsigned long ) __privileged_data_start__ ) |\r
 598                                 ( portMPU_REGION_ENABLE );\r
 599 \r
 600                 /* Invalidate all other regions. */\r
 601                 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 602                 {\r
 603                         xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 604                         xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 605                 }\r
 606         }\r
 607         else\r
 608         {\r
 609                 /* This function is called automatically when the task is created - in\r
 610                 which case the stack region parameters will be valid.  At all other\r
 611                 times the stack parameters will not be valid and it is assumed that the\r
 612                 stack region has already been configured. */\r
 613                 if( usStackDepth > 0 )\r
 614                 {\r
 615                         /* Define the region that allows access to the stack. */\r
 616                         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 617                                         ( ( unsigned long ) pxBottomOfStack ) |\r
 618                                         ( portMPU_REGION_VALID ) |\r
 619                                         ( portSTACK_REGION ); /* Region number. */\r
 620 \r
 621                         xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 622                                         ( portMPU_REGION_READ_WRITE ) | /* Read and write. */\r
 623                                         ( prvGetMPURegionSizeSetting( ( unsigned long ) usStackDepth * ( unsigned long ) sizeof( portSTACK_TYPE ) ) ) |\r
 624                                         ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 625                                         ( portMPU_REGION_ENABLE );\r
 626                 }\r
 627 \r
 628                 lIndex = 0;\r
 629 \r
 630                 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 631                 {\r
 632                         if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\r
 633                         {\r
 634                                 /* Translate the generic region definition contained in\r
 635                                 xRegions into the CM3 specific MPU settings that are then\r
 636                                 stored in xMPUSettings. */\r
 637                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\r
 638                                                 ( ( unsigned long ) xRegions[ lIndex ].pvBaseAddress ) |\r
 639                                                 ( portMPU_REGION_VALID ) |\r
 640                                                 ( portSTACK_REGION + ul ); /* Region number. */\r
 641 \r
 642                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute =\r
 643                                                 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\r
 644                                                 ( xRegions[ lIndex ].ulParameters ) |\r
 645                                                 ( portMPU_REGION_ENABLE );\r
 646                         }\r
 647                         else\r
 648                         {\r
 649                                 /* Invalidate the region. */\r
 650                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 651                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 652                         }\r
 653 \r
 654                         lIndex++;\r
 655                 }\r
 656         }\r
 657 }\r
 658 /*-----------------------------------------------------------*/\r
 659 \r
 660 signed portBASE_TYPE MPU_xTaskGenericCreate( pdTASK_CODE pvTaskCode, const signed char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions )\r
 661 {\r
 662 signed portBASE_TYPE xReturn;\r
 663 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 664 \r
 665         xReturn = xTaskGenericCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask, puxStackBuffer, xRegions );\r
 666         portRESET_PRIVILEGE( xRunningPrivileged );\r
 667         return xReturn;\r
 668 }\r
 669 /*-----------------------------------------------------------*/\r
 670 \r
 671 void MPU_vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const xRegions )\r
 672 {\r
 673 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 674 \r
 675         vTaskAllocateMPURegions( xTask, xRegions );\r
 676         portRESET_PRIVILEGE( xRunningPrivileged );\r
 677 }\r
 678 /*-----------------------------------------------------------*/\r
 679 \r
 680 #if ( INCLUDE_vTaskDelete == 1 )\r
 681         void MPU_vTaskDelete( xTaskHandle pxTaskToDelete )\r
 682         {\r
 683     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 684 \r
 685                 vTaskDelete( pxTaskToDelete );\r
 686         portRESET_PRIVILEGE( xRunningPrivileged );\r
 687         }\r
 688 #endif\r
 689 /*-----------------------------------------------------------*/\r
 690 \r
 691 #if ( INCLUDE_vTaskDelayUntil == 1 )\r
 692         void MPU_vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement )\r
 693         {\r
 694     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 695 \r
 696                 vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );\r
 697         portRESET_PRIVILEGE( xRunningPrivileged );\r
 698         }\r
 699 #endif\r
 700 /*-----------------------------------------------------------*/\r
 701 \r
 702 #if ( INCLUDE_vTaskDelay == 1 )\r
 703         void MPU_vTaskDelay( portTickType xTicksToDelay )\r
 704         {\r
 705     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 706 \r
 707                 vTaskDelay( xTicksToDelay );\r
 708         portRESET_PRIVILEGE( xRunningPrivileged );\r
 709         }\r
 710 #endif\r
 711 /*-----------------------------------------------------------*/\r
 712 \r
 713 #if ( INCLUDE_uxTaskPriorityGet == 1 )\r
 714         unsigned portBASE_TYPE MPU_uxTaskPriorityGet( xTaskHandle pxTask )\r
 715         {\r
 716         unsigned portBASE_TYPE uxReturn;\r
 717     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 718 \r
 719                 uxReturn = uxTaskPriorityGet( pxTask );\r
 720         portRESET_PRIVILEGE( xRunningPrivileged );\r
 721                 return uxReturn;\r
 722         }\r
 723 #endif\r
 724 /*-----------------------------------------------------------*/\r
 725 \r
 726 #if ( INCLUDE_vTaskPrioritySet == 1 )\r
 727         void MPU_vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority )\r
 728         {\r
 729     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 730 \r
 731                 vTaskPrioritySet( pxTask, uxNewPriority );\r
 732         portRESET_PRIVILEGE( xRunningPrivileged );\r
 733         }\r
 734 #endif\r
 735 /*-----------------------------------------------------------*/\r
 736 \r
 737 #if ( INCLUDE_eTaskStateGet == 1 )\r
 738         eTaskState MPU_eTaskStateGet( xTaskHandle pxTask )\r
 739         {\r
 740     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 741         eTaskState eReturn;\r
 742 \r
 743                 eReturn = eTaskStateGet( pxTask );\r
 744         portRESET_PRIVILEGE( xRunningPrivileged );\r
 745                 return eReturn;\r
 746         }\r
 747 #endif\r
 748 /*-----------------------------------------------------------*/\r
 749 \r
 750 #if ( INCLUDE_vTaskSuspend == 1 )\r
 751         void MPU_vTaskSuspend( xTaskHandle pxTaskToSuspend )\r
 752         {\r
 753     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 754 \r
 755                 vTaskSuspend( pxTaskToSuspend );\r
 756         portRESET_PRIVILEGE( xRunningPrivileged );\r
 757         }\r
 758 #endif\r
 759 /*-----------------------------------------------------------*/\r
 760 \r
 761 #if ( INCLUDE_vTaskSuspend == 1 )\r
 762         signed portBASE_TYPE MPU_xTaskIsTaskSuspended( xTaskHandle xTask )\r
 763         {\r
 764         signed portBASE_TYPE xReturn;\r
 765     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 766 \r
 767                 xReturn = xTaskIsTaskSuspended( xTask );\r
 768         portRESET_PRIVILEGE( xRunningPrivileged );\r
 769                 return xReturn;\r
 770         }\r
 771 #endif\r
 772 /*-----------------------------------------------------------*/\r
 773 \r
 774 #if ( INCLUDE_vTaskSuspend == 1 )\r
 775         void MPU_vTaskResume( xTaskHandle pxTaskToResume )\r
 776         {\r
 777     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 778 \r
 779                 vTaskResume( pxTaskToResume );\r
 780         portRESET_PRIVILEGE( xRunningPrivileged );\r
 781         }\r
 782 #endif\r
 783 /*-----------------------------------------------------------*/\r
 784 \r
 785 void MPU_vTaskSuspendAll( void )\r
 786 {\r
 787 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 788 \r
 789         vTaskSuspendAll();\r
 790     portRESET_PRIVILEGE( xRunningPrivileged );\r
 791 }\r
 792 /*-----------------------------------------------------------*/\r
 793 \r
 794 signed portBASE_TYPE MPU_xTaskResumeAll( void )\r
 795 {\r
 796 signed portBASE_TYPE xReturn;\r
 797 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 798 \r
 799         xReturn = xTaskResumeAll();\r
 800     portRESET_PRIVILEGE( xRunningPrivileged );\r
 801     return xReturn;\r
 802 }\r
 803 /*-----------------------------------------------------------*/\r
 804 \r
 805 portTickType MPU_xTaskGetTickCount( void )\r
 806 {\r
 807 portTickType xReturn;\r
 808 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 809 \r
 810         xReturn = xTaskGetTickCount();\r
 811     portRESET_PRIVILEGE( xRunningPrivileged );\r
 812         return xReturn;\r
 813 }\r
 814 /*-----------------------------------------------------------*/\r
 815 \r
 816 unsigned portBASE_TYPE MPU_uxTaskGetNumberOfTasks( void )\r
 817 {\r
 818 unsigned portBASE_TYPE uxReturn;\r
 819 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 820 \r
 821         uxReturn = uxTaskGetNumberOfTasks();\r
 822     portRESET_PRIVILEGE( xRunningPrivileged );\r
 823         return uxReturn;\r
 824 }\r
 825 /*-----------------------------------------------------------*/\r
 826 \r
 827 #if ( configUSE_TRACE_FACILITY == 1 )\r
 828         void MPU_vTaskList( signed char *pcWriteBuffer )\r
 829         {\r
 830         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 831 \r
 832                 vTaskList( pcWriteBuffer );\r
 833                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 834         }\r
 835 #endif\r
 836 /*-----------------------------------------------------------*/\r
 837 \r
 838 #if ( configGENERATE_RUN_TIME_STATS == 1 )\r
 839         void MPU_vTaskGetRunTimeStats( signed char *pcWriteBuffer )\r
 840         {\r
 841     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 842 \r
 843                 vTaskGetRunTimeStats( pcWriteBuffer );\r
 844         portRESET_PRIVILEGE( xRunningPrivileged );\r
 845         }\r
 846 #endif\r
 847 /*-----------------------------------------------------------*/\r
 848 \r
 849 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 850         void MPU_vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxTagValue )\r
 851         {\r
 852     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 853 \r
 854                 vTaskSetApplicationTaskTag( xTask, pxTagValue );\r
 855         portRESET_PRIVILEGE( xRunningPrivileged );\r
 856         }\r
 857 #endif\r
 858 /*-----------------------------------------------------------*/\r
 859 \r
 860 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 861         pdTASK_HOOK_CODE MPU_xTaskGetApplicationTaskTag( xTaskHandle xTask )\r
 862         {\r
 863         pdTASK_HOOK_CODE xReturn;\r
 864     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 865 \r
 866                 xReturn = xTaskGetApplicationTaskTag( xTask );\r
 867         portRESET_PRIVILEGE( xRunningPrivileged );\r
 868                 return xReturn;\r
 869         }\r
 870 #endif\r
 871 /*-----------------------------------------------------------*/\r
 872 \r
 873 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 874         portBASE_TYPE MPU_xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter )\r
 875         {\r
 876         portBASE_TYPE xReturn;\r
 877     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 878 \r
 879                 xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );\r
 880         portRESET_PRIVILEGE( xRunningPrivileged );\r
 881                 return xReturn;\r
 882         }\r
 883 #endif\r
 884 /*-----------------------------------------------------------*/\r
 885 \r
 886 #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )\r
 887         unsigned portBASE_TYPE MPU_uxTaskGetStackHighWaterMark( xTaskHandle xTask )\r
 888         {\r
 889         unsigned portBASE_TYPE uxReturn;\r
 890     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 891 \r
 892                 uxReturn = uxTaskGetStackHighWaterMark( xTask );\r
 893         portRESET_PRIVILEGE( xRunningPrivileged );\r
 894                 return uxReturn;\r
 895         }\r
 896 #endif\r
 897 /*-----------------------------------------------------------*/\r
 898 \r
 899 #if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 )\r
 900         xTaskHandle MPU_xTaskGetCurrentTaskHandle( void )\r
 901         {\r
 902         xTaskHandle xReturn;\r
 903     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 904 \r
 905                 xReturn = xTaskGetCurrentTaskHandle();\r
 906         portRESET_PRIVILEGE( xRunningPrivileged );\r
 907                 return xReturn;\r
 908         }\r
 909 #endif\r
 910 /*-----------------------------------------------------------*/\r
 911 \r
 912 #if ( INCLUDE_xTaskGetSchedulerState == 1 )\r
 913         portBASE_TYPE MPU_xTaskGetSchedulerState( void )\r
 914         {\r
 915         portBASE_TYPE xReturn;\r
 916     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 917 \r
 918                 xReturn = xTaskGetSchedulerState();\r
 919         portRESET_PRIVILEGE( xRunningPrivileged );\r
 920                 return xReturn;\r
 921         }\r
 922 #endif\r
 923 /*-----------------------------------------------------------*/\r
 924 \r
 925 xQueueHandle MPU_xQueueGenericCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize, unsigned char ucQueueType )\r
 926 {\r
 927 xQueueHandle xReturn;\r
 928 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 929 \r
 930         xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );\r
 931         portRESET_PRIVILEGE( xRunningPrivileged );\r
 932         return xReturn;\r
 933 }\r
 934 /*-----------------------------------------------------------*/\r
 935 \r
 936 signed portBASE_TYPE MPU_xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition )\r
 937 {\r
 938 signed portBASE_TYPE xReturn;\r
 939 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 940 \r
 941         xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );\r
 942         portRESET_PRIVILEGE( xRunningPrivileged );\r
 943         return xReturn;\r
 944 }\r
 945 /*-----------------------------------------------------------*/\r
 946 \r
 947 unsigned portBASE_TYPE MPU_uxQueueMessagesWaiting( const xQueueHandle pxQueue )\r
 948 {\r
 949 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 950 unsigned portBASE_TYPE uxReturn;\r
 951 \r
 952         uxReturn = uxQueueMessagesWaiting( pxQueue );\r
 953         portRESET_PRIVILEGE( xRunningPrivileged );\r
 954         return uxReturn;\r
 955 }\r
 956 /*-----------------------------------------------------------*/\r
 957 \r
 958 signed portBASE_TYPE MPU_xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking )\r
 959 {\r
 960 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 961 signed portBASE_TYPE xReturn;\r
 962 \r
 963         xReturn = xQueueGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking );\r
 964         portRESET_PRIVILEGE( xRunningPrivileged );\r
 965         return xReturn;\r
 966 }\r
 967 /*-----------------------------------------------------------*/\r
 968 \r
 969 #if ( configUSE_MUTEXES == 1 )\r
 970         xQueueHandle MPU_xQueueCreateMutex( void )\r
 971         {\r
 972     xQueueHandle xReturn;\r
 973         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 974 \r
 975                 xReturn = xQueueCreateMutex( queueQUEUE_TYPE_MUTEX );\r
 976                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 977                 return xReturn;\r
 978         }\r
 979 #endif\r
 980 /*-----------------------------------------------------------*/\r
 981 \r
 982 #if configUSE_COUNTING_SEMAPHORES == 1\r
 983         xQueueHandle MPU_xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount )\r
 984         {\r
 985     xQueueHandle xReturn;\r
 986         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 987 \r
 988                 xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );\r
 989                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 990                 return xReturn;\r
 991         }\r
 992 #endif\r
 993 /*-----------------------------------------------------------*/\r
 994 \r
 995 #if ( configUSE_MUTEXES == 1 )\r
 996         portBASE_TYPE MPU_xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime )\r
 997         {\r
 998         portBASE_TYPE xReturn;\r
 999         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1000 \r
1001                 xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );\r
1002                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1003                 return xReturn;\r
1004         }\r
1005 #endif\r
1006 /*-----------------------------------------------------------*/\r
1007 \r
1008 #if ( configUSE_MUTEXES == 1 )\r
1009         portBASE_TYPE MPU_xQueueGiveMutexRecursive( xQueueHandle xMutex )\r
1010         {\r
1011         portBASE_TYPE xReturn;\r
1012         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1013 \r
1014                 xReturn = xQueueGiveMutexRecursive( xMutex );\r
1015                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1016                 return xReturn;\r
1017         }\r
1018 #endif\r
1019 /*-----------------------------------------------------------*/\r
1020 \r
1021 #if configUSE_ALTERNATIVE_API == 1\r
1022         signed portBASE_TYPE MPU_xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition )\r
1023         {\r
1024         signed portBASE_TYPE xReturn;\r
1025         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1026 \r
1027                 xReturn =       signed portBASE_TYPE xQueueAltGenericSend( pxQueue, pvItemToQueue, xTicksToWait, xCopyPosition );\r
1028                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1029                 return xReturn;\r
1030         }\r
1031 #endif\r
1032 /*-----------------------------------------------------------*/\r
1033 \r
1034 #if configUSE_ALTERNATIVE_API == 1\r
1035         signed portBASE_TYPE MPU_xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking )\r
1036         {\r
1037     signed portBASE_TYPE xReturn;\r
1038         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1039 \r
1040                 xReturn = xQueueAltGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking );\r
1041                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1042                 return xReturn;\r
1043         }\r
1044 #endif\r
1045 /*-----------------------------------------------------------*/\r
1046 \r
1047 #if configQUEUE_REGISTRY_SIZE > 0\r
1048         void MPU_vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcName )\r
1049         {\r
1050         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1051 \r
1052                 vQueueAddToRegistry( xQueue, pcName );\r
1053 \r
1054                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1055         }\r
1056 #endif\r
1057 /*-----------------------------------------------------------*/\r
1058 \r
1059 void MPU_vQueueDelete( xQueueHandle xQueue )\r
1060 {\r
1061 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1062 \r
1063         vQueueDelete( xQueue );\r
1064 \r
1065         portRESET_PRIVILEGE( xRunningPrivileged );\r
1066 }\r
1067 /*-----------------------------------------------------------*/\r
1068 \r
1069 void *MPU_pvPortMalloc( size_t xSize )\r
1070 {\r
1071 void *pvReturn;\r
1072 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1073 \r
1074         pvReturn = pvPortMalloc( xSize );\r
1075 \r
1076         portRESET_PRIVILEGE( xRunningPrivileged );\r
1077 \r
1078         return pvReturn;\r
1079 }\r
1080 /*-----------------------------------------------------------*/\r
1081 \r
1082 void MPU_vPortFree( void *pv )\r
1083 {\r
1084 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1085 \r
1086         vPortFree( pv );\r
1087 \r
1088         portRESET_PRIVILEGE( xRunningPrivileged );\r
1089 }\r
1090 /*-----------------------------------------------------------*/\r
1091 \r
1092 void MPU_vPortInitialiseBlocks( void )\r
1093 {\r
1094 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1095 \r
1096         vPortInitialiseBlocks();\r
1097 \r
1098         portRESET_PRIVILEGE( xRunningPrivileged );\r
1099 }\r
1100 /*-----------------------------------------------------------*/\r
1101 \r
1102 size_t MPU_xPortGetFreeHeapSize( void )\r
1103 {\r
1104 size_t xReturn;\r
1105 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1106 \r
1107         xReturn = xPortGetFreeHeapSize();\r
1108 \r
1109         portRESET_PRIVILEGE( xRunningPrivileged );\r
1110 \r
1111         return xReturn;\r
1112 }\r
1113 \r