2 FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 distribute a combined work that includes FreeRTOS without being obliged to
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35 provide the source code for proprietary components outside of the FreeRTOS
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38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 details. You should have received a copy of the GNU General Public License
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42 and the FreeRTOS license exception along with FreeRTOS; if not it can be
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43 viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 writing to Real Time Engineers Ltd., contact details for whom are available
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45 on the FreeRTOS WEB site.
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49 ***************************************************************************
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51 * Having a problem? Start by reading the FAQ "My application does *
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52 * not run, what could be wrong?" *
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54 * http://www.FreeRTOS.org/FAQHelp.html *
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56 ***************************************************************************
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59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 license and Real Time Engineers Ltd. contact details.
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62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 fully thread aware and reentrant UDP/IP stack.
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66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 Integrity Systems, who sell the code with commercial support,
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68 indemnification and middleware, under the OpenRTOS brand.
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70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 engineered and independently SIL3 certified version for use in safety and
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72 mission critical applications that require provable dependability.
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75 /*-----------------------------------------------------------
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76 * Implementation of functions defined in portable.h for the ARM CM4F port.
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77 *----------------------------------------------------------*/
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79 /* Scheduler includes. */
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80 #include "FreeRTOS.h"
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84 #error This port can only be used when the project options are configured to enable hardware floating point support.
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87 #ifndef configSYSTICK_CLOCK_HZ
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88 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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91 /* Constants required to manipulate the core. Registers first... */
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92 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
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93 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) )
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94 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) )
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95 #define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )
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96 /* ...then bits in the registers. */
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97 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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98 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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99 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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100 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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101 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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102 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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104 #define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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105 #define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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107 /* Constants required to check the validity of an interrupt prority. */
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108 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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109 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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110 #define portAIRCR_REG ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )
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111 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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113 /* Constants required to manipulate the VFP. */
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114 #define portFPCCR ( ( volatile unsigned long * ) 0xe000ef34 ) /* Floating point context control register. */
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115 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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117 /* Constants required to set up the initial stack. */
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118 #define portINITIAL_XPSR ( 0x01000000 )
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119 #define portINITIAL_EXEC_RETURN ( 0xfffffffd )
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121 /* The systick is a 24-bit counter. */
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122 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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124 /* A fiddle factor to estimate the number of SysTick counts that would have
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125 occurred while the SysTick counter is stopped during tickless idle
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127 #define portMISSED_COUNTS_FACTOR ( 45UL )
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129 /* Each task maintains its own interrupt status in the critical nesting
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131 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;
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134 * Setup the timer to generate the tick interrupts. The implementation in this
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135 * file is weak to allow application writers to change the timer used to
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136 * generate the tick interrupt.
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138 void vPortSetupTimerInterrupt( void );
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141 * Exception handlers.
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143 void xPortPendSVHandler( void ) __attribute__ (( naked ));
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144 void xPortSysTickHandler( void );
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145 void vPortSVCHandler( void ) __attribute__ (( naked ));
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148 * Start first task is a separate function so it can be tested in isolation.
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150 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
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153 * Function to enable the VFP.
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155 static void vPortEnableVFP( void ) __attribute__ (( naked ));
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157 /*-----------------------------------------------------------*/
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160 * The number of SysTick increments that make up one tick period.
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162 #if configUSE_TICKLESS_IDLE == 1
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163 static unsigned long ulTimerCountsForOneTick = 0;
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164 #endif /* configUSE_TICKLESS_IDLE */
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167 * The maximum number of tick periods that can be suppressed is limited by the
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168 * 24 bit resolution of the SysTick timer.
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170 #if configUSE_TICKLESS_IDLE == 1
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171 static unsigned long xMaximumPossibleSuppressedTicks = 0;
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172 #endif /* configUSE_TICKLESS_IDLE */
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175 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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176 * power functionality only.
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178 #if configUSE_TICKLESS_IDLE == 1
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179 static unsigned long ulStoppedTimerCompensation = 0;
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180 #endif /* configUSE_TICKLESS_IDLE */
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183 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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184 * FreeRTOS API functions are not called from interrupts that have been assigned
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185 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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187 #if ( configASSERT_DEFINED == 1 )
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188 static unsigned char ucMaxSysCallPriority = 0;
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189 static const volatile unsigned char * const pcInterruptPriorityRegisters = ( const volatile unsigned char * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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190 #endif /* configASSERT_DEFINED */
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192 /*-----------------------------------------------------------*/
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195 * See header file for description.
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197 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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199 /* Simulate the stack frame as it would be created by a context switch
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202 /* Offset added to account for the way the MCU uses the stack on entry/exit
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203 of interrupts, and to ensure alignment. */
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206 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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208 *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */
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210 *pxTopOfStack = 0; /* LR */
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212 /* Save code space by skipping register initialisation. */
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213 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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214 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
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216 /* A save method is being used that requires each task to maintain its
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217 own exec return value. */
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219 *pxTopOfStack = portINITIAL_EXEC_RETURN;
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221 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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223 return pxTopOfStack;
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225 /*-----------------------------------------------------------*/
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227 void vPortSVCHandler( void )
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230 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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231 " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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232 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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233 " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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234 " msr psp, r0 \n" /* Restore the task stack pointer. */
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236 " msr basepri, r0 \n"
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240 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
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243 /*-----------------------------------------------------------*/
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245 static void prvPortStartFirstTask( void )
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248 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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251 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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252 " cpsie i \n" /* Globally enable interrupts. */
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253 " svc 0 \n" /* System call to start first task. */
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257 /*-----------------------------------------------------------*/
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260 * See header file for description.
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262 portBASE_TYPE xPortStartScheduler( void )
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264 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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265 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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266 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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268 #if( configASSERT_DEFINED == 1 )
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270 volatile unsigned long ulOriginalPriority;
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271 volatile char * const pcFirstUserPriorityRegister = ( volatile char * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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273 /* Determine the maximum priority from which ISR safe FreeRTOS API
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274 functions can be called. ISR safe functions are those that end in
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275 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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276 ensure interrupt entry is as fast and simple as possible.
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278 Save the interrupt priority value that is about to be clobbered. */
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279 ulOriginalPriority = *pcFirstUserPriorityRegister;
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281 /* Write the configMAX_SYSCALL_INTERRUPT_PRIORITY value to an interrupt
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282 priority register. */
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283 *pcFirstUserPriorityRegister = configMAX_SYSCALL_INTERRUPT_PRIORITY;
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285 /* Read back the written priority to obtain its value as seen by the
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286 hardware, which will only implement a subset of the priority bits. */
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287 ucMaxSysCallPriority = *pcFirstUserPriorityRegister;
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289 /* Restore the clobbered interrupt priority register to its original
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291 *pcFirstUserPriorityRegister = ulOriginalPriority;
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293 #endif /* conifgASSERT_DEFINED */
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295 /* Make PendSV and SysTick the lowest priority interrupts. */
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296 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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297 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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299 /* Start the timer that generates the tick ISR. Interrupts are disabled
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301 vPortSetupTimerInterrupt();
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303 /* Initialise the critical nesting count ready for the first task. */
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304 uxCriticalNesting = 0;
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306 /* Ensure the VFP is enabled - it should be anyway. */
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309 /* Lazy save always. */
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310 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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312 /* Start the first task. */
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313 prvPortStartFirstTask();
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315 /* Should not get here! */
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318 /*-----------------------------------------------------------*/
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320 void vPortEndScheduler( void )
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322 /* It is unlikely that the CM4F port will require this function as there
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323 is nothing to return to. */
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325 /*-----------------------------------------------------------*/
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327 void vPortYield( void )
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329 /* Set a PendSV to request a context switch. */
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330 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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332 /* Barriers are normally not required but do ensure the code is completely
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333 within the specified behaviour for the architecture. */
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334 __asm volatile( "dsb" );
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335 __asm volatile( "isb" );
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337 /*-----------------------------------------------------------*/
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339 void vPortEnterCritical( void )
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341 portDISABLE_INTERRUPTS();
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342 uxCriticalNesting++;
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343 __asm volatile( "dsb" );
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344 __asm volatile( "isb" );
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346 /*-----------------------------------------------------------*/
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348 void vPortExitCritical( void )
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350 uxCriticalNesting--;
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351 if( uxCriticalNesting == 0 )
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353 portENABLE_INTERRUPTS();
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356 /*-----------------------------------------------------------*/
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358 __attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )
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362 " mrs r0, basepri \n" \
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364 " msr basepri, r1 \n" \
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366 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1" \
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369 /* This return will not be reached but is necessary to prevent compiler
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373 /*-----------------------------------------------------------*/
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375 __attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )
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379 " msr basepri, r0 \n" \
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384 /* Just to avoid compiler warnings. */
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385 ( void ) ulNewMaskValue;
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387 /*-----------------------------------------------------------*/
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389 void xPortPendSVHandler( void )
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391 /* This is a naked function. */
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397 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
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400 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
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402 " vstmdbeq r0!, {s16-s31} \n"
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404 " stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */
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406 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
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408 " stmdb sp!, {r3, r14} \n"
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410 " msr basepri, r0 \n"
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411 " bl vTaskSwitchContext \n"
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413 " msr basepri, r0 \n"
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414 " ldmia sp!, {r3, r14} \n"
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416 " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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419 " ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */
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421 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
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423 " vldmiaeq r0!, {s16-s31} \n"
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429 "pxCurrentTCBConst: .word pxCurrentTCB \n"
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430 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
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433 /*-----------------------------------------------------------*/
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435 void xPortSysTickHandler( void )
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437 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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438 executes all interrupts must be unmasked. There is therefore no need to
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439 save and then restore the interrupt mask value as its value is already
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441 ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
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443 /* Increment the RTOS tick. */
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444 if( xTaskIncrementTick() != pdFALSE )
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446 /* A context switch is required. Context switching is performed in
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447 the PendSV interrupt. Pend the PendSV interrupt. */
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448 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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451 portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
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453 /*-----------------------------------------------------------*/
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455 #if configUSE_TICKLESS_IDLE == 1
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457 __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )
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459 unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
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460 portTickType xModifiableIdleTime;
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462 /* Make sure the SysTick reload value does not overflow the counter. */
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463 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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465 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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468 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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469 is accounted for as best it can be, but using the tickless mode will
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470 inevitably result in some tiny drift of the time maintained by the
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471 kernel with respect to calendar time. */
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472 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
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474 /* Calculate the reload value required to wait xExpectedIdleTime
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475 tick periods. -1 is used because this code will execute part way
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476 through one of the tick periods. */
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477 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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478 if( ulReloadValue > ulStoppedTimerCompensation )
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480 ulReloadValue -= ulStoppedTimerCompensation;
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483 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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484 method as that will mask interrupts that should exit sleep mode. */
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485 __asm volatile( "cpsid i" );
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487 /* If a context switch is pending or a task is waiting for the scheduler
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488 to be unsuspended then abandon the low power entry. */
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489 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
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491 /* Restart SysTick. */
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492 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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494 /* Re-enable interrupts - see comments above the cpsid instruction()
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496 __asm volatile( "cpsie i" );
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500 /* Set the new reload value. */
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501 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
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503 /* Clear the SysTick count flag and set the count value back to
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505 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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507 /* Restart SysTick. */
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508 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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510 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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511 set its parameter to 0 to indicate that its implementation contains
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512 its own wait for interrupt or wait for event instruction, and so wfi
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513 should not be executed again. However, the original expected idle
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514 time variable must remain unmodified, so a copy is taken. */
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515 xModifiableIdleTime = xExpectedIdleTime;
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516 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
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517 if( xModifiableIdleTime > 0 )
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519 __asm volatile( "dsb" );
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520 __asm volatile( "wfi" );
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521 __asm volatile( "isb" );
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523 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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525 /* Stop SysTick. Again, the time the SysTick is stopped for is
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526 accounted for as best it can be, but using the tickless mode will
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527 inevitably result in some tiny drift of the time maintained by the
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528 kernel with respect to calendar time. */
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529 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
\r
531 /* Re-enable interrupts - see comments above the cpsid instruction()
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533 __asm volatile( "cpsie i" );
\r
535 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
\r
537 /* The tick interrupt has already executed, and the SysTick
\r
538 count reloaded with ulReloadValue. Reset the
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539 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
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541 portNVIC_SYSTICK_LOAD_REG = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
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543 /* The tick interrupt handler will already have pended the tick
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544 processing in the kernel. As the pending tick will be
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545 processed as soon as this function exits, the tick value
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546 maintained by the tick is stepped forward by one less than the
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547 time spent waiting. */
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548 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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552 /* Something other than the tick interrupt ended the sleep.
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553 Work out how long the sleep lasted rounded to complete tick
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554 periods (not the ulReload value which accounted for part
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556 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
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558 /* How many complete tick periods passed while the processor
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560 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
\r
562 /* The reload value is set to whatever fraction of a single tick
\r
564 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
\r
567 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
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568 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
\r
570 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
571 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
\r
573 vTaskStepTick( ulCompleteTickPeriods );
\r
575 /* The counter must start by the time the reload value is reset. */
\r
576 configASSERT( portNVIC_SYSTICK_CURRENT_VALUE_REG );
\r
577 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
581 #endif /* #if configUSE_TICKLESS_IDLE */
\r
582 /*-----------------------------------------------------------*/
\r
585 * Setup the systick timer to generate the tick interrupts at the required
\r
588 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
\r
590 /* Calculate the constants required to configure the tick interrupt. */
\r
591 #if configUSE_TICKLESS_IDLE == 1
\r
593 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
594 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
595 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
597 #endif /* configUSE_TICKLESS_IDLE */
\r
599 /* Configure SysTick to interrupt at the requested rate. */
\r
600 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;
\r
601 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
\r
603 /*-----------------------------------------------------------*/
\r
605 /* This is a naked function. */
\r
606 static void vPortEnableVFP( void )
\r
610 " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
\r
613 " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
\r
618 /*-----------------------------------------------------------*/
\r
620 #if( configASSERT_DEFINED == 1 )
\r
622 void vPortValidateInterruptPriority( void )
\r
624 unsigned long ulCurrentInterrupt;
\r
625 unsigned char ucCurrentPriority;
\r
627 /* Obtain the number of the currently executing interrupt. */
\r
628 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
\r
630 /* Is the interrupt number a user defined interrupt? */
\r
631 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
633 /* Look up the interrupt's priority. */
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634 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
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636 /* The following assertion will fail if a service routine (ISR) for
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637 an interrupt that has been assigned a priority above
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638 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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639 function. ISR safe FreeRTOS API functions must *only* be called
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640 from interrupts that have been assigned a priority at or below
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641 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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643 Numerically low interrupt priority numbers represent logically high
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644 interrupt priorities, therefore the priority of the interrupt must
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645 be set to a value equal to or numerically *higher* than
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646 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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648 Interrupts that use the FreeRTOS API must not be left at their
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649 default priority of zero as that is the highest possible priority,
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650 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
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651 and therefore also guaranteed to be invalid.
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653 FreeRTOS maintains separate thread and ISR API functions to ensure
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654 interrupt entry is as fast and simple as possible.
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656 The following links provide detailed information:
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657 http://www.freertos.org/RTOS-Cortex-M3-M4.html
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658 http://www.freertos.org/FAQHelp.html */
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659 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
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662 /* Priority grouping: The interrupt controller (NVIC) allows the bits
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663 that define each interrupt's priority to be split between bits that
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664 define the interrupt's pre-emption priority bits and bits that define
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665 the interrupt's sub-priority. For simplicity all bits must be defined
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666 to be pre-emption priority bits. The following assertion will fail if
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667 this is not the case (if some bits represent a sub-priority).
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669 If CMSIS libraries are being used then the correct setting can be
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670 achieved by calling NVIC_SetPriorityGrouping( 0 ); before starting the
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672 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) == 0 );
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675 #endif /* configASSERT_DEFINED */
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