2 FreeRTOS V7.5.3 - Copyright (C) 2013 Real Time Engineers Ltd.
\r
5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
7 ***************************************************************************
\r
9 * FreeRTOS provides completely free yet professionally developed, *
\r
10 * robust, strictly quality controlled, supported, and cross *
\r
11 * platform software that has become a de facto standard. *
\r
13 * Help yourself get started quickly and support the FreeRTOS *
\r
14 * project by purchasing a FreeRTOS tutorial book, reference *
\r
15 * manual, or both from: http://www.FreeRTOS.org/Documentation *
\r
19 ***************************************************************************
\r
21 This file is part of the FreeRTOS distribution.
\r
23 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
24 the terms of the GNU General Public License (version 2) as published by the
\r
25 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
\r
27 >>! NOTE: The modification to the GPL is included to allow you to distribute
\r
28 >>! a combined work that includes FreeRTOS without being obliged to provide
\r
29 >>! the source code for proprietary components outside of the FreeRTOS
\r
32 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
33 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
34 FOR A PARTICULAR PURPOSE. Full license text is available from the following
\r
35 link: http://www.freertos.org/a00114.html
\r
39 ***************************************************************************
\r
41 * Having a problem? Start by reading the FAQ "My application does *
\r
42 * not run, what could be wrong?" *
\r
44 * http://www.FreeRTOS.org/FAQHelp.html *
\r
46 ***************************************************************************
\r
48 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
\r
49 license and Real Time Engineers Ltd. contact details.
\r
51 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
52 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
53 compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
55 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
\r
56 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
57 licenses offer ticketed support, indemnification and middleware.
\r
59 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
60 engineered and independently SIL3 certified version for use in safety and
\r
61 mission critical applications that require provable dependability.
\r
66 /*-----------------------------------------------------------
\r
67 * Implementation of functions defined in portable.h for the ARM CM4F port.
\r
68 *----------------------------------------------------------*/
\r
70 /* Scheduler includes. */
\r
71 #include "FreeRTOS.h"
\r
75 #error This port can only be used when the project options are configured to enable hardware floating point support.
\r
78 #ifndef configSYSTICK_CLOCK_HZ
\r
79 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
\r
82 /* Constants required to manipulate the core. Registers first... */
\r
83 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
\r
84 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) )
\r
85 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) )
\r
86 #define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )
\r
87 /* ...then bits in the registers. */
\r
88 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
\r
89 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
\r
90 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
\r
91 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
\r
92 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
\r
93 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
\r
95 #define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
\r
96 #define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
\r
98 /* Constants required to check the validity of an interrupt priority. */
\r
99 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
\r
100 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
\r
101 #define portAIRCR_REG ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )
\r
102 #define portMAX_8_BIT_VALUE ( ( unsigned char ) 0xff )
\r
103 #define portTOP_BIT_OF_BYTE ( ( unsigned char ) 0x80 )
\r
104 #define portMAX_PRIGROUP_BITS ( ( unsigned char ) 7 )
\r
105 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
\r
106 #define portPRIGROUP_SHIFT ( 8UL )
\r
108 /* Constants required to manipulate the VFP. */
\r
109 #define portFPCCR ( ( volatile unsigned long * ) 0xe000ef34 ) /* Floating point context control register. */
\r
110 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
\r
112 /* Constants required to set up the initial stack. */
\r
113 #define portINITIAL_XPSR ( 0x01000000 )
\r
114 #define portINITIAL_EXEC_RETURN ( 0xfffffffd )
\r
116 /* The systick is a 24-bit counter. */
\r
117 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
\r
119 /* A fiddle factor to estimate the number of SysTick counts that would have
\r
120 occurred while the SysTick counter is stopped during tickless idle
\r
122 #define portMISSED_COUNTS_FACTOR ( 45UL )
\r
124 /* Let the user override the pre-loading of the initial LR with the address of
\r
125 prvTaskExitError() in case is messes up unwinding of the stack in the
\r
127 #ifdef configTASK_RETURN_ADDRESS
\r
128 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
\r
130 #define portTASK_RETURN_ADDRESS prvTaskExitError
\r
133 /* Each task maintains its own interrupt status in the critical nesting
\r
135 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;
\r
138 * Setup the timer to generate the tick interrupts. The implementation in this
\r
139 * file is weak to allow application writers to change the timer used to
\r
140 * generate the tick interrupt.
\r
142 void vPortSetupTimerInterrupt( void );
\r
145 * Exception handlers.
\r
147 void xPortPendSVHandler( void ) __attribute__ (( naked ));
\r
148 void xPortSysTickHandler( void );
\r
149 void vPortSVCHandler( void ) __attribute__ (( naked ));
\r
152 * Start first task is a separate function so it can be tested in isolation.
\r
154 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
\r
157 * Function to enable the VFP.
\r
159 static void vPortEnableVFP( void ) __attribute__ (( naked ));
\r
162 * Used to catch tasks that attempt to return from their implementing function.
\r
164 static void prvTaskExitError( void );
\r
166 /*-----------------------------------------------------------*/
\r
169 * The number of SysTick increments that make up one tick period.
\r
171 #if configUSE_TICKLESS_IDLE == 1
\r
172 static unsigned long ulTimerCountsForOneTick = 0;
\r
173 #endif /* configUSE_TICKLESS_IDLE */
\r
176 * The maximum number of tick periods that can be suppressed is limited by the
\r
177 * 24 bit resolution of the SysTick timer.
\r
179 #if configUSE_TICKLESS_IDLE == 1
\r
180 static unsigned long xMaximumPossibleSuppressedTicks = 0;
\r
181 #endif /* configUSE_TICKLESS_IDLE */
\r
184 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
\r
185 * power functionality only.
\r
187 #if configUSE_TICKLESS_IDLE == 1
\r
188 static unsigned long ulStoppedTimerCompensation = 0;
\r
189 #endif /* configUSE_TICKLESS_IDLE */
\r
192 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
\r
193 * FreeRTOS API functions are not called from interrupts that have been assigned
\r
194 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
196 #if ( configASSERT_DEFINED == 1 )
\r
197 static unsigned char ucMaxSysCallPriority = 0;
\r
198 static unsigned long ulMaxPRIGROUPValue = 0;
\r
199 static const volatile unsigned char * const pcInterruptPriorityRegisters = ( const volatile unsigned char * const ) portNVIC_IP_REGISTERS_OFFSET_16;
\r
200 #endif /* configASSERT_DEFINED */
\r
202 /*-----------------------------------------------------------*/
\r
205 * See header file for description.
\r
207 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
\r
209 /* Simulate the stack frame as it would be created by a context switch
\r
212 /* Offset added to account for the way the MCU uses the stack on entry/exit
\r
213 of interrupts, and to ensure alignment. */
\r
216 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
\r
218 *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */
\r
220 *pxTopOfStack = ( portSTACK_TYPE ) portTASK_RETURN_ADDRESS; /* LR */
\r
222 /* Save code space by skipping register initialisation. */
\r
223 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
\r
224 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
\r
226 /* A save method is being used that requires each task to maintain its
\r
227 own exec return value. */
\r
229 *pxTopOfStack = portINITIAL_EXEC_RETURN;
\r
231 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
\r
233 return pxTopOfStack;
\r
235 /*-----------------------------------------------------------*/
\r
237 static void prvTaskExitError( void )
\r
239 /* A function that implements a task must not exit or attempt to return to
\r
240 its caller as there is nothing to return to. If a task wants to exit it
\r
241 should instead call vTaskDelete( NULL ).
\r
243 Artificially force an assert() to be triggered if configASSERT() is
\r
244 defined, then stop here so application writers can catch the error. */
\r
245 configASSERT( uxCriticalNesting == ~0UL );
\r
246 portDISABLE_INTERRUPTS();
\r
249 /*-----------------------------------------------------------*/
\r
251 void vPortSVCHandler( void )
\r
254 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
\r
255 " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
\r
256 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
\r
257 " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
\r
258 " msr psp, r0 \n" /* Restore the task stack pointer. */
\r
260 " msr basepri, r0 \n"
\r
264 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
\r
267 /*-----------------------------------------------------------*/
\r
269 static void prvPortStartFirstTask( void )
\r
272 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
\r
275 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
\r
276 " cpsie i \n" /* Globally enable interrupts. */
\r
277 " svc 0 \n" /* System call to start first task. */
\r
281 /*-----------------------------------------------------------*/
\r
284 * See header file for description.
\r
286 portBASE_TYPE xPortStartScheduler( void )
\r
288 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
\r
289 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
\r
290 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
\r
292 #if( configASSERT_DEFINED == 1 )
\r
294 volatile unsigned long ulOriginalPriority;
\r
295 volatile char * const pcFirstUserPriorityRegister = ( volatile char * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
\r
296 volatile unsigned char ucMaxPriorityValue;
\r
298 /* Determine the maximum priority from which ISR safe FreeRTOS API
\r
299 functions can be called. ISR safe functions are those that end in
\r
300 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
\r
301 ensure interrupt entry is as fast and simple as possible.
\r
303 Save the interrupt priority value that is about to be clobbered. */
\r
304 ulOriginalPriority = *pcFirstUserPriorityRegister;
\r
306 /* Determine the number of priority bits available. First write to all
\r
308 *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
\r
310 /* Read the value back to see how many bits stuck. */
\r
311 ucMaxPriorityValue = *pcFirstUserPriorityRegister;
\r
313 /* Use the same mask on the maximum system call priority. */
\r
314 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
\r
316 /* Calculate the maximum acceptable priority group value for the number
\r
317 of bits read back. */
\r
318 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
\r
319 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
\r
321 ulMaxPRIGROUPValue--;
\r
322 ucMaxPriorityValue <<= ( unsigned char ) 0x01;
\r
325 /* Shift the priority group value back to its position within the AIRCR
\r
327 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
\r
328 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
\r
330 /* Restore the clobbered interrupt priority register to its original
\r
332 *pcFirstUserPriorityRegister = ulOriginalPriority;
\r
334 #endif /* conifgASSERT_DEFINED */
\r
336 /* Make PendSV and SysTick the lowest priority interrupts. */
\r
337 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
\r
338 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
\r
340 /* Start the timer that generates the tick ISR. Interrupts are disabled
\r
342 vPortSetupTimerInterrupt();
\r
344 /* Initialise the critical nesting count ready for the first task. */
\r
345 uxCriticalNesting = 0;
\r
347 /* Ensure the VFP is enabled - it should be anyway. */
\r
350 /* Lazy save always. */
\r
351 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
\r
353 /* Start the first task. */
\r
354 prvPortStartFirstTask();
\r
356 /* Should not get here! */
\r
359 /*-----------------------------------------------------------*/
\r
361 void vPortEndScheduler( void )
\r
363 /* It is unlikely that the CM4F port will require this function as there
\r
364 is nothing to return to. */
\r
366 /*-----------------------------------------------------------*/
\r
368 void vPortYield( void )
\r
370 /* Set a PendSV to request a context switch. */
\r
371 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
\r
373 /* Barriers are normally not required but do ensure the code is completely
\r
374 within the specified behaviour for the architecture. */
\r
375 __asm volatile( "dsb" );
\r
376 __asm volatile( "isb" );
\r
378 /*-----------------------------------------------------------*/
\r
380 void vPortEnterCritical( void )
\r
382 portDISABLE_INTERRUPTS();
\r
383 uxCriticalNesting++;
\r
384 __asm volatile( "dsb" );
\r
385 __asm volatile( "isb" );
\r
387 /*-----------------------------------------------------------*/
\r
389 void vPortExitCritical( void )
\r
391 uxCriticalNesting--;
\r
392 if( uxCriticalNesting == 0 )
\r
394 portENABLE_INTERRUPTS();
\r
397 /*-----------------------------------------------------------*/
\r
399 __attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )
\r
403 " mrs r0, basepri \n" \
\r
405 " msr basepri, r1 \n" \
\r
407 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1" \
\r
410 /* This return will not be reached but is necessary to prevent compiler
\r
414 /*-----------------------------------------------------------*/
\r
416 __attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )
\r
420 " msr basepri, r0 \n" \
\r
425 /* Just to avoid compiler warnings. */
\r
426 ( void ) ulNewMaskValue;
\r
428 /*-----------------------------------------------------------*/
\r
430 void xPortPendSVHandler( void )
\r
432 /* This is a naked function. */
\r
438 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
\r
441 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
\r
443 " vstmdbeq r0!, {s16-s31} \n"
\r
445 " stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */
\r
447 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
\r
449 " stmdb sp!, {r3, r14} \n"
\r
451 " msr basepri, r0 \n"
\r
452 " bl vTaskSwitchContext \n"
\r
454 " msr basepri, r0 \n"
\r
455 " ldmia sp!, {r3, r14} \n"
\r
457 " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
\r
460 " ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */
\r
462 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
\r
464 " vldmiaeq r0!, {s16-s31} \n"
\r
468 #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
\r
469 #if WORKAROUND_PMU_CM001 == 1
\r
478 "pxCurrentTCBConst: .word pxCurrentTCB \n"
\r
479 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
\r
482 /*-----------------------------------------------------------*/
\r
484 void xPortSysTickHandler( void )
\r
486 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
\r
487 executes all interrupts must be unmasked. There is therefore no need to
\r
488 save and then restore the interrupt mask value as its value is already
\r
490 ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
\r
492 /* Increment the RTOS tick. */
\r
493 if( xTaskIncrementTick() != pdFALSE )
\r
495 /* A context switch is required. Context switching is performed in
\r
496 the PendSV interrupt. Pend the PendSV interrupt. */
\r
497 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
\r
500 portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
\r
502 /*-----------------------------------------------------------*/
\r
504 #if configUSE_TICKLESS_IDLE == 1
\r
506 __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )
\r
508 unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
\r
509 portTickType xModifiableIdleTime;
\r
511 /* Make sure the SysTick reload value does not overflow the counter. */
\r
512 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
\r
514 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
\r
517 /* Stop the SysTick momentarily. The time the SysTick is stopped for
\r
518 is accounted for as best it can be, but using the tickless mode will
\r
519 inevitably result in some tiny drift of the time maintained by the
\r
520 kernel with respect to calendar time. */
\r
521 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
\r
523 /* Calculate the reload value required to wait xExpectedIdleTime
\r
524 tick periods. -1 is used because this code will execute part way
\r
525 through one of the tick periods. */
\r
526 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
\r
527 if( ulReloadValue > ulStoppedTimerCompensation )
\r
529 ulReloadValue -= ulStoppedTimerCompensation;
\r
532 /* Enter a critical section but don't use the taskENTER_CRITICAL()
\r
533 method as that will mask interrupts that should exit sleep mode. */
\r
534 __asm volatile( "cpsid i" );
\r
536 /* If a context switch is pending or a task is waiting for the scheduler
\r
537 to be unsuspended then abandon the low power entry. */
\r
538 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
\r
540 /* Restart from whatever is left in the count register to complete
\r
541 this tick period. */
\r
542 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
544 /* Restart SysTick. */
\r
545 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
\r
547 /* Reset the reload register to the value required for normal tick
\r
549 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
551 /* Re-enable interrupts - see comments above the cpsid instruction()
\r
553 __asm volatile( "cpsie i" );
\r
557 /* Set the new reload value. */
\r
558 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
\r
560 /* Clear the SysTick count flag and set the count value back to
\r
562 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
564 /* Restart SysTick. */
\r
565 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
\r
567 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
\r
568 set its parameter to 0 to indicate that its implementation contains
\r
569 its own wait for interrupt or wait for event instruction, and so wfi
\r
570 should not be executed again. However, the original expected idle
\r
571 time variable must remain unmodified, so a copy is taken. */
\r
572 xModifiableIdleTime = xExpectedIdleTime;
\r
573 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
\r
574 if( xModifiableIdleTime > 0 )
\r
576 __asm volatile( "dsb" );
\r
577 __asm volatile( "wfi" );
\r
578 __asm volatile( "isb" );
\r
580 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
\r
582 /* Stop SysTick. Again, the time the SysTick is stopped for is
\r
583 accounted for as best it can be, but using the tickless mode will
\r
584 inevitably result in some tiny drift of the time maintained by the
\r
585 kernel with respect to calendar time. */
\r
586 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
\r
588 /* Re-enable interrupts - see comments above the cpsid instruction()
\r
590 __asm volatile( "cpsie i" );
\r
592 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
\r
594 unsigned long ulCalculatedLoadValue;
\r
596 /* The tick interrupt has already executed, and the SysTick
\r
597 count reloaded with ulReloadValue. Reset the
\r
598 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
\r
600 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
\r
602 /* Don't allow a tiny value, or values that have somehow
\r
603 underflowed because the post sleep hook did something
\r
604 that took too long. */
\r
605 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
607 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
\r
610 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
\r
612 /* The tick interrupt handler will already have pended the tick
\r
613 processing in the kernel. As the pending tick will be
\r
614 processed as soon as this function exits, the tick value
\r
615 maintained by the tick is stepped forward by one less than the
\r
616 time spent waiting. */
\r
617 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
621 /* Something other than the tick interrupt ended the sleep.
\r
622 Work out how long the sleep lasted rounded to complete tick
\r
623 periods (not the ulReload value which accounted for part
\r
625 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
627 /* How many complete tick periods passed while the processor
\r
629 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
\r
631 /* The reload value is set to whatever fraction of a single tick
\r
633 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
\r
636 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
\r
637 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
\r
638 value. The critical section is used to ensure the tick interrupt
\r
639 can only execute once in the case that the reload register is near
\r
641 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
642 portENTER_CRITICAL();
\r
644 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
\r
645 vTaskStepTick( ulCompleteTickPeriods );
\r
646 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
648 portEXIT_CRITICAL();
\r
652 #endif /* #if configUSE_TICKLESS_IDLE */
\r
653 /*-----------------------------------------------------------*/
\r
656 * Setup the systick timer to generate the tick interrupts at the required
\r
659 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
\r
661 /* Calculate the constants required to configure the tick interrupt. */
\r
662 #if configUSE_TICKLESS_IDLE == 1
\r
664 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
665 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
666 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
668 #endif /* configUSE_TICKLESS_IDLE */
\r
670 /* Configure SysTick to interrupt at the requested rate. */
\r
671 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;
\r
672 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
\r
674 /*-----------------------------------------------------------*/
\r
676 /* This is a naked function. */
\r
677 static void vPortEnableVFP( void )
\r
681 " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
\r
684 " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
\r
689 /*-----------------------------------------------------------*/
\r
691 #if( configASSERT_DEFINED == 1 )
\r
693 void vPortValidateInterruptPriority( void )
\r
695 unsigned long ulCurrentInterrupt;
\r
696 unsigned char ucCurrentPriority;
\r
698 /* Obtain the number of the currently executing interrupt. */
\r
699 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
\r
701 /* Is the interrupt number a user defined interrupt? */
\r
702 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
704 /* Look up the interrupt's priority. */
\r
705 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
707 /* The following assertion will fail if a service routine (ISR) for
\r
708 an interrupt that has been assigned a priority above
\r
709 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
710 function. ISR safe FreeRTOS API functions must *only* be called
\r
711 from interrupts that have been assigned a priority at or below
\r
712 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
714 Numerically low interrupt priority numbers represent logically high
\r
715 interrupt priorities, therefore the priority of the interrupt must
\r
716 be set to a value equal to or numerically *higher* than
\r
717 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
719 Interrupts that use the FreeRTOS API must not be left at their
\r
720 default priority of zero as that is the highest possible priority,
\r
721 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
722 and therefore also guaranteed to be invalid.
\r
724 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
725 interrupt entry is as fast and simple as possible.
\r
727 The following links provide detailed information:
\r
728 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
729 http://www.freertos.org/FAQHelp.html */
\r
730 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
733 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
734 that define each interrupt's priority to be split between bits that
\r
735 define the interrupt's pre-emption priority bits and bits that define
\r
736 the interrupt's sub-priority. For simplicity all bits must be defined
\r
737 to be pre-emption priority bits. The following assertion will fail if
\r
738 this is not the case (if some bits represent a sub-priority).
\r
740 If the application only uses CMSIS libraries for interrupt
\r
741 configuration then the correct setting can be achieved on all Cortex-M
\r
742 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
743 scheduler. Note however that some vendor specific peripheral libraries
\r
744 assume a non-zero priority group setting, in which cases using a value
\r
745 of zero will result in unpredicable behaviour. */
\r
746 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
749 #endif /* configASSERT_DEFINED */
\r
projects / freertos / blob