git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c

   1 /*\r
   2  * FreeRTOS Kernel V10.3.0\r
   3  * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software.\r
  14  *\r
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21  *\r
  22  * http://www.FreeRTOS.org\r
  23  * http://aws.amazon.com/freertos\r
  24  *\r
  25  * 1 tab == 4 spaces!\r
  26  */\r
  27 \r
  28 /*-----------------------------------------------------------\r
  29  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  30  *----------------------------------------------------------*/\r
  31 \r
  32 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
  33 all the API functions to use the MPU wrappers.  That should only be done when\r
  34 task.h is included from an application file. */\r
  35 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  36 \r
  37 /* Scheduler includes. */\r
  38 #include "FreeRTOS.h"\r
  39 #include "task.h"\r
  40 \r
  41 #ifndef __VFP_FP__\r
  42         #error This port can only be used when the project options are configured to enable hardware floating point support.\r
  43 #endif\r
  44 \r
  45 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  46 \r
  47 #ifndef configSYSTICK_CLOCK_HZ\r
  48         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  49         /* Ensure the SysTick is clocked at the same frequency as the core. */\r
  50         #define portNVIC_SYSTICK_CLK    ( 1UL << 2UL )\r
  51 #else\r
  52         /* The way the SysTick is clocked is not modified in case it is not the same\r
  53         as the core. */\r
  54         #define portNVIC_SYSTICK_CLK    ( 0 )\r
  55 #endif\r
  56 \r
  57 /* Constants required to access and manipulate the NVIC. */\r
  58 #define portNVIC_SYSTICK_CTRL_REG                               ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
  59 #define portNVIC_SYSTICK_LOAD_REG                               ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
  60 #define portNVIC_SYSTICK_CURRENT_VALUE_REG              ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
  61 #define portNVIC_SYSPRI2_REG                                    ( *     ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
  62 #define portNVIC_SYSPRI1_REG                                    ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )\r
  63 #define portNVIC_SYS_CTRL_STATE_REG                             ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )\r
  64 #define portNVIC_MEM_FAULT_ENABLE                               ( 1UL << 16UL )\r
  65 \r
  66 /* Constants required to access and manipulate the MPU. */\r
  67 #define portMPU_TYPE_REG                                                ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
  68 #define portMPU_REGION_BASE_ADDRESS_REG                 ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )\r
  69 #define portMPU_REGION_ATTRIBUTE_REG                    ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )\r
  70 #define portMPU_CTRL_REG                                                ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
  71 #define portEXPECTED_MPU_TYPE_VALUE                             ( 8UL << 8UL ) /* 8 regions, unified. */\r
  72 #define portMPU_ENABLE                                                  ( 0x01UL )\r
  73 #define portMPU_BACKGROUND_ENABLE                               ( 1UL << 2UL )\r
  74 #define portPRIVILEGED_EXECUTION_START_ADDRESS  ( 0UL )\r
  75 #define portMPU_REGION_VALID                                    ( 0x10UL )\r
  76 #define portMPU_REGION_ENABLE                                   ( 0x01UL )\r
  77 #define portPERIPHERALS_START_ADDRESS                   0x40000000UL\r
  78 #define portPERIPHERALS_END_ADDRESS                             0x5FFFFFFFUL\r
  79 \r
  80 /* Constants required to access and manipulate the SysTick. */\r
  81 #define portNVIC_SYSTICK_INT                                    ( 0x00000002UL )\r
  82 #define portNVIC_SYSTICK_ENABLE                                 ( 0x00000001UL )\r
  83 #define portNVIC_PENDSV_PRI                                             ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
  84 #define portNVIC_SYSTICK_PRI                                    ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
  85 #define portNVIC_SVC_PRI                                                ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )\r
  86 \r
  87 /* Constants required to manipulate the VFP. */\r
  88 #define portFPCCR                                                               ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */\r
  89 #define portASPEN_AND_LSPEN_BITS                                ( 0x3UL << 30UL )\r
  90 \r
  91 /* Constants required to set up the initial stack. */\r
  92 #define portINITIAL_XPSR                                                ( 0x01000000UL )\r
  93 #define portINITIAL_EXC_RETURN                                  ( 0xfffffffdUL )\r
  94 #define portINITIAL_CONTROL_IF_UNPRIVILEGED             ( 0x03 )\r
  95 #define portINITIAL_CONTROL_IF_PRIVILEGED               ( 0x02 )\r
  96 \r
  97 /* Constants required to check the validity of an interrupt priority. */\r
  98 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
  99 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
 100 #define portAIRCR_REG                                           ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
 101 #define portMAX_8_BIT_VALUE                                     ( ( uint8_t ) 0xff )\r
 102 #define portTOP_BIT_OF_BYTE                                     ( ( uint8_t ) 0x80 )\r
 103 #define portMAX_PRIGROUP_BITS                           ( ( uint8_t ) 7 )\r
 104 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
 105 #define portPRIGROUP_SHIFT                                      ( 8UL )\r
 106 \r
 107 /* Offsets in the stack to the parameters when inside the SVC handler. */\r
 108 #define portOFFSET_TO_PC                                                ( 6 )\r
 109 \r
 110 /* For strict compliance with the Cortex-M spec the task start address should\r
 111 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\r
 112 #define portSTART_ADDRESS_MASK                          ( ( StackType_t ) 0xfffffffeUL )\r
 113 \r
 114 /*\r
 115  * Configure a number of standard MPU regions that are used by all tasks.\r
 116  */\r
 117 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
 118 \r
 119 /*\r
 120  * Return the smallest MPU region size that a given number of bytes will fit\r
 121  * into.  The region size is returned as the value that should be programmed\r
 122  * into the region attribute register for that region.\r
 123  */\r
 124 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
 125 \r
 126 /*\r
 127  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 128  * file is weak to allow application writers to change the timer used to\r
 129  * generate the tick interrupt.\r
 130  */\r
 131 void vPortSetupTimerInterrupt( void );\r
 132 \r
 133 /*\r
 134  * Standard FreeRTOS exception handlers.\r
 135  */\r
 136 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 137 void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;\r
 138 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 139 \r
 140 /*\r
 141  * Starts the scheduler by restoring the context of the first task to run.\r
 142  */\r
 143 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
 144 \r
 145 /*\r
 146  * C portion of the SVC handler.  The SVC handler is split between an asm entry\r
 147  * and a C wrapper for simplicity of coding and maintenance.\r
 148  */\r
 149 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
 150 \r
 151 /*\r
 152  * Function to enable the VFP.\r
 153  */\r
 154  static void vPortEnableVFP( void ) __attribute__ (( naked ));\r
 155 \r
 156 /**\r
 157  * @brief Checks whether or not the processor is privileged.\r
 158  *\r
 159  * @return 1 if the processor is already privileged, 0 otherwise.\r
 160  */\r
 161 BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));\r
 162 \r
 163 /**\r
 164  * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
 165  * register.\r
 166  *\r
 167  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
 168  *  Bit[0] = 0 --> The processor is running privileged\r
 169  *  Bit[0] = 1 --> The processor is running unprivileged.\r
 170  */\r
 171 void vResetPrivilege( void ) __attribute__ (( naked ));\r
 172 \r
 173 /**\r
 174  * @brief Calls the port specific code to raise the privilege.\r
 175  *\r
 176  * @return pdFALSE if privilege was raised, pdTRUE otherwise.\r
 177  */\r
 178 extern BaseType_t xPortRaisePrivilege( void );\r
 179 \r
 180 /**\r
 181  * @brief If xRunningPrivileged is not pdTRUE, calls the port specific\r
 182  * code to reset the privilege, otherwise does nothing.\r
 183  */\r
 184 extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );\r
 185 /*-----------------------------------------------------------*/\r
 186 \r
 187 /* Each task maintains its own interrupt status in the critical nesting\r
 188 variable.  Note this is not saved as part of the task context as context\r
 189 switches can only occur when uxCriticalNesting is zero. */\r
 190 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
 191 \r
 192 /*\r
 193  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
 194  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 195  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 196  */\r
 197 #if ( configASSERT_DEFINED == 1 )\r
 198          static uint8_t ucMaxSysCallPriority = 0;\r
 199          static uint32_t ulMaxPRIGROUPValue = 0;\r
 200          static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 201 #endif /* configASSERT_DEFINED */\r
 202 \r
 203 /*-----------------------------------------------------------*/\r
 204 \r
 205 /*\r
 206  * See header file for description.\r
 207  */\r
 208 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )\r
 209 {\r
 210         /* Simulate the stack frame as it would be created by a context switch\r
 211         interrupt. */\r
 212         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 213         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 214         pxTopOfStack--;\r
 215         *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;    /* PC */\r
 216         pxTopOfStack--;\r
 217         *pxTopOfStack = 0;      /* LR */\r
 218         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 219         *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
 220 \r
 221         /* A save method is being used that requires each task to maintain its\r
 222         own exec return value. */\r
 223         pxTopOfStack--;\r
 224         *pxTopOfStack = portINITIAL_EXC_RETURN;\r
 225 \r
 226         pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 227 \r
 228         if( xRunPrivileged == pdTRUE )\r
 229         {\r
 230                 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\r
 231         }\r
 232         else\r
 233         {\r
 234                 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\r
 235         }\r
 236 \r
 237         return pxTopOfStack;\r
 238 }\r
 239 /*-----------------------------------------------------------*/\r
 240 \r
 241 void vPortSVCHandler( void )\r
 242 {\r
 243         /* Assumes psp was in use. */\r
 244         __asm volatile\r
 245         (\r
 246                 #ifndef USE_PROCESS_STACK       /* Code should not be required if a main() is using the process stack. */\r
 247                         "       tst lr, #4                                              \n"\r
 248                         "       ite eq                                                  \n"\r
 249                         "       mrseq r0, msp                                   \n"\r
 250                         "       mrsne r0, psp                                   \n"\r
 251                 #else\r
 252                         "       mrs r0, psp                                             \n"\r
 253                 #endif\r
 254                         "       b %0                                                    \n"\r
 255                         ::"i"(prvSVCHandler):"r0", "memory"\r
 256         );\r
 257 }\r
 258 /*-----------------------------------------------------------*/\r
 259 \r
 260 static void prvSVCHandler(      uint32_t *pulParam )\r
 261 {\r
 262 uint8_t ucSVCNumber;\r
 263 uint32_t ulPC;\r
 264 #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )\r
 265         #if defined( __ARMCC_VERSION )\r
 266                 /* Declaration when these variable are defined in code instead of being\r
 267                 * exported from linker scripts. */\r
 268                 extern uint32_t * __syscalls_flash_start__;\r
 269                 extern uint32_t * __syscalls_flash_end__;\r
 270         #else\r
 271                 /* Declaration when these variable are exported from linker scripts. */\r
 272                 extern uint32_t __syscalls_flash_start__[];\r
 273                 extern uint32_t __syscalls_flash_end__[];\r
 274         #endif /* #if defined( __ARMCC_VERSION ) */\r
 275 #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\r
 276 \r
 277         /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR.  The first\r
 278         argument (r0) is pulParam[ 0 ]. */\r
 279         ulPC = pulParam[ portOFFSET_TO_PC ];\r
 280         ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];\r
 281 \r
 282         switch( ucSVCNumber )\r
 283         {\r
 284                 case portSVC_START_SCHEDULER    :       portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;\r
 285                                                                                         prvRestoreContextOfFirstTask();\r
 286                                                                                         break;\r
 287 \r
 288                 case portSVC_YIELD                              :       portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 289                                                                                         /* Barriers are normally not required\r
 290                                                                                         but do ensure the code is completely\r
 291                                                                                         within the specified behaviour for the\r
 292                                                                                         architecture. */\r
 293                                                                                         __asm volatile( "dsb" ::: "memory" );\r
 294                                                                                         __asm volatile( "isb" );\r
 295 \r
 296                                                                                         break;\r
 297 \r
 298         #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )\r
 299                 case portSVC_RAISE_PRIVILEGE    :       /* Only raise the privilege, if the\r
 300                                                                                          * svc was raised from any of the\r
 301                                                                                          * system calls. */\r
 302                                                                                         if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
 303                                                                                                 ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
 304                                                                                         {\r
 305                                                                                                 __asm volatile\r
 306                                                                                                 (\r
 307                                                                                                         "       mrs r1, control         \n" /* Obtain current control value. */\r
 308                                                                                                         "       bic r1, #1                      \n" /* Set privilege bit. */\r
 309                                                                                                         "       msr control, r1         \n" /* Write back new control value. */\r
 310                                                                                                         ::: "r1", "memory"\r
 311                                                                                                 );\r
 312                                                                                         }\r
 313                                                                                         break;\r
 314         #else\r
 315                 case portSVC_RAISE_PRIVILEGE    :       __asm volatile\r
 316                                                                                         (\r
 317                                                                                                 "       mrs r1, control         \n" /* Obtain current control value. */\r
 318                                                                                                 "       bic r1, #1                      \n" /* Set privilege bit. */\r
 319                                                                                                 "       msr control, r1         \n" /* Write back new control value. */\r
 320                                                                                                 ::: "r1", "memory"\r
 321                                                                                         );\r
 322                                                                                         break;\r
 323         #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */\r
 324 \r
 325                 default                                                 :       /* Unknown SVC call. */\r
 326                                                                                         break;\r
 327         }\r
 328 }\r
 329 /*-----------------------------------------------------------*/\r
 330 \r
 331 static void prvRestoreContextOfFirstTask( void )\r
 332 {\r
 333         __asm volatile\r
 334         (\r
 335                 "       ldr r0, =0xE000ED08                             \n" /* Use the NVIC offset register to locate the stack. */\r
 336                 "       ldr r0, [r0]                                    \n"\r
 337                 "       ldr r0, [r0]                                    \n"\r
 338                 "       msr msp, r0                                             \n" /* Set the msp back to the start of the stack. */\r
 339                 "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 340                 "       ldr r1, [r3]                                    \n"\r
 341                 "       ldr r0, [r1]                                    \n" /* The first item in the TCB is the task top of stack. */\r
 342                 "       add r1, r1, #4                                  \n" /* Move onto the second item in the TCB... */\r
 343                 "                                                                       \n"\r
 344                 "       dmb                                                             \n" /* Complete outstanding transfers before disabling MPU. */\r
 345                 "       ldr r2, =0xe000ed94                             \n" /* MPU_CTRL register. */\r
 346                 "       ldr r3, [r2]                                    \n" /* Read the value of MPU_CTRL. */\r
 347                 "       bic r3, #1                                              \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */\r
 348                 "       str r3, [r2]                                    \n" /* Disable MPU. */\r
 349                 "                                                                       \n"\r
 350                 "       ldr r2, =0xe000ed9c                             \n" /* Region Base Address register. */\r
 351                 "       ldmia r1!, {r4-r11}                             \n" /* Read 4 sets of MPU registers from TCB. */\r
 352                 "       stmia r2!, {r4-r11}                             \n" /* Write 4 sets of MPU registers. */\r
 353                 "                                                                       \n"\r
 354                 "       ldr r2, =0xe000ed94                             \n" /* MPU_CTRL register. */\r
 355                 "       ldr r3, [r2]                                    \n" /* Read the value of MPU_CTRL. */\r
 356                 "       orr r3, #1                                              \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */\r
 357                 "       str r3, [r2]                                    \n" /* Enable MPU. */\r
 358                 "       dsb                                                             \n" /* Force memory writes before continuing. */\r
 359                 "                                                                       \n"\r
 360                 "       ldmia r0!, {r3-r11, r14}                \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 361                 "       msr control, r3                                 \n"\r
 362                 "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 363                 "       mov r0, #0                                              \n"\r
 364                 "       msr     basepri, r0                                     \n"\r
 365                 "       bx r14                                                  \n"\r
 366                 "                                                                       \n"\r
 367                 "       .align 4                                                \n"\r
 368                 "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
 369         );\r
 370 }\r
 371 /*-----------------------------------------------------------*/\r
 372 \r
 373 /*\r
 374  * See header file for description.\r
 375  */\r
 376 BaseType_t xPortStartScheduler( void )\r
 377 {\r
 378         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See\r
 379         http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 380         configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\r
 381 \r
 382         #if( configASSERT_DEFINED == 1 )\r
 383         {\r
 384                 volatile uint32_t ulOriginalPriority;\r
 385                 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 386                 volatile uint8_t ucMaxPriorityValue;\r
 387 \r
 388                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 389                 functions can be called.  ISR safe functions are those that end in\r
 390                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 391                 ensure interrupt entry is as fast and simple as possible.\r
 392 \r
 393                 Save the interrupt priority value that is about to be clobbered. */\r
 394                 ulOriginalPriority = *pucFirstUserPriorityRegister;\r
 395 \r
 396                 /* Determine the number of priority bits available.  First write to all\r
 397                 possible bits. */\r
 398                 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
 399 \r
 400                 /* Read the value back to see how many bits stuck. */\r
 401                 ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
 402 \r
 403                 /* Use the same mask on the maximum system call priority. */\r
 404                 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
 405 \r
 406                 /* Calculate the maximum acceptable priority group value for the number\r
 407                 of bits read back. */\r
 408                 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
 409                 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
 410                 {\r
 411                         ulMaxPRIGROUPValue--;\r
 412                         ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
 413                 }\r
 414 \r
 415                 #ifdef __NVIC_PRIO_BITS\r
 416                 {\r
 417                         /* Check the CMSIS configuration that defines the number of\r
 418                         priority bits matches the number of priority bits actually queried\r
 419                         from the hardware. */\r
 420                         configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\r
 421                 }\r
 422                 #endif\r
 423 \r
 424                 #ifdef configPRIO_BITS\r
 425                 {\r
 426                         /* Check the FreeRTOS configuration that defines the number of\r
 427                         priority bits matches the number of priority bits actually queried\r
 428                         from the hardware. */\r
 429                         configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\r
 430                 }\r
 431                 #endif\r
 432 \r
 433                 /* Shift the priority group value back to its position within the AIRCR\r
 434                 register. */\r
 435                 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
 436                 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
 437 \r
 438                 /* Restore the clobbered interrupt priority register to its original\r
 439                 value. */\r
 440                 *pucFirstUserPriorityRegister = ulOriginalPriority;\r
 441         }\r
 442         #endif /* conifgASSERT_DEFINED */\r
 443 \r
 444         /* Make PendSV and SysTick the same priority as the kernel, and the SVC\r
 445         handler higher priority so it can be used to exit a critical section (where\r
 446         lower priorities are masked). */\r
 447         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 448         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 449 \r
 450         /* Configure the regions in the MPU that are common to all tasks. */\r
 451         prvSetupMPU();\r
 452 \r
 453         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 454         here already. */\r
 455         vPortSetupTimerInterrupt();\r
 456 \r
 457         /* Initialise the critical nesting count ready for the first task. */\r
 458         uxCriticalNesting = 0;\r
 459 \r
 460         /* Ensure the VFP is enabled - it should be anyway. */\r
 461         vPortEnableVFP();\r
 462 \r
 463         /* Lazy save always. */\r
 464         *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
 465 \r
 466         /* Start the first task.  This also clears the bit that indicates the FPU is\r
 467         in use in case the FPU was used before the scheduler was started - which\r
 468         would otherwise result in the unnecessary leaving of space in the SVC stack\r
 469         for lazy saving of FPU registers. */\r
 470         __asm volatile(\r
 471                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 472                                         " ldr r0, [r0]                  \n"\r
 473                                         " ldr r0, [r0]                  \n"\r
 474                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 475                                         " mov r0, #0                    \n" /* Clear the bit that indicates the FPU is in use, see comment above. */\r
 476                                         " msr control, r0               \n"\r
 477                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 478                                         " cpsie f                               \n"\r
 479                                         " dsb                                   \n"\r
 480                                         " isb                                   \n"\r
 481                                         " svc %0                                \n" /* System call to start first task. */\r
 482                                         " nop                                   \n"\r
 483                                         :: "i" (portSVC_START_SCHEDULER) : "memory" );\r
 484 \r
 485         /* Should not get here! */\r
 486         return 0;\r
 487 }\r
 488 /*-----------------------------------------------------------*/\r
 489 \r
 490 void vPortEndScheduler( void )\r
 491 {\r
 492         /* Not implemented in ports where there is nothing to return to.\r
 493         Artificially force an assert. */\r
 494         configASSERT( uxCriticalNesting == 1000UL );\r
 495 }\r
 496 /*-----------------------------------------------------------*/\r
 497 \r
 498 void vPortEnterCritical( void )\r
 499 {\r
 500 BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
 501 \r
 502         portDISABLE_INTERRUPTS();\r
 503         uxCriticalNesting++;\r
 504 \r
 505         vPortResetPrivilege( xRunningPrivileged );\r
 506 }\r
 507 /*-----------------------------------------------------------*/\r
 508 \r
 509 void vPortExitCritical( void )\r
 510 {\r
 511 BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
 512 \r
 513         configASSERT( uxCriticalNesting );\r
 514         uxCriticalNesting--;\r
 515         if( uxCriticalNesting == 0 )\r
 516         {\r
 517                 portENABLE_INTERRUPTS();\r
 518         }\r
 519         vPortResetPrivilege( xRunningPrivileged );\r
 520 }\r
 521 /*-----------------------------------------------------------*/\r
 522 \r
 523 void xPortPendSVHandler( void )\r
 524 {\r
 525         /* This is a naked function. */\r
 526 \r
 527         __asm volatile\r
 528         (\r
 529                 "       mrs r0, psp                                                     \n"\r
 530                 "       isb                                                                     \n"\r
 531                 "                                                                               \n"\r
 532                 "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 533                 "       ldr     r2, [r3]                                                \n"\r
 534                 "                                                                               \n"\r
 535                 "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, push high vfp registers. */\r
 536                 "       it eq                                                           \n"\r
 537                 "       vstmdbeq r0!, {s16-s31}                         \n"\r
 538                 "                                                                               \n"\r
 539                 "       mrs r1, control                                         \n"\r
 540                 "       stmdb r0!, {r1, r4-r11, r14}            \n" /* Save the remaining registers. */\r
 541                 "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 542                 "                                                                               \n"\r
 543                 "       stmdb sp!, {r0, r3}                                     \n"\r
 544                 "       mov r0, %0                                                      \n"\r
 545                 "       msr basepri, r0                                         \n"\r
 546                 "       dsb                                                                     \n"\r
 547                 "       isb                                                                     \n"\r
 548                 "       bl vTaskSwitchContext                           \n"\r
 549                 "       mov r0, #0                                                      \n"\r
 550                 "       msr basepri, r0                                         \n"\r
 551                 "       ldmia sp!, {r0, r3}                                     \n"\r
 552                 "                                                                               \n" /* Restore the context. */\r
 553                 "       ldr r1, [r3]                                            \n"\r
 554                 "       ldr r0, [r1]                                            \n" /* The first item in the TCB is the task top of stack. */\r
 555                 "       add r1, r1, #4                                          \n" /* Move onto the second item in the TCB... */\r
 556                 "                                                                               \n"\r
 557                 "       dmb                                                                     \n" /* Complete outstanding transfers before disabling MPU. */\r
 558                 "       ldr r2, =0xe000ed94                                     \n" /* MPU_CTRL register. */\r
 559                 "       ldr r3, [r2]                                            \n" /* Read the value of MPU_CTRL. */\r
 560                 "       bic r3, #1                                                      \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */\r
 561                 "       str r3, [r2]                                            \n" /* Disable MPU. */\r
 562                 "                                                                               \n"\r
 563                 "       ldr r2, =0xe000ed9c                                     \n" /* Region Base Address register. */\r
 564                 "       ldmia r1!, {r4-r11}                                     \n" /* Read 4 sets of MPU registers from TCB. */\r
 565                 "       stmia r2!, {r4-r11}                                     \n" /* Write 4 sets of MPU registers. */\r
 566                 "                                                                               \n"\r
 567                 "       ldr r2, =0xe000ed94                                     \n" /* MPU_CTRL register. */\r
 568                 "       ldr r3, [r2]                                            \n" /* Read the value of MPU_CTRL. */\r
 569                 "       orr r3, #1                                                      \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */\r
 570                 "       str r3, [r2]                                            \n" /* Enable MPU. */\r
 571                 "       dsb                                                                     \n" /* Force memory writes before continuing. */\r
 572                 "                                                                               \n"\r
 573                 "       ldmia r0!, {r3-r11, r14}                        \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 574                 "       msr control, r3                                         \n"\r
 575                 "                                                                               \n"\r
 576                 "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\r
 577                 "       it eq                                                           \n"\r
 578                 "       vldmiaeq r0!, {s16-s31}                         \n"\r
 579                 "                                                                               \n"\r
 580                 "       msr psp, r0                                                     \n"\r
 581                 "       bx r14                                                          \n"\r
 582                 "                                                                               \n"\r
 583                 "       .align 4                                                        \n"\r
 584                 "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 585                 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 586         );\r
 587 }\r
 588 /*-----------------------------------------------------------*/\r
 589 \r
 590 void xPortSysTickHandler( void )\r
 591 {\r
 592 uint32_t ulDummy;\r
 593 \r
 594         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
 595         {\r
 596                 /* Increment the RTOS tick. */\r
 597                 if( xTaskIncrementTick() != pdFALSE )\r
 598                 {\r
 599                         /* Pend a context switch. */\r
 600                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 601                 }\r
 602         }\r
 603         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
 604 }\r
 605 /*-----------------------------------------------------------*/\r
 606 \r
 607 /*\r
 608  * Setup the systick timer to generate the tick interrupts at the required\r
 609  * frequency.\r
 610  */\r
 611 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 612 {\r
 613         /* Stop and clear the SysTick. */\r
 614         portNVIC_SYSTICK_CTRL_REG = 0UL;\r
 615         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 616 \r
 617         /* Configure SysTick to interrupt at the requested rate. */\r
 618         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 619         portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );\r
 620 }\r
 621 /*-----------------------------------------------------------*/\r
 622 \r
 623 /* This is a naked function. */\r
 624 static void vPortEnableVFP( void )\r
 625 {\r
 626         __asm volatile\r
 627         (\r
 628                 "       ldr.w r0, =0xE000ED88           \n" /* The FPU enable bits are in the CPACR. */\r
 629                 "       ldr r1, [r0]                            \n"\r
 630                 "                                                               \n"\r
 631                 "       orr r1, r1, #( 0xf << 20 )      \n" /* Enable CP10 and CP11 coprocessors, then save back. */\r
 632                 "       str r1, [r0]                            \n"\r
 633                 "       bx r14                                          "\r
 634         );\r
 635 }\r
 636 /*-----------------------------------------------------------*/\r
 637 \r
 638 static void prvSetupMPU( void )\r
 639 {\r
 640 #if defined( __ARMCC_VERSION )\r
 641         /* Declaration when these variable are defined in code instead of being\r
 642          * exported from linker scripts. */\r
 643         extern uint32_t * __privileged_functions_end__;\r
 644         extern uint32_t * __FLASH_segment_start__;\r
 645         extern uint32_t * __FLASH_segment_end__;\r
 646         extern uint32_t * __privileged_data_start__;\r
 647         extern uint32_t * __privileged_data_end__;\r
 648 #else\r
 649         /* Declaration when these variable are exported from linker scripts. */\r
 650         extern uint32_t __privileged_functions_end__[];\r
 651         extern uint32_t __FLASH_segment_start__[];\r
 652         extern uint32_t __FLASH_segment_end__[];\r
 653         extern uint32_t __privileged_data_start__[];\r
 654         extern uint32_t __privileged_data_end__[];\r
 655 #endif\r
 656         /* Check the expected MPU is present. */\r
 657         if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
 658         {\r
 659                 /* First setup the entire flash for unprivileged read only access. */\r
 660                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 661                                                                                         ( portMPU_REGION_VALID ) |\r
 662                                                                                         ( portUNPRIVILEGED_FLASH_REGION );\r
 663 \r
 664                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_ONLY ) |\r
 665                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 666                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 667                                                                                 ( portMPU_REGION_ENABLE );\r
 668 \r
 669                 /* Setup the first nK for privileged only access (even though less\r
 670                 than 10K is actually being used).  This is where the kernel code is\r
 671                 placed. */\r
 672                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 673                                                                                         ( portMPU_REGION_VALID ) |\r
 674                                                                                         ( portPRIVILEGED_FLASH_REGION );\r
 675 \r
 676                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
 677                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 678                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 679                                                                                 ( portMPU_REGION_ENABLE );\r
 680 \r
 681                 /* Setup the privileged data RAM region.  This is where the kernel data\r
 682                 is placed. */\r
 683                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 684                                                                                         ( portMPU_REGION_VALID ) |\r
 685                                                                                         ( portPRIVILEGED_RAM_REGION );\r
 686 \r
 687                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 688                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 689                                                                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 690                                                                                 ( portMPU_REGION_ENABLE );\r
 691 \r
 692                 /* By default allow everything to access the general peripherals.  The\r
 693                 system peripherals and registers are protected. */\r
 694                 portMPU_REGION_BASE_ADDRESS_REG =       ( portPERIPHERALS_START_ADDRESS ) |\r
 695                                                                                         ( portMPU_REGION_VALID ) |\r
 696                                                                                         ( portGENERAL_PERIPHERALS_REGION );\r
 697 \r
 698                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
 699                                                                                 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\r
 700                                                                                 ( portMPU_REGION_ENABLE );\r
 701 \r
 702                 /* Enable the memory fault exception. */\r
 703                 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;\r
 704 \r
 705                 /* Enable the MPU with the background region configured. */\r
 706                 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
 707         }\r
 708 }\r
 709 /*-----------------------------------------------------------*/\r
 710 \r
 711 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )\r
 712 {\r
 713 uint32_t ulRegionSize, ulReturnValue = 4;\r
 714 \r
 715         /* 32 is the smallest region size, 31 is the largest valid value for\r
 716         ulReturnValue. */\r
 717         for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\r
 718         {\r
 719                 if( ulActualSizeInBytes <= ulRegionSize )\r
 720                 {\r
 721                         break;\r
 722                 }\r
 723                 else\r
 724                 {\r
 725                         ulReturnValue++;\r
 726                 }\r
 727         }\r
 728 \r
 729         /* Shift the code by one before returning so it can be written directly\r
 730         into the the correct bit position of the attribute register. */\r
 731         return ( ulReturnValue << 1UL );\r
 732 }\r
 733 /*-----------------------------------------------------------*/\r
 734 \r
 735 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
 736 {\r
 737         __asm volatile\r
 738         (\r
 739         "       mrs r0, control                                                 \n" /* r0 = CONTROL. */\r
 740         "       tst r0, #1                                                              \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
 741         "       ite ne                                                                  \n"\r
 742         "       movne r0, #0                                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
 743         "       moveq r0, #1                                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
 744         "       bx lr                                                                   \n" /* Return. */\r
 745         "                                                                                       \n"\r
 746         "       .align 4                                                                \n"\r
 747         ::: "r0", "memory"\r
 748         );\r
 749 }\r
 750 /*-----------------------------------------------------------*/\r
 751 \r
 752 void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
 753 {\r
 754         __asm volatile\r
 755         (\r
 756         "       mrs r0, control                                                 \n" /* r0 = CONTROL. */\r
 757         "       orr r0, #1                                                              \n" /* r0 = r0 | 1. */\r
 758         "       msr control, r0                                                 \n" /* CONTROL = r0. */\r
 759         "       bx lr                                                                   \n" /* Return to the caller. */\r
 760         :::"r0", "memory"\r
 761         );\r
 762 }\r
 763 /*-----------------------------------------------------------*/\r
 764 \r
 765 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
 766 {\r
 767 #if defined( __ARMCC_VERSION )\r
 768         /* Declaration when these variable are defined in code instead of being\r
 769          * exported from linker scripts. */\r
 770         extern uint32_t * __SRAM_segment_start__;\r
 771         extern uint32_t * __SRAM_segment_end__;\r
 772         extern uint32_t * __privileged_data_start__;\r
 773         extern uint32_t * __privileged_data_end__;\r
 774 #else\r
 775         /* Declaration when these variable are exported from linker scripts. */\r
 776         extern uint32_t __SRAM_segment_start__[];\r
 777         extern uint32_t __SRAM_segment_end__[];\r
 778         extern uint32_t __privileged_data_start__[];\r
 779         extern uint32_t __privileged_data_end__[];\r
 780 #endif\r
 781 \r
 782 int32_t lIndex;\r
 783 uint32_t ul;\r
 784 \r
 785         if( xRegions == NULL )\r
 786         {\r
 787                 /* No MPU regions are specified so allow access to all RAM. */\r
 788                 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 789                                 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */\r
 790                                 ( portMPU_REGION_VALID ) |\r
 791                                 ( portSTACK_REGION );\r
 792 \r
 793                 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 794                                 ( portMPU_REGION_READ_WRITE ) |\r
 795                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 796                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |\r
 797                                 ( portMPU_REGION_ENABLE );\r
 798 \r
 799                 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
 800                 just removed the privileged only parameters. */\r
 801                 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =\r
 802                                 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 803                                 ( portMPU_REGION_VALID ) |\r
 804                                 ( portSTACK_REGION + 1 );\r
 805 \r
 806                 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =\r
 807                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 808                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 809                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 810                                 ( portMPU_REGION_ENABLE );\r
 811 \r
 812                 /* Invalidate all other regions. */\r
 813                 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 814                 {\r
 815                         xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 816                         xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 817                 }\r
 818         }\r
 819         else\r
 820         {\r
 821                 /* This function is called automatically when the task is created - in\r
 822                 which case the stack region parameters will be valid.  At all other\r
 823                 times the stack parameters will not be valid and it is assumed that the\r
 824                 stack region has already been configured. */\r
 825                 if( ulStackDepth > 0 )\r
 826                 {\r
 827                         /* Define the region that allows access to the stack. */\r
 828                         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 829                                         ( ( uint32_t ) pxBottomOfStack ) |\r
 830                                         ( portMPU_REGION_VALID ) |\r
 831                                         ( portSTACK_REGION ); /* Region number. */\r
 832 \r
 833                         xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 834                                         ( portMPU_REGION_READ_WRITE ) | /* Read and write. */\r
 835                                         ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |\r
 836                                         ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 837                                         ( portMPU_REGION_ENABLE );\r
 838                 }\r
 839 \r
 840                 lIndex = 0;\r
 841 \r
 842                 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 843                 {\r
 844                         if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\r
 845                         {\r
 846                                 /* Translate the generic region definition contained in\r
 847                                 xRegions into the CM3 specific MPU settings that are then\r
 848                                 stored in xMPUSettings. */\r
 849                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\r
 850                                                 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |\r
 851                                                 ( portMPU_REGION_VALID ) |\r
 852                                                 ( portSTACK_REGION + ul ); /* Region number. */\r
 853 \r
 854                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute =\r
 855                                                 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\r
 856                                                 ( xRegions[ lIndex ].ulParameters ) |\r
 857                                                 ( portMPU_REGION_ENABLE );\r
 858                         }\r
 859                         else\r
 860                         {\r
 861                                 /* Invalidate the region. */\r
 862                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 863                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 864                         }\r
 865 \r
 866                         lIndex++;\r
 867                 }\r
 868         }\r
 869 }\r
 870 /*-----------------------------------------------------------*/\r
 871 \r
 872 #if( configASSERT_DEFINED == 1 )\r
 873 \r
 874         void vPortValidateInterruptPriority( void )\r
 875         {\r
 876         uint32_t ulCurrentInterrupt;\r
 877         uint8_t ucCurrentPriority;\r
 878 \r
 879                 /* Obtain the number of the currently executing interrupt. */\r
 880                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
 881 \r
 882                 /* Is the interrupt number a user defined interrupt? */\r
 883                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 884                 {\r
 885                         /* Look up the interrupt's priority. */\r
 886                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 887 \r
 888                         /* The following assertion will fail if a service routine (ISR) for\r
 889                         an interrupt that has been assigned a priority above\r
 890                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 891                         function.  ISR safe FreeRTOS API functions must *only* be called\r
 892                         from interrupts that have been assigned a priority at or below\r
 893                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 894 \r
 895                         Numerically low interrupt priority numbers represent logically high\r
 896                         interrupt priorities, therefore the priority of the interrupt must\r
 897                         be set to a value equal to or numerically *higher* than\r
 898                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 899 \r
 900                         Interrupts that use the FreeRTOS API must not be left at their\r
 901                         default priority of     zero as that is the highest possible priority,\r
 902                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
 903                         and     therefore also guaranteed to be invalid.\r
 904 \r
 905                         FreeRTOS maintains separate thread and ISR API functions to ensure\r
 906                         interrupt entry is as fast and simple as possible.\r
 907 \r
 908                         The following links provide detailed information:\r
 909                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 910                         http://www.freertos.org/FAQHelp.html */\r
 911                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 912                 }\r
 913 \r
 914                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits\r
 915                 that define each interrupt's priority to be split between bits that\r
 916                 define the interrupt's pre-emption priority bits and bits that define\r
 917                 the interrupt's sub-priority.  For simplicity all bits must be defined\r
 918                 to be pre-emption priority bits.  The following assertion will fail if\r
 919                 this is not the case (if some bits represent a sub-priority).\r
 920 \r
 921                 If the application only uses CMSIS libraries for interrupt\r
 922                 configuration then the correct setting can be achieved on all Cortex-M\r
 923                 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
 924                 scheduler.  Note however that some vendor specific peripheral libraries\r
 925                 assume a non-zero priority group setting, in which cases using a value\r
 926                 of zero will result in unpredicable behaviour. */\r
 927                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
 928         }\r
 929 \r
 930 #endif /* configASSERT_DEFINED */\r
 931 /*-----------------------------------------------------------*/\r
 932 \r
 933 \r