2 * FreeRTOS Kernel V10.2.1
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /*-----------------------------------------------------------
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29 * Implementation of functions defined in portable.h for the ARM CM3 port.
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30 *----------------------------------------------------------*/
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32 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
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33 all the API functions to use the MPU wrappers. That should only be done when
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34 task.h is included from an application file. */
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35 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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37 /* Scheduler includes. */
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38 #include "FreeRTOS.h"
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42 #error This port can only be used when the project options are configured to enable hardware floating point support.
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45 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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47 #ifndef configSYSTICK_CLOCK_HZ
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48 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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49 /* Ensure the SysTick is clocked at the same frequency as the core. */
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50 #define portNVIC_SYSTICK_CLK ( 1UL << 2UL )
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52 /* The way the SysTick is clocked is not modified in case it is not the same
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54 #define portNVIC_SYSTICK_CLK ( 0 )
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57 /* Constants required to access and manipulate the NVIC. */
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58 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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59 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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60 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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61 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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62 #define portNVIC_SYSPRI1_REG ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
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63 #define portNVIC_SYS_CTRL_STATE_REG ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
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64 #define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
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66 /* Constants required to access and manipulate the MPU. */
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67 #define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
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68 #define portMPU_REGION_BASE_ADDRESS_REG ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
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69 #define portMPU_REGION_ATTRIBUTE_REG ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
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70 #define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
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71 #define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
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72 #define portMPU_ENABLE ( 0x01UL )
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73 #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
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74 #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
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75 #define portMPU_REGION_VALID ( 0x10UL )
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76 #define portMPU_REGION_ENABLE ( 0x01UL )
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77 #define portPERIPHERALS_START_ADDRESS 0x40000000UL
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78 #define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
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80 /* Constants required to access and manipulate the SysTick. */
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81 #define portNVIC_SYSTICK_INT ( 0x00000002UL )
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82 #define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
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83 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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84 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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85 #define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
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87 /* Constants required to manipulate the VFP. */
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88 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
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89 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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91 /* Constants required to set up the initial stack. */
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92 #define portINITIAL_XPSR ( 0x01000000UL )
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93 #define portINITIAL_EXC_RETURN ( 0xfffffffdUL )
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94 #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
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95 #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
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97 /* Constants required to check the validity of an interrupt priority. */
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98 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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99 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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100 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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101 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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102 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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103 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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104 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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105 #define portPRIGROUP_SHIFT ( 8UL )
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107 /* Offsets in the stack to the parameters when inside the SVC handler. */
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108 #define portOFFSET_TO_PC ( 6 )
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110 /* For strict compliance with the Cortex-M spec the task start address should
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111 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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112 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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115 * Configure a number of standard MPU regions that are used by all tasks.
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117 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
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120 * Return the smallest MPU region size that a given number of bytes will fit
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121 * into. The region size is returned as the value that should be programmed
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122 * into the region attribute register for that region.
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124 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
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127 * Setup the timer to generate the tick interrupts. The implementation in this
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128 * file is weak to allow application writers to change the timer used to
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129 * generate the tick interrupt.
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131 void vPortSetupTimerInterrupt( void );
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134 * Standard FreeRTOS exception handlers.
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136 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
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137 void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
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138 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
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141 * Starts the scheduler by restoring the context of the first task to run.
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143 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
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146 * C portion of the SVC handler. The SVC handler is split between an asm entry
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147 * and a C wrapper for simplicity of coding and maintenance.
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149 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;
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152 * Function to enable the VFP.
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154 static void vPortEnableVFP( void ) __attribute__ (( naked ));
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157 * @brief Checks whether or not the processor is privileged.
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159 * @return 1 if the processor is already privileged, 0 otherwise.
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161 BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
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164 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
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167 * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
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168 * Bit[0] = 0 --> The processor is running privileged
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169 * Bit[0] = 1 --> The processor is running unprivileged.
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171 void vResetPrivilege( void ) __attribute__ (( naked ));
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174 * @brief Calls the port specific code to raise the privilege.
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176 * @return pdFALSE if privilege was raised, pdTRUE otherwise.
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178 extern BaseType_t xPortRaisePrivilege( void );
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181 * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
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182 * code to reset the privilege, otherwise does nothing.
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184 extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
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185 /*-----------------------------------------------------------*/
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187 /* Each task maintains its own interrupt status in the critical nesting
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188 variable. Note this is not saved as part of the task context as context
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189 switches can only occur when uxCriticalNesting is zero. */
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190 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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193 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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194 * FreeRTOS API functions are not called from interrupts that have been assigned
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195 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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197 #if ( configASSERT_DEFINED == 1 )
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198 static uint8_t ucMaxSysCallPriority = 0;
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199 static uint32_t ulMaxPRIGROUPValue = 0;
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200 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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201 #endif /* configASSERT_DEFINED */
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203 /*-----------------------------------------------------------*/
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206 * See header file for description.
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208 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
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210 /* Simulate the stack frame as it would be created by a context switch
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212 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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213 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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215 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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217 *pxTopOfStack = 0; /* LR */
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218 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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219 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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221 /* A save method is being used that requires each task to maintain its
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222 own exec return value. */
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224 *pxTopOfStack = portINITIAL_EXC_RETURN;
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226 pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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228 if( xRunPrivileged == pdTRUE )
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230 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
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234 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
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237 return pxTopOfStack;
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239 /*-----------------------------------------------------------*/
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241 void vPortSVCHandler( void )
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243 /* Assumes psp was in use. */
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246 #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
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249 " mrseq r0, msp \n"
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250 " mrsne r0, psp \n"
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255 ::"i"(prvSVCHandler):"r0", "memory"
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258 /*-----------------------------------------------------------*/
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260 static void prvSVCHandler( uint32_t *pulParam )
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262 uint8_t ucSVCNumber;
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264 #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
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265 #if defined( __ARMCC_VERSION )
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266 /* Declaration when these variable are defined in code instead of being
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267 * exported from linker scripts. */
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268 extern uint32_t * __syscalls_flash_start__;
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269 extern uint32_t * __syscalls_flash_end__;
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271 /* Declaration when these variable are exported from linker scripts. */
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272 extern uint32_t __syscalls_flash_start__[];
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273 extern uint32_t __syscalls_flash_end__[];
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274 #endif /* #if defined( __ARMCC_VERSION ) */
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275 #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
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277 /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
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278 argument (r0) is pulParam[ 0 ]. */
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279 ulPC = pulParam[ portOFFSET_TO_PC ];
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280 ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
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282 switch( ucSVCNumber )
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284 case portSVC_START_SCHEDULER : portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
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285 prvRestoreContextOfFirstTask();
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288 case portSVC_YIELD : portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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289 /* Barriers are normally not required
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290 but do ensure the code is completely
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291 within the specified behaviour for the
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293 __asm volatile( "dsb" ::: "memory" );
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294 __asm volatile( "isb" );
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298 #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
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299 case portSVC_RAISE_PRIVILEGE : /* Only raise the privilege, if the
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300 * svc was raised from any of the
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302 if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
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303 ulPC <= ( uint32_t ) __syscalls_flash_end__ )
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307 " mrs r1, control \n" /* Obtain current control value. */
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308 " bic r1, #1 \n" /* Set privilege bit. */
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309 " msr control, r1 \n" /* Write back new control value. */
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315 case portSVC_RAISE_PRIVILEGE : __asm volatile
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317 " mrs r1, control \n" /* Obtain current control value. */
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318 " bic r1, #1 \n" /* Set privilege bit. */
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319 " msr control, r1 \n" /* Write back new control value. */
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323 #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
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325 default : /* Unknown SVC call. */
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329 /*-----------------------------------------------------------*/
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331 static void prvRestoreContextOfFirstTask( void )
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335 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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338 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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339 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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341 " ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */
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342 " add r1, r1, #4 \n" /* Move onto the second item in the TCB... */
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344 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
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345 " ldr r2, =0xe000ed94 \n" /* MPU_CTRL register. */
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346 " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */
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347 " bic r3, #1 \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
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348 " str r3, [r2] \n" /* Disable MPU. */
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350 " ldr r2, =0xe000ed9c \n" /* Region Base Address register. */
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351 " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers from TCB. */
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352 " stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */
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354 " ldr r2, =0xe000ed94 \n" /* MPU_CTRL register. */
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355 " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */
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356 " orr r3, #1 \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
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357 " str r3, [r2] \n" /* Enable MPU. */
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358 " dsb \n" /* Force memory writes before continuing. */
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360 " ldmia r0!, {r3-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry. */
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361 " msr control, r3 \n"
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362 " msr psp, r0 \n" /* Restore the task stack pointer. */
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364 " msr basepri, r0 \n"
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368 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
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371 /*-----------------------------------------------------------*/
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374 * See header file for description.
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376 BaseType_t xPortStartScheduler( void )
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378 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
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379 http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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380 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
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382 #if( configASSERT_DEFINED == 1 )
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384 volatile uint32_t ulOriginalPriority;
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385 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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386 volatile uint8_t ucMaxPriorityValue;
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388 /* Determine the maximum priority from which ISR safe FreeRTOS API
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389 functions can be called. ISR safe functions are those that end in
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390 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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391 ensure interrupt entry is as fast and simple as possible.
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393 Save the interrupt priority value that is about to be clobbered. */
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394 ulOriginalPriority = *pucFirstUserPriorityRegister;
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396 /* Determine the number of priority bits available. First write to all
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398 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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400 /* Read the value back to see how many bits stuck. */
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401 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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403 /* Use the same mask on the maximum system call priority. */
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404 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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406 /* Calculate the maximum acceptable priority group value for the number
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407 of bits read back. */
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408 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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409 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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411 ulMaxPRIGROUPValue--;
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412 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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415 #ifdef __NVIC_PRIO_BITS
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417 /* Check the CMSIS configuration that defines the number of
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418 priority bits matches the number of priority bits actually queried
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419 from the hardware. */
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420 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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424 #ifdef configPRIO_BITS
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426 /* Check the FreeRTOS configuration that defines the number of
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427 priority bits matches the number of priority bits actually queried
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428 from the hardware. */
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429 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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433 /* Shift the priority group value back to its position within the AIRCR
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435 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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436 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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438 /* Restore the clobbered interrupt priority register to its original
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440 *pucFirstUserPriorityRegister = ulOriginalPriority;
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442 #endif /* conifgASSERT_DEFINED */
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444 /* Make PendSV and SysTick the same priority as the kernel, and the SVC
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445 handler higher priority so it can be used to exit a critical section (where
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446 lower priorities are masked). */
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447 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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448 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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450 /* Configure the regions in the MPU that are common to all tasks. */
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453 /* Start the timer that generates the tick ISR. Interrupts are disabled
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455 vPortSetupTimerInterrupt();
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457 /* Initialise the critical nesting count ready for the first task. */
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458 uxCriticalNesting = 0;
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460 /* Ensure the VFP is enabled - it should be anyway. */
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463 /* Lazy save always. */
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464 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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466 /* Start the first task. This also clears the bit that indicates the FPU is
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467 in use in case the FPU was used before the scheduler was started - which
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468 would otherwise result in the unnecessary leaving of space in the SVC stack
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469 for lazy saving of FPU registers. */
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471 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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474 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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475 " mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */
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476 " msr control, r0 \n"
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477 " cpsie i \n" /* Globally enable interrupts. */
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481 " svc %0 \n" /* System call to start first task. */
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483 :: "i" (portSVC_START_SCHEDULER) : "memory" );
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485 /* Should not get here! */
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488 /*-----------------------------------------------------------*/
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490 void vPortEndScheduler( void )
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492 /* Not implemented in ports where there is nothing to return to.
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493 Artificially force an assert. */
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494 configASSERT( uxCriticalNesting == 1000UL );
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496 /*-----------------------------------------------------------*/
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498 void vPortEnterCritical( void )
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500 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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502 portDISABLE_INTERRUPTS();
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503 uxCriticalNesting++;
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505 vPortResetPrivilege( xRunningPrivileged );
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507 /*-----------------------------------------------------------*/
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509 void vPortExitCritical( void )
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511 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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513 configASSERT( uxCriticalNesting );
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514 uxCriticalNesting--;
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515 if( uxCriticalNesting == 0 )
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517 portENABLE_INTERRUPTS();
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519 vPortResetPrivilege( xRunningPrivileged );
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521 /*-----------------------------------------------------------*/
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523 void xPortPendSVHandler( void )
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525 /* This is a naked function. */
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532 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
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535 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
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537 " vstmdbeq r0!, {s16-s31} \n"
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539 " mrs r1, control \n"
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540 " stmdb r0!, {r1, r4-r11, r14} \n" /* Save the remaining registers. */
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541 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
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543 " stmdb sp!, {r0, r3} \n"
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545 " msr basepri, r0 \n"
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548 " bl vTaskSwitchContext \n"
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550 " msr basepri, r0 \n"
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551 " ldmia sp!, {r0, r3} \n"
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552 " \n" /* Restore the context. */
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554 " ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */
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555 " add r1, r1, #4 \n" /* Move onto the second item in the TCB... */
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557 " dmb \n" /* Complete outstanding transfers before disabling MPU. */
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558 " ldr r2, =0xe000ed94 \n" /* MPU_CTRL register. */
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559 " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */
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560 " bic r3, #1 \n" /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
\r
561 " str r3, [r2] \n" /* Disable MPU. */
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563 " ldr r2, =0xe000ed9c \n" /* Region Base Address register. */
\r
564 " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers from TCB. */
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565 " stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */
\r
567 " ldr r2, =0xe000ed94 \n" /* MPU_CTRL register. */
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568 " ldr r3, [r2] \n" /* Read the value of MPU_CTRL. */
\r
569 " orr r3, #1 \n" /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
\r
570 " str r3, [r2] \n" /* Enable MPU. */
\r
571 " dsb \n" /* Force memory writes before continuing. */
\r
573 " ldmia r0!, {r3-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry. */
\r
574 " msr control, r3 \n"
\r
576 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
\r
578 " vldmiaeq r0!, {s16-s31} \n"
\r
584 "pxCurrentTCBConst: .word pxCurrentTCB \n"
\r
585 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
\r
588 /*-----------------------------------------------------------*/
\r
590 void xPortSysTickHandler( void )
\r
594 ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
\r
596 /* Increment the RTOS tick. */
\r
597 if( xTaskIncrementTick() != pdFALSE )
\r
599 /* Pend a context switch. */
\r
600 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
\r
603 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
\r
605 /*-----------------------------------------------------------*/
\r
608 * Setup the systick timer to generate the tick interrupts at the required
\r
611 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
\r
613 /* Stop and clear the SysTick. */
\r
614 portNVIC_SYSTICK_CTRL_REG = 0UL;
\r
615 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
617 /* Configure SysTick to interrupt at the requested rate. */
\r
618 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
\r
619 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
\r
621 /*-----------------------------------------------------------*/
\r
623 /* This is a naked function. */
\r
624 static void vPortEnableVFP( void )
\r
628 " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
\r
631 " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
\r
636 /*-----------------------------------------------------------*/
\r
638 static void prvSetupMPU( void )
\r
640 #if defined( __ARMCC_VERSION )
\r
641 /* Declaration when these variable are defined in code instead of being
\r
642 * exported from linker scripts. */
\r
643 extern uint32_t * __privileged_functions_end__;
\r
644 extern uint32_t * __FLASH_segment_start__;
\r
645 extern uint32_t * __FLASH_segment_end__;
\r
646 extern uint32_t * __privileged_data_start__;
\r
647 extern uint32_t * __privileged_data_end__;
\r
649 /* Declaration when these variable are exported from linker scripts. */
\r
650 extern uint32_t __privileged_functions_end__[];
\r
651 extern uint32_t __FLASH_segment_start__[];
\r
652 extern uint32_t __FLASH_segment_end__[];
\r
653 extern uint32_t __privileged_data_start__[];
\r
654 extern uint32_t __privileged_data_end__[];
\r
656 /* Check the expected MPU is present. */
\r
657 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
\r
659 /* First setup the entire flash for unprivileged read only access. */
\r
660 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
\r
661 ( portMPU_REGION_VALID ) |
\r
662 ( portUNPRIVILEGED_FLASH_REGION );
\r
664 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
\r
665 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
666 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
\r
667 ( portMPU_REGION_ENABLE );
\r
669 /* Setup the first nK for privileged only access (even though less
\r
670 than 10K is actually being used). This is where the kernel code is
\r
672 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
\r
673 ( portMPU_REGION_VALID ) |
\r
674 ( portPRIVILEGED_FLASH_REGION );
\r
676 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
\r
677 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
678 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
\r
679 ( portMPU_REGION_ENABLE );
\r
681 /* Setup the privileged data RAM region. This is where the kernel data
\r
683 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
684 ( portMPU_REGION_VALID ) |
\r
685 ( portPRIVILEGED_RAM_REGION );
\r
687 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
688 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
689 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
690 ( portMPU_REGION_ENABLE );
\r
692 /* By default allow everything to access the general peripherals. The
\r
693 system peripherals and registers are protected. */
\r
694 portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
\r
695 ( portMPU_REGION_VALID ) |
\r
696 ( portGENERAL_PERIPHERALS_REGION );
\r
698 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
\r
699 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
\r
700 ( portMPU_REGION_ENABLE );
\r
702 /* Enable the memory fault exception. */
\r
703 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
\r
705 /* Enable the MPU with the background region configured. */
\r
706 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
\r
709 /*-----------------------------------------------------------*/
\r
711 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
\r
713 uint32_t ulRegionSize, ulReturnValue = 4;
\r
715 /* 32 is the smallest region size, 31 is the largest valid value for
\r
717 for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
\r
719 if( ulActualSizeInBytes <= ulRegionSize )
\r
729 /* Shift the code by one before returning so it can be written directly
\r
730 into the the correct bit position of the attribute register. */
\r
731 return ( ulReturnValue << 1UL );
\r
733 /*-----------------------------------------------------------*/
\r
735 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
\r
739 " mrs r0, control \n" /* r0 = CONTROL. */
\r
740 " tst r0, #1 \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
\r
742 " movne r0, #0 \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
\r
743 " moveq r0, #1 \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
\r
744 " bx lr \n" /* Return. */
\r
750 /*-----------------------------------------------------------*/
\r
752 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
\r
756 " mrs r0, control \n" /* r0 = CONTROL. */
\r
757 " orr r0, #1 \n" /* r0 = r0 | 1. */
\r
758 " msr control, r0 \n" /* CONTROL = r0. */
\r
759 " bx lr \n" /* Return to the caller. */
\r
763 /*-----------------------------------------------------------*/
\r
765 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
\r
767 #if defined( __ARMCC_VERSION )
\r
768 /* Declaration when these variable are defined in code instead of being
\r
769 * exported from linker scripts. */
\r
770 extern uint32_t * __SRAM_segment_start__;
\r
771 extern uint32_t * __SRAM_segment_end__;
\r
772 extern uint32_t * __privileged_data_start__;
\r
773 extern uint32_t * __privileged_data_end__;
\r
775 /* Declaration when these variable are exported from linker scripts. */
\r
776 extern uint32_t __SRAM_segment_start__[];
\r
777 extern uint32_t __SRAM_segment_end__[];
\r
778 extern uint32_t __privileged_data_start__[];
\r
779 extern uint32_t __privileged_data_end__[];
\r
785 if( xRegions == NULL )
\r
787 /* No MPU regions are specified so allow access to all RAM. */
\r
788 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
789 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
\r
790 ( portMPU_REGION_VALID ) |
\r
791 ( portSTACK_REGION );
\r
793 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
794 ( portMPU_REGION_READ_WRITE ) |
\r
795 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
796 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
\r
797 ( portMPU_REGION_ENABLE );
\r
799 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
\r
800 just removed the privileged only parameters. */
\r
801 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
\r
802 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
803 ( portMPU_REGION_VALID ) |
\r
804 ( portSTACK_REGION + 1 );
\r
806 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
\r
807 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
808 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
809 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
810 ( portMPU_REGION_ENABLE );
\r
812 /* Invalidate all other regions. */
\r
813 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
815 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
816 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
821 /* This function is called automatically when the task is created - in
\r
822 which case the stack region parameters will be valid. At all other
\r
823 times the stack parameters will not be valid and it is assumed that the
\r
824 stack region has already been configured. */
\r
825 if( ulStackDepth > 0 )
\r
827 /* Define the region that allows access to the stack. */
\r
828 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
829 ( ( uint32_t ) pxBottomOfStack ) |
\r
830 ( portMPU_REGION_VALID ) |
\r
831 ( portSTACK_REGION ); /* Region number. */
\r
833 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
834 ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
\r
835 ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
\r
836 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
837 ( portMPU_REGION_ENABLE );
\r
842 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
844 if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
\r
846 /* Translate the generic region definition contained in
\r
847 xRegions into the CM3 specific MPU settings that are then
\r
848 stored in xMPUSettings. */
\r
849 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
\r
850 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
\r
851 ( portMPU_REGION_VALID ) |
\r
852 ( portSTACK_REGION + ul ); /* Region number. */
\r
854 xMPUSettings->xRegion[ ul ].ulRegionAttribute =
\r
855 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
\r
856 ( xRegions[ lIndex ].ulParameters ) |
\r
857 ( portMPU_REGION_ENABLE );
\r
861 /* Invalidate the region. */
\r
862 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
863 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
870 /*-----------------------------------------------------------*/
\r
872 #if( configASSERT_DEFINED == 1 )
\r
874 void vPortValidateInterruptPriority( void )
\r
876 uint32_t ulCurrentInterrupt;
\r
877 uint8_t ucCurrentPriority;
\r
879 /* Obtain the number of the currently executing interrupt. */
\r
880 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
\r
882 /* Is the interrupt number a user defined interrupt? */
\r
883 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
885 /* Look up the interrupt's priority. */
\r
886 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
888 /* The following assertion will fail if a service routine (ISR) for
\r
889 an interrupt that has been assigned a priority above
\r
890 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
891 function. ISR safe FreeRTOS API functions must *only* be called
\r
892 from interrupts that have been assigned a priority at or below
\r
893 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
895 Numerically low interrupt priority numbers represent logically high
\r
896 interrupt priorities, therefore the priority of the interrupt must
\r
897 be set to a value equal to or numerically *higher* than
\r
898 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
900 Interrupts that use the FreeRTOS API must not be left at their
\r
901 default priority of zero as that is the highest possible priority,
\r
902 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
903 and therefore also guaranteed to be invalid.
\r
905 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
906 interrupt entry is as fast and simple as possible.
\r
908 The following links provide detailed information:
\r
909 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
910 http://www.freertos.org/FAQHelp.html */
\r
911 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
914 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
915 that define each interrupt's priority to be split between bits that
\r
916 define the interrupt's pre-emption priority bits and bits that define
\r
917 the interrupt's sub-priority. For simplicity all bits must be defined
\r
918 to be pre-emption priority bits. The following assertion will fail if
\r
919 this is not the case (if some bits represent a sub-priority).
\r
921 If the application only uses CMSIS libraries for interrupt
\r
922 configuration then the correct setting can be achieved on all Cortex-M
\r
923 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
924 scheduler. Note however that some vendor specific peripheral libraries
\r
925 assume a non-zero priority group setting, in which cases using a value
\r
926 of zero will result in unpredicable behaviour. */
\r
927 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
930 #endif /* configASSERT_DEFINED */
\r
931 /*-----------------------------------------------------------*/
\r