2 * FreeRTOS Kernel V10.0.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software. If you wish to use our Amazon
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14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23 * http://www.FreeRTOS.org
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24 * http://aws.amazon.com/freertos
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26 * 1 tab == 4 spaces!
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29 /*-----------------------------------------------------------
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30 * Implementation of functions defined in portable.h for the ARM CM3 port.
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31 *----------------------------------------------------------*/
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33 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
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34 all the API functions to use the MPU wrappers. That should only be done when
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35 task.h is included from an application file. */
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36 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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38 /* Scheduler includes. */
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39 #include "FreeRTOS.h"
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43 #error This port can only be used when the project options are configured to enable hardware floating point support.
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46 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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48 #ifndef configSYSTICK_CLOCK_HZ
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49 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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50 /* Ensure the SysTick is clocked at the same frequency as the core. */
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51 #define portNVIC_SYSTICK_CLK ( 1UL << 2UL )
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53 /* The way the SysTick is clocked is not modified in case it is not the same
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55 #define portNVIC_SYSTICK_CLK ( 0 )
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58 /* Constants required to access and manipulate the NVIC. */
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59 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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60 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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61 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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62 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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63 #define portNVIC_SYSPRI1_REG ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
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64 #define portNVIC_SYS_CTRL_STATE_REG ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
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65 #define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
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67 /* Constants required to access and manipulate the MPU. */
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68 #define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
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69 #define portMPU_REGION_BASE_ADDRESS_REG ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
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70 #define portMPU_REGION_ATTRIBUTE_REG ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
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71 #define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
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72 #define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
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73 #define portMPU_ENABLE ( 0x01UL )
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74 #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
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75 #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
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76 #define portMPU_REGION_VALID ( 0x10UL )
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77 #define portMPU_REGION_ENABLE ( 0x01UL )
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78 #define portPERIPHERALS_START_ADDRESS 0x40000000UL
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79 #define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
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81 /* Constants required to access and manipulate the SysTick. */
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82 #define portNVIC_SYSTICK_INT ( 0x00000002UL )
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83 #define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
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84 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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85 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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86 #define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
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88 /* Constants required to manipulate the VFP. */
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89 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
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90 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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92 /* Constants required to set up the initial stack. */
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93 #define portINITIAL_XPSR ( 0x01000000UL )
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94 #define portINITIAL_EXC_RETURN ( 0xfffffffdUL )
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95 #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
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96 #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
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98 /* Constants required to check the validity of an interrupt priority. */
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99 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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100 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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101 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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102 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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103 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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104 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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105 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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106 #define portPRIGROUP_SHIFT ( 8UL )
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108 /* Offsets in the stack to the parameters when inside the SVC handler. */
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109 #define portOFFSET_TO_PC ( 6 )
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111 /* For strict compliance with the Cortex-M spec the task start address should
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112 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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113 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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116 * Configure a number of standard MPU regions that are used by all tasks.
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118 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
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121 * Return the smallest MPU region size that a given number of bytes will fit
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122 * into. The region size is returned as the value that should be programmed
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123 * into the region attribute register for that region.
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125 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
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128 * Checks to see if being called from the context of an unprivileged task, and
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129 * if so raises the privilege level and returns false - otherwise does nothing
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130 * other than return true.
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132 BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));
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135 * Setup the timer to generate the tick interrupts. The implementation in this
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136 * file is weak to allow application writers to change the timer used to
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137 * generate the tick interrupt.
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139 void vPortSetupTimerInterrupt( void );
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142 * Standard FreeRTOS exception handlers.
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144 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
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145 void xPortSysTickHandler( void ) __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;
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146 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
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149 * Starts the scheduler by restoring the context of the first task to run.
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151 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
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154 * C portion of the SVC handler. The SVC handler is split between an asm entry
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155 * and a C wrapper for simplicity of coding and maintenance.
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157 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;
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160 * Function to enable the VFP.
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162 static void vPortEnableVFP( void ) __attribute__ (( naked ));
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164 /*-----------------------------------------------------------*/
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166 /* Each task maintains its own interrupt status in the critical nesting
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167 variable. Note this is not saved as part of the task context as context
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168 switches can only occur when uxCriticalNesting is zero. */
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169 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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172 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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173 * FreeRTOS API functions are not called from interrupts that have been assigned
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174 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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176 #if ( configASSERT_DEFINED == 1 )
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177 static uint8_t ucMaxSysCallPriority = 0;
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178 static uint32_t ulMaxPRIGROUPValue = 0;
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179 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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180 #endif /* configASSERT_DEFINED */
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182 /*-----------------------------------------------------------*/
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185 * See header file for description.
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187 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
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189 /* Simulate the stack frame as it would be created by a context switch
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191 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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192 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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194 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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196 *pxTopOfStack = 0; /* LR */
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197 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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198 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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200 /* A save method is being used that requires each task to maintain its
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201 own exec return value. */
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203 *pxTopOfStack = portINITIAL_EXC_RETURN;
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205 pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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207 if( xRunPrivileged == pdTRUE )
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209 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
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213 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
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216 return pxTopOfStack;
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218 /*-----------------------------------------------------------*/
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220 void vPortSVCHandler( void )
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222 /* Assumes psp was in use. */
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225 #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
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228 " mrseq r0, msp \n"
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229 " mrsne r0, psp \n"
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234 ::"i"(prvSVCHandler):"r0", "memory"
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237 /*-----------------------------------------------------------*/
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239 static void prvSVCHandler( uint32_t *pulParam )
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241 uint8_t ucSVCNumber;
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243 /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
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244 xPSR. The first argument (r0) is pulParam[ 0 ]. */
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245 ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
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246 switch( ucSVCNumber )
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248 case portSVC_START_SCHEDULER : portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
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249 prvRestoreContextOfFirstTask();
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252 case portSVC_YIELD : portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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253 /* Barriers are normally not required
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254 but do ensure the code is completely
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255 within the specified behaviour for the
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257 __asm volatile( "dsb" ::: "memory" );
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258 __asm volatile( "isb" );
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262 case portSVC_RAISE_PRIVILEGE : __asm volatile
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264 " mrs r1, control \n" /* Obtain current control value. */
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265 " bic r1, #1 \n" /* Set privilege bit. */
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266 " msr control, r1 \n" /* Write back new control value. */
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271 default : /* Unknown SVC call. */
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275 /*-----------------------------------------------------------*/
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277 static void prvRestoreContextOfFirstTask( void )
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281 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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284 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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285 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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287 " ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */
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288 " add r1, r1, #4 \n" /* Move onto the second item in the TCB... */
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289 " ldr r2, =0xe000ed9c \n" /* Region Base Address register. */
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290 " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */
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291 " stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */
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292 " ldmia r0!, {r3-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry. */
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293 " msr control, r3 \n"
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294 " msr psp, r0 \n" /* Restore the task stack pointer. */
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296 " msr basepri, r0 \n"
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300 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
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303 /*-----------------------------------------------------------*/
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306 * See header file for description.
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308 BaseType_t xPortStartScheduler( void )
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310 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
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311 http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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312 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
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314 #if( configASSERT_DEFINED == 1 )
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316 volatile uint32_t ulOriginalPriority;
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317 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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318 volatile uint8_t ucMaxPriorityValue;
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320 /* Determine the maximum priority from which ISR safe FreeRTOS API
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321 functions can be called. ISR safe functions are those that end in
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322 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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323 ensure interrupt entry is as fast and simple as possible.
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325 Save the interrupt priority value that is about to be clobbered. */
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326 ulOriginalPriority = *pucFirstUserPriorityRegister;
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328 /* Determine the number of priority bits available. First write to all
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330 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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332 /* Read the value back to see how many bits stuck. */
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333 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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335 /* Use the same mask on the maximum system call priority. */
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336 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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338 /* Calculate the maximum acceptable priority group value for the number
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339 of bits read back. */
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340 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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341 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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343 ulMaxPRIGROUPValue--;
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344 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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347 #ifdef __NVIC_PRIO_BITS
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349 /* Check the CMSIS configuration that defines the number of
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350 priority bits matches the number of priority bits actually queried
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351 from the hardware. */
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352 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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356 #ifdef configPRIO_BITS
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358 /* Check the FreeRTOS configuration that defines the number of
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359 priority bits matches the number of priority bits actually queried
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360 from the hardware. */
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361 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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365 /* Shift the priority group value back to its position within the AIRCR
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367 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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368 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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370 /* Restore the clobbered interrupt priority register to its original
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372 *pucFirstUserPriorityRegister = ulOriginalPriority;
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374 #endif /* conifgASSERT_DEFINED */
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376 /* Make PendSV and SysTick the same priority as the kernel, and the SVC
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377 handler higher priority so it can be used to exit a critical section (where
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378 lower priorities are masked). */
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379 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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380 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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382 /* Configure the regions in the MPU that are common to all tasks. */
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385 /* Start the timer that generates the tick ISR. Interrupts are disabled
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387 vPortSetupTimerInterrupt();
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389 /* Initialise the critical nesting count ready for the first task. */
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390 uxCriticalNesting = 0;
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392 /* Ensure the VFP is enabled - it should be anyway. */
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395 /* Lazy save always. */
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396 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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398 /* Start the first task. This also clears the bit that indicates the FPU is
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399 in use in case the FPU was used before the scheduler was started - which
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400 would otherwise result in the unnecessary leaving of space in the SVC stack
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401 for lazy saving of FPU registers. */
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403 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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406 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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407 " mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */
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408 " msr control, r0 \n"
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409 " cpsie i \n" /* Globally enable interrupts. */
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413 " svc %0 \n" /* System call to start first task. */
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415 :: "i" (portSVC_START_SCHEDULER) : "memory" );
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417 /* Should not get here! */
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420 /*-----------------------------------------------------------*/
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422 void vPortEndScheduler( void )
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424 /* Not implemented in ports where there is nothing to return to.
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425 Artificially force an assert. */
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426 configASSERT( uxCriticalNesting == 1000UL );
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428 /*-----------------------------------------------------------*/
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430 void vPortEnterCritical( void )
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432 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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434 portDISABLE_INTERRUPTS();
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435 uxCriticalNesting++;
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437 vPortResetPrivilege( xRunningPrivileged );
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439 /*-----------------------------------------------------------*/
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441 void vPortExitCritical( void )
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443 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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445 configASSERT( uxCriticalNesting );
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446 uxCriticalNesting--;
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447 if( uxCriticalNesting == 0 )
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449 portENABLE_INTERRUPTS();
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451 vPortResetPrivilege( xRunningPrivileged );
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453 /*-----------------------------------------------------------*/
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455 void xPortPendSVHandler( void )
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457 /* This is a naked function. */
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464 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
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467 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
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469 " vstmdbeq r0!, {s16-s31} \n"
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471 " mrs r1, control \n"
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472 " stmdb r0!, {r1, r4-r11, r14} \n" /* Save the remaining registers. */
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473 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
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475 " stmdb sp!, {r0, r3} \n"
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477 " msr basepri, r0 \n"
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480 " bl vTaskSwitchContext \n"
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482 " msr basepri, r0 \n"
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483 " ldmia sp!, {r0, r3} \n"
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484 " \n" /* Restore the context. */
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486 " ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */
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487 " add r1, r1, #4 \n" /* Move onto the second item in the TCB... */
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488 " ldr r2, =0xe000ed9c \n" /* Region Base Address register. */
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489 " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */
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490 " stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */
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491 " ldmia r0!, {r3-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry. */
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492 " msr control, r3 \n"
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494 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
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496 " vldmiaeq r0!, {s16-s31} \n"
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502 "pxCurrentTCBConst: .word pxCurrentTCB \n"
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503 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
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506 /*-----------------------------------------------------------*/
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508 void xPortSysTickHandler( void )
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512 ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
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514 /* Increment the RTOS tick. */
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515 if( xTaskIncrementTick() != pdFALSE )
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517 /* Pend a context switch. */
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518 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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521 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
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523 /*-----------------------------------------------------------*/
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526 * Setup the systick timer to generate the tick interrupts at the required
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529 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
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531 /* Stop and clear the SysTick. */
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532 portNVIC_SYSTICK_CTRL_REG = 0UL;
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533 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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535 /* Configure SysTick to interrupt at the requested rate. */
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536 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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537 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
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539 /*-----------------------------------------------------------*/
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541 /* This is a naked function. */
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542 static void vPortEnableVFP( void )
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546 " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
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549 " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
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554 /*-----------------------------------------------------------*/
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556 static void prvSetupMPU( void )
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558 extern uint32_t __privileged_functions_end__[];
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559 extern uint32_t __FLASH_segment_start__[];
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560 extern uint32_t __FLASH_segment_end__[];
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561 extern uint32_t __privileged_data_start__[];
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562 extern uint32_t __privileged_data_end__[];
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564 /* Check the expected MPU is present. */
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565 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
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567 /* First setup the entire flash for unprivileged read only access. */
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568 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
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569 ( portMPU_REGION_VALID ) |
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570 ( portUNPRIVILEGED_FLASH_REGION );
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572 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
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573 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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574 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
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575 ( portMPU_REGION_ENABLE );
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577 /* Setup the first 16K for privileged only access (even though less
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578 than 10K is actually being used). This is where the kernel code is
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580 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
\r
581 ( portMPU_REGION_VALID ) |
\r
582 ( portPRIVILEGED_FLASH_REGION );
\r
584 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
\r
585 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
586 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
\r
587 ( portMPU_REGION_ENABLE );
\r
589 /* Setup the privileged data RAM region. This is where the kernel data
\r
591 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
592 ( portMPU_REGION_VALID ) |
\r
593 ( portPRIVILEGED_RAM_REGION );
\r
595 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
596 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
597 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
598 ( portMPU_REGION_ENABLE );
\r
600 /* By default allow everything to access the general peripherals. The
\r
601 system peripherals and registers are protected. */
\r
602 portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
\r
603 ( portMPU_REGION_VALID ) |
\r
604 ( portGENERAL_PERIPHERALS_REGION );
\r
606 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
\r
607 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
\r
608 ( portMPU_REGION_ENABLE );
\r
610 /* Enable the memory fault exception. */
\r
611 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
\r
613 /* Enable the MPU with the background region configured. */
\r
614 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
\r
617 /*-----------------------------------------------------------*/
\r
619 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
\r
621 uint32_t ulRegionSize, ulReturnValue = 4;
\r
623 /* 32 is the smallest region size, 31 is the largest valid value for
\r
625 for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
\r
627 if( ulActualSizeInBytes <= ulRegionSize )
\r
637 /* Shift the code by one before returning so it can be written directly
\r
638 into the the correct bit position of the attribute register. */
\r
639 return ( ulReturnValue << 1UL );
\r
641 /*-----------------------------------------------------------*/
\r
643 BaseType_t xPortRaisePrivilege( void )
\r
647 " mrs r0, control \n"
\r
648 " tst r0, #1 \n" /* Is the task running privileged? */
\r
650 " movne r0, #0 \n" /* CONTROL[0]!=0, return false. */
\r
651 " svcne %0 \n" /* Switch to privileged. */
\r
652 " moveq r0, #1 \n" /* CONTROL[0]==0, return true. */
\r
654 :: "i" (portSVC_RAISE_PRIVILEGE) : "r0", "memory"
\r
659 /*-----------------------------------------------------------*/
\r
661 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
\r
663 extern uint32_t __SRAM_segment_start__[];
\r
664 extern uint32_t __SRAM_segment_end__[];
\r
665 extern uint32_t __privileged_data_start__[];
\r
666 extern uint32_t __privileged_data_end__[];
\r
670 if( xRegions == NULL )
\r
672 /* No MPU regions are specified so allow access to all RAM. */
\r
673 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
674 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
\r
675 ( portMPU_REGION_VALID ) |
\r
676 ( portSTACK_REGION );
\r
678 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
679 ( portMPU_REGION_READ_WRITE ) |
\r
680 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
681 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
\r
682 ( portMPU_REGION_ENABLE );
\r
684 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
\r
685 just removed the privileged only parameters. */
\r
686 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
\r
687 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
688 ( portMPU_REGION_VALID ) |
\r
689 ( portSTACK_REGION + 1 );
\r
691 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
\r
692 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
693 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
694 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
695 ( portMPU_REGION_ENABLE );
\r
697 /* Invalidate all other regions. */
\r
698 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
700 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
701 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
706 /* This function is called automatically when the task is created - in
\r
707 which case the stack region parameters will be valid. At all other
\r
708 times the stack parameters will not be valid and it is assumed that the
\r
709 stack region has already been configured. */
\r
710 if( ulStackDepth > 0 )
\r
712 /* Define the region that allows access to the stack. */
\r
713 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
714 ( ( uint32_t ) pxBottomOfStack ) |
\r
715 ( portMPU_REGION_VALID ) |
\r
716 ( portSTACK_REGION ); /* Region number. */
\r
718 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
719 ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
\r
720 ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
\r
721 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
722 ( portMPU_REGION_ENABLE );
\r
727 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
729 if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
\r
731 /* Translate the generic region definition contained in
\r
732 xRegions into the CM3 specific MPU settings that are then
\r
733 stored in xMPUSettings. */
\r
734 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
\r
735 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
\r
736 ( portMPU_REGION_VALID ) |
\r
737 ( portSTACK_REGION + ul ); /* Region number. */
\r
739 xMPUSettings->xRegion[ ul ].ulRegionAttribute =
\r
740 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
\r
741 ( xRegions[ lIndex ].ulParameters ) |
\r
742 ( portMPU_REGION_ENABLE );
\r
746 /* Invalidate the region. */
\r
747 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
748 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
755 /*-----------------------------------------------------------*/
\r
757 #if( configASSERT_DEFINED == 1 )
\r
759 void vPortValidateInterruptPriority( void )
\r
761 uint32_t ulCurrentInterrupt;
\r
762 uint8_t ucCurrentPriority;
\r
764 /* Obtain the number of the currently executing interrupt. */
\r
765 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
\r
767 /* Is the interrupt number a user defined interrupt? */
\r
768 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
770 /* Look up the interrupt's priority. */
\r
771 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
773 /* The following assertion will fail if a service routine (ISR) for
\r
774 an interrupt that has been assigned a priority above
\r
775 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
776 function. ISR safe FreeRTOS API functions must *only* be called
\r
777 from interrupts that have been assigned a priority at or below
\r
778 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
780 Numerically low interrupt priority numbers represent logically high
\r
781 interrupt priorities, therefore the priority of the interrupt must
\r
782 be set to a value equal to or numerically *higher* than
\r
783 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
785 Interrupts that use the FreeRTOS API must not be left at their
\r
786 default priority of zero as that is the highest possible priority,
\r
787 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
788 and therefore also guaranteed to be invalid.
\r
790 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
791 interrupt entry is as fast and simple as possible.
\r
793 The following links provide detailed information:
\r
794 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
795 http://www.freertos.org/FAQHelp.html */
\r
796 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
799 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
800 that define each interrupt's priority to be split between bits that
\r
801 define the interrupt's pre-emption priority bits and bits that define
\r
802 the interrupt's sub-priority. For simplicity all bits must be defined
\r
803 to be pre-emption priority bits. The following assertion will fail if
\r
804 this is not the case (if some bits represent a sub-priority).
\r
806 If the application only uses CMSIS libraries for interrupt
\r
807 configuration then the correct setting can be achieved on all Cortex-M
\r
808 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
809 scheduler. Note however that some vendor specific peripheral libraries
\r
810 assume a non-zero priority group setting, in which cases using a value
\r
811 of zero will result in unpredicable behaviour. */
\r
812 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
815 #endif /* configASSERT_DEFINED */
\r
816 /*-----------------------------------------------------------*/
\r