git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c

   1 /*\r
   2  * FreeRTOS Kernel V10.0.0\r
   3  * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software. If you wish to use our Amazon\r
  14  * FreeRTOS name, please do so in a fair use way that does not cause confusion.\r
  15  *\r
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  18  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  19  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  20  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  22  *\r
  23  * http://www.FreeRTOS.org\r
  24  * http://aws.amazon.com/freertos\r
  25  *\r
  26  * 1 tab == 4 spaces!\r
  27  */\r
  28 \r
  29 /*-----------------------------------------------------------\r
  30  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  31  *----------------------------------------------------------*/\r
  32 \r
  33 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
  34 all the API functions to use the MPU wrappers.  That should only be done when\r
  35 task.h is included from an application file. */\r
  36 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  37 \r
  38 /* Scheduler includes. */\r
  39 #include "FreeRTOS.h"\r
  40 #include "task.h"\r
  41 \r
  42 #ifndef __VFP_FP__\r
  43         #error This port can only be used when the project options are configured to enable hardware floating point support.\r
  44 #endif\r
  45 \r
  46 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  47 \r
  48 #ifndef configSYSTICK_CLOCK_HZ\r
  49         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  50         /* Ensure the SysTick is clocked at the same frequency as the core. */\r
  51         #define portNVIC_SYSTICK_CLK    ( 1UL << 2UL )\r
  52 #else\r
  53         /* The way the SysTick is clocked is not modified in case it is not the same\r
  54         as the core. */\r
  55         #define portNVIC_SYSTICK_CLK    ( 0 )\r
  56 #endif\r
  57 \r
  58 /* Constants required to access and manipulate the NVIC. */\r
  59 #define portNVIC_SYSTICK_CTRL_REG                               ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
  60 #define portNVIC_SYSTICK_LOAD_REG                               ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
  61 #define portNVIC_SYSTICK_CURRENT_VALUE_REG              ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
  62 #define portNVIC_SYSPRI2_REG                                    ( *     ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
  63 #define portNVIC_SYSPRI1_REG                                    ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )\r
  64 #define portNVIC_SYS_CTRL_STATE_REG                             ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )\r
  65 #define portNVIC_MEM_FAULT_ENABLE                               ( 1UL << 16UL )\r
  66 \r
  67 /* Constants required to access and manipulate the MPU. */\r
  68 #define portMPU_TYPE_REG                                                ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
  69 #define portMPU_REGION_BASE_ADDRESS_REG                 ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )\r
  70 #define portMPU_REGION_ATTRIBUTE_REG                    ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )\r
  71 #define portMPU_CTRL_REG                                                ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
  72 #define portEXPECTED_MPU_TYPE_VALUE                             ( 8UL << 8UL ) /* 8 regions, unified. */\r
  73 #define portMPU_ENABLE                                                  ( 0x01UL )\r
  74 #define portMPU_BACKGROUND_ENABLE                               ( 1UL << 2UL )\r
  75 #define portPRIVILEGED_EXECUTION_START_ADDRESS  ( 0UL )\r
  76 #define portMPU_REGION_VALID                                    ( 0x10UL )\r
  77 #define portMPU_REGION_ENABLE                                   ( 0x01UL )\r
  78 #define portPERIPHERALS_START_ADDRESS                   0x40000000UL\r
  79 #define portPERIPHERALS_END_ADDRESS                             0x5FFFFFFFUL\r
  80 \r
  81 /* Constants required to access and manipulate the SysTick. */\r
  82 #define portNVIC_SYSTICK_INT                                    ( 0x00000002UL )\r
  83 #define portNVIC_SYSTICK_ENABLE                                 ( 0x00000001UL )\r
  84 #define portNVIC_PENDSV_PRI                                             ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
  85 #define portNVIC_SYSTICK_PRI                                    ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
  86 #define portNVIC_SVC_PRI                                                ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )\r
  87 \r
  88 /* Constants required to manipulate the VFP. */\r
  89 #define portFPCCR                                                               ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */\r
  90 #define portASPEN_AND_LSPEN_BITS                                ( 0x3UL << 30UL )\r
  91 \r
  92 /* Constants required to set up the initial stack. */\r
  93 #define portINITIAL_XPSR                                                ( 0x01000000UL )\r
  94 #define portINITIAL_EXC_RETURN                                  ( 0xfffffffdUL )\r
  95 #define portINITIAL_CONTROL_IF_UNPRIVILEGED             ( 0x03 )\r
  96 #define portINITIAL_CONTROL_IF_PRIVILEGED               ( 0x02 )\r
  97 \r
  98 /* Constants required to check the validity of an interrupt priority. */\r
  99 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
 100 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
 101 #define portAIRCR_REG                                           ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
 102 #define portMAX_8_BIT_VALUE                                     ( ( uint8_t ) 0xff )\r
 103 #define portTOP_BIT_OF_BYTE                                     ( ( uint8_t ) 0x80 )\r
 104 #define portMAX_PRIGROUP_BITS                           ( ( uint8_t ) 7 )\r
 105 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
 106 #define portPRIGROUP_SHIFT                                      ( 8UL )\r
 107 \r
 108 /* Offsets in the stack to the parameters when inside the SVC handler. */\r
 109 #define portOFFSET_TO_PC                                                ( 6 )\r
 110 \r
 111 /* For strict compliance with the Cortex-M spec the task start address should\r
 112 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\r
 113 #define portSTART_ADDRESS_MASK                          ( ( StackType_t ) 0xfffffffeUL )\r
 114 \r
 115 /*\r
 116  * Configure a number of standard MPU regions that are used by all tasks.\r
 117  */\r
 118 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
 119 \r
 120 /*\r
 121  * Return the smallest MPU region size that a given number of bytes will fit\r
 122  * into.  The region size is returned as the value that should be programmed\r
 123  * into the region attribute register for that region.\r
 124  */\r
 125 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
 126 \r
 127 /*\r
 128  * Checks to see if being called from the context of an unprivileged task, and\r
 129  * if so raises the privilege level and returns false - otherwise does nothing\r
 130  * other than return true.\r
 131  */\r
 132 BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));\r
 133 \r
 134 /*\r
 135  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 136  * file is weak to allow application writers to change the timer used to\r
 137  * generate the tick interrupt.\r
 138  */\r
 139 void vPortSetupTimerInterrupt( void );\r
 140 \r
 141 /*\r
 142  * Standard FreeRTOS exception handlers.\r
 143  */\r
 144 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 145 void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;\r
 146 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 147 \r
 148 /*\r
 149  * Starts the scheduler by restoring the context of the first task to run.\r
 150  */\r
 151 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
 152 \r
 153 /*\r
 154  * C portion of the SVC handler.  The SVC handler is split between an asm entry\r
 155  * and a C wrapper for simplicity of coding and maintenance.\r
 156  */\r
 157 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
 158 \r
 159 /*\r
 160  * Function to enable the VFP.\r
 161  */\r
 162  static void vPortEnableVFP( void ) __attribute__ (( naked ));\r
 163 \r
 164 /*-----------------------------------------------------------*/\r
 165 \r
 166 /* Each task maintains its own interrupt status in the critical nesting\r
 167 variable.  Note this is not saved as part of the task context as context\r
 168 switches can only occur when uxCriticalNesting is zero. */\r
 169 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
 170 \r
 171 /*\r
 172  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
 173  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 174  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 175  */\r
 176 #if ( configASSERT_DEFINED == 1 )\r
 177          static uint8_t ucMaxSysCallPriority = 0;\r
 178          static uint32_t ulMaxPRIGROUPValue = 0;\r
 179          static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 180 #endif /* configASSERT_DEFINED */\r
 181 \r
 182 /*-----------------------------------------------------------*/\r
 183 \r
 184 /*\r
 185  * See header file for description.\r
 186  */\r
 187 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )\r
 188 {\r
 189         /* Simulate the stack frame as it would be created by a context switch\r
 190         interrupt. */\r
 191         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 192         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 193         pxTopOfStack--;\r
 194         *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;    /* PC */\r
 195         pxTopOfStack--;\r
 196         *pxTopOfStack = 0;      /* LR */\r
 197         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 198         *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
 199 \r
 200         /* A save method is being used that requires each task to maintain its\r
 201         own exec return value. */\r
 202         pxTopOfStack--;\r
 203         *pxTopOfStack = portINITIAL_EXC_RETURN;\r
 204 \r
 205         pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 206 \r
 207         if( xRunPrivileged == pdTRUE )\r
 208         {\r
 209                 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\r
 210         }\r
 211         else\r
 212         {\r
 213                 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\r
 214         }\r
 215 \r
 216         return pxTopOfStack;\r
 217 }\r
 218 /*-----------------------------------------------------------*/\r
 219 \r
 220 void vPortSVCHandler( void )\r
 221 {\r
 222         /* Assumes psp was in use. */\r
 223         __asm volatile\r
 224         (\r
 225                 #ifndef USE_PROCESS_STACK       /* Code should not be required if a main() is using the process stack. */\r
 226                         "       tst lr, #4                                              \n"\r
 227                         "       ite eq                                                  \n"\r
 228                         "       mrseq r0, msp                                   \n"\r
 229                         "       mrsne r0, psp                                   \n"\r
 230                 #else\r
 231                         "       mrs r0, psp                                             \n"\r
 232                 #endif\r
 233                         "       b %0                                                    \n"\r
 234                         ::"i"(prvSVCHandler):"r0", "memory"\r
 235         );\r
 236 }\r
 237 /*-----------------------------------------------------------*/\r
 238 \r
 239 static void prvSVCHandler(      uint32_t *pulParam )\r
 240 {\r
 241 uint8_t ucSVCNumber;\r
 242 \r
 243         /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and\r
 244         xPSR.  The first argument (r0) is pulParam[ 0 ]. */\r
 245         ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];\r
 246         switch( ucSVCNumber )\r
 247         {\r
 248                 case portSVC_START_SCHEDULER    :       portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;\r
 249                                                                                         prvRestoreContextOfFirstTask();\r
 250                                                                                         break;\r
 251 \r
 252                 case portSVC_YIELD                              :       portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 253                                                                                         /* Barriers are normally not required\r
 254                                                                                         but do ensure the code is completely\r
 255                                                                                         within the specified behaviour for the\r
 256                                                                                         architecture. */\r
 257                                                                                         __asm volatile( "dsb" ::: "memory" );\r
 258                                                                                         __asm volatile( "isb" );\r
 259 \r
 260                                                                                         break;\r
 261 \r
 262                 case portSVC_RAISE_PRIVILEGE    :       __asm volatile\r
 263                                                                                         (\r
 264                                                                                                 "       mrs r1, control         \n" /* Obtain current control value. */\r
 265                                                                                                 "       bic r1, #1                      \n" /* Set privilege bit. */\r
 266                                                                                                 "       msr control, r1         \n" /* Write back new control value. */\r
 267                                                                                                 ::: "r1", "memory"\r
 268                                                                                         );\r
 269                                                                                         break;\r
 270 \r
 271                 default                                                 :       /* Unknown SVC call. */\r
 272                                                                                         break;\r
 273         }\r
 274 }\r
 275 /*-----------------------------------------------------------*/\r
 276 \r
 277 static void prvRestoreContextOfFirstTask( void )\r
 278 {\r
 279         __asm volatile\r
 280         (\r
 281                 "       ldr r0, =0xE000ED08                             \n" /* Use the NVIC offset register to locate the stack. */\r
 282                 "       ldr r0, [r0]                                    \n"\r
 283                 "       ldr r0, [r0]                                    \n"\r
 284                 "       msr msp, r0                                             \n" /* Set the msp back to the start of the stack. */\r
 285                 "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 286                 "       ldr r1, [r3]                                    \n"\r
 287                 "       ldr r0, [r1]                                    \n" /* The first item in the TCB is the task top of stack. */\r
 288                 "       add r1, r1, #4                                  \n" /* Move onto the second item in the TCB... */\r
 289                 "       ldr r2, =0xe000ed9c                             \n" /* Region Base Address register. */\r
 290                 "       ldmia r1!, {r4-r11}                             \n" /* Read 4 sets of MPU registers. */\r
 291                 "       stmia r2!, {r4-r11}                             \n" /* Write 4 sets of MPU registers. */\r
 292                 "       ldmia r0!, {r3-r11, r14}                \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 293                 "       msr control, r3                                 \n"\r
 294                 "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 295                 "       mov r0, #0                                              \n"\r
 296                 "       msr     basepri, r0                                     \n"\r
 297                 "       bx r14                                                  \n"\r
 298                 "                                                                       \n"\r
 299                 "       .align 4                                                \n"\r
 300                 "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
 301         );\r
 302 }\r
 303 /*-----------------------------------------------------------*/\r
 304 \r
 305 /*\r
 306  * See header file for description.\r
 307  */\r
 308 BaseType_t xPortStartScheduler( void )\r
 309 {\r
 310         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See\r
 311         http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 312         configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\r
 313 \r
 314         #if( configASSERT_DEFINED == 1 )\r
 315         {\r
 316                 volatile uint32_t ulOriginalPriority;\r
 317                 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 318                 volatile uint8_t ucMaxPriorityValue;\r
 319 \r
 320                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 321                 functions can be called.  ISR safe functions are those that end in\r
 322                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 323                 ensure interrupt entry is as fast and simple as possible.\r
 324 \r
 325                 Save the interrupt priority value that is about to be clobbered. */\r
 326                 ulOriginalPriority = *pucFirstUserPriorityRegister;\r
 327 \r
 328                 /* Determine the number of priority bits available.  First write to all\r
 329                 possible bits. */\r
 330                 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
 331 \r
 332                 /* Read the value back to see how many bits stuck. */\r
 333                 ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
 334 \r
 335                 /* Use the same mask on the maximum system call priority. */\r
 336                 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
 337 \r
 338                 /* Calculate the maximum acceptable priority group value for the number\r
 339                 of bits read back. */\r
 340                 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
 341                 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
 342                 {\r
 343                         ulMaxPRIGROUPValue--;\r
 344                         ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
 345                 }\r
 346 \r
 347                 #ifdef __NVIC_PRIO_BITS\r
 348                 {\r
 349                         /* Check the CMSIS configuration that defines the number of\r
 350                         priority bits matches the number of priority bits actually queried\r
 351                         from the hardware. */\r
 352                         configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\r
 353                 }\r
 354                 #endif\r
 355 \r
 356                 #ifdef configPRIO_BITS\r
 357                 {\r
 358                         /* Check the FreeRTOS configuration that defines the number of\r
 359                         priority bits matches the number of priority bits actually queried\r
 360                         from the hardware. */\r
 361                         configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\r
 362                 }\r
 363                 #endif\r
 364 \r
 365                 /* Shift the priority group value back to its position within the AIRCR\r
 366                 register. */\r
 367                 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
 368                 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
 369 \r
 370                 /* Restore the clobbered interrupt priority register to its original\r
 371                 value. */\r
 372                 *pucFirstUserPriorityRegister = ulOriginalPriority;\r
 373         }\r
 374         #endif /* conifgASSERT_DEFINED */\r
 375 \r
 376         /* Make PendSV and SysTick the same priority as the kernel, and the SVC\r
 377         handler higher priority so it can be used to exit a critical section (where\r
 378         lower priorities are masked). */\r
 379         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 380         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 381 \r
 382         /* Configure the regions in the MPU that are common to all tasks. */\r
 383         prvSetupMPU();\r
 384 \r
 385         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 386         here already. */\r
 387         vPortSetupTimerInterrupt();\r
 388 \r
 389         /* Initialise the critical nesting count ready for the first task. */\r
 390         uxCriticalNesting = 0;\r
 391 \r
 392         /* Ensure the VFP is enabled - it should be anyway. */\r
 393         vPortEnableVFP();\r
 394 \r
 395         /* Lazy save always. */\r
 396         *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
 397 \r
 398         /* Start the first task.  This also clears the bit that indicates the FPU is\r
 399         in use in case the FPU was used before the scheduler was started - which\r
 400         would otherwise result in the unnecessary leaving of space in the SVC stack\r
 401         for lazy saving of FPU registers. */\r
 402         __asm volatile(\r
 403                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 404                                         " ldr r0, [r0]                  \n"\r
 405                                         " ldr r0, [r0]                  \n"\r
 406                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 407                                         " mov r0, #0                    \n" /* Clear the bit that indicates the FPU is in use, see comment above. */\r
 408                                         " msr control, r0               \n"\r
 409                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 410                                         " cpsie f                               \n"\r
 411                                         " dsb                                   \n"\r
 412                                         " isb                                   \n"\r
 413                                         " svc %0                                \n" /* System call to start first task. */\r
 414                                         " nop                                   \n"\r
 415                                         :: "i" (portSVC_START_SCHEDULER) : "memory" );\r
 416 \r
 417         /* Should not get here! */\r
 418         return 0;\r
 419 }\r
 420 /*-----------------------------------------------------------*/\r
 421 \r
 422 void vPortEndScheduler( void )\r
 423 {\r
 424         /* Not implemented in ports where there is nothing to return to.\r
 425         Artificially force an assert. */\r
 426         configASSERT( uxCriticalNesting == 1000UL );\r
 427 }\r
 428 /*-----------------------------------------------------------*/\r
 429 \r
 430 void vPortEnterCritical( void )\r
 431 {\r
 432 BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
 433 \r
 434         portDISABLE_INTERRUPTS();\r
 435         uxCriticalNesting++;\r
 436 \r
 437         vPortResetPrivilege( xRunningPrivileged );\r
 438 }\r
 439 /*-----------------------------------------------------------*/\r
 440 \r
 441 void vPortExitCritical( void )\r
 442 {\r
 443 BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
 444 \r
 445         configASSERT( uxCriticalNesting );\r
 446         uxCriticalNesting--;\r
 447         if( uxCriticalNesting == 0 )\r
 448         {\r
 449                 portENABLE_INTERRUPTS();\r
 450         }\r
 451         vPortResetPrivilege( xRunningPrivileged );\r
 452 }\r
 453 /*-----------------------------------------------------------*/\r
 454 \r
 455 void xPortPendSVHandler( void )\r
 456 {\r
 457         /* This is a naked function. */\r
 458 \r
 459         __asm volatile\r
 460         (\r
 461                 "       mrs r0, psp                                                     \n"\r
 462                 "       isb                                                                     \n"\r
 463                 "                                                                               \n"\r
 464                 "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 465                 "       ldr     r2, [r3]                                                \n"\r
 466                 "                                                                               \n"\r
 467                 "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, push high vfp registers. */\r
 468                 "       it eq                                                           \n"\r
 469                 "       vstmdbeq r0!, {s16-s31}                         \n"\r
 470                 "                                                                               \n"\r
 471                 "       mrs r1, control                                         \n"\r
 472                 "       stmdb r0!, {r1, r4-r11, r14}            \n" /* Save the remaining registers. */\r
 473                 "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 474                 "                                                                               \n"\r
 475                 "       stmdb sp!, {r0, r3}                                     \n"\r
 476                 "       mov r0, %0                                                      \n"\r
 477                 "       msr basepri, r0                                         \n"\r
 478                 "       dsb                                                                     \n"\r
 479                 "       isb                                                                     \n"\r
 480                 "       bl vTaskSwitchContext                           \n"\r
 481                 "       mov r0, #0                                                      \n"\r
 482                 "       msr basepri, r0                                         \n"\r
 483                 "       ldmia sp!, {r0, r3}                                     \n"\r
 484                 "                                                                               \n" /* Restore the context. */\r
 485                 "       ldr r1, [r3]                                            \n"\r
 486                 "       ldr r0, [r1]                                            \n" /* The first item in the TCB is the task top of stack. */\r
 487                 "       add r1, r1, #4                                          \n" /* Move onto the second item in the TCB... */\r
 488                 "       ldr r2, =0xe000ed9c                                     \n" /* Region Base Address register. */\r
 489                 "       ldmia r1!, {r4-r11}                                     \n" /* Read 4 sets of MPU registers. */\r
 490                 "       stmia r2!, {r4-r11}                                     \n" /* Write 4 sets of MPU registers. */\r
 491                 "       ldmia r0!, {r3-r11, r14}                        \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 492                 "       msr control, r3                                         \n"\r
 493                 "                                                                               \n"\r
 494                 "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\r
 495                 "       it eq                                                           \n"\r
 496                 "       vldmiaeq r0!, {s16-s31}                         \n"\r
 497                 "                                                                               \n"\r
 498                 "       msr psp, r0                                                     \n"\r
 499                 "       bx r14                                                          \n"\r
 500                 "                                                                               \n"\r
 501                 "       .align 4                                                        \n"\r
 502                 "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 503                 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 504         );\r
 505 }\r
 506 /*-----------------------------------------------------------*/\r
 507 \r
 508 void xPortSysTickHandler( void )\r
 509 {\r
 510 uint32_t ulDummy;\r
 511 \r
 512         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
 513         {\r
 514                 /* Increment the RTOS tick. */\r
 515                 if( xTaskIncrementTick() != pdFALSE )\r
 516                 {\r
 517                         /* Pend a context switch. */\r
 518                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 519                 }\r
 520         }\r
 521         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
 522 }\r
 523 /*-----------------------------------------------------------*/\r
 524 \r
 525 /*\r
 526  * Setup the systick timer to generate the tick interrupts at the required\r
 527  * frequency.\r
 528  */\r
 529 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 530 {\r
 531         /* Stop and clear the SysTick. */\r
 532         portNVIC_SYSTICK_CTRL_REG = 0UL;\r
 533         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 534 \r
 535         /* Configure SysTick to interrupt at the requested rate. */\r
 536         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 537         portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );\r
 538 }\r
 539 /*-----------------------------------------------------------*/\r
 540 \r
 541 /* This is a naked function. */\r
 542 static void vPortEnableVFP( void )\r
 543 {\r
 544         __asm volatile\r
 545         (\r
 546                 "       ldr.w r0, =0xE000ED88           \n" /* The FPU enable bits are in the CPACR. */\r
 547                 "       ldr r1, [r0]                            \n"\r
 548                 "                                                               \n"\r
 549                 "       orr r1, r1, #( 0xf << 20 )      \n" /* Enable CP10 and CP11 coprocessors, then save back. */\r
 550                 "       str r1, [r0]                            \n"\r
 551                 "       bx r14                                          "\r
 552         );\r
 553 }\r
 554 /*-----------------------------------------------------------*/\r
 555 \r
 556 static void prvSetupMPU( void )\r
 557 {\r
 558 extern uint32_t __privileged_functions_end__[];\r
 559 extern uint32_t __FLASH_segment_start__[];\r
 560 extern uint32_t __FLASH_segment_end__[];\r
 561 extern uint32_t __privileged_data_start__[];\r
 562 extern uint32_t __privileged_data_end__[];\r
 563 \r
 564         /* Check the expected MPU is present. */\r
 565         if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
 566         {\r
 567                 /* First setup the entire flash for unprivileged read only access. */\r
 568                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 569                                                                                         ( portMPU_REGION_VALID ) |\r
 570                                                                                         ( portUNPRIVILEGED_FLASH_REGION );\r
 571 \r
 572                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_ONLY ) |\r
 573                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 574                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 575                                                                                 ( portMPU_REGION_ENABLE );\r
 576 \r
 577                 /* Setup the first 16K for privileged only access (even though less\r
 578                 than 10K is actually being used).  This is where the kernel code is\r
 579                 placed. */\r
 580                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 581                                                                                         ( portMPU_REGION_VALID ) |\r
 582                                                                                         ( portPRIVILEGED_FLASH_REGION );\r
 583 \r
 584                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
 585                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 586                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 587                                                                                 ( portMPU_REGION_ENABLE );\r
 588 \r
 589                 /* Setup the privileged data RAM region.  This is where the kernel data\r
 590                 is placed. */\r
 591                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 592                                                                                         ( portMPU_REGION_VALID ) |\r
 593                                                                                         ( portPRIVILEGED_RAM_REGION );\r
 594 \r
 595                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 596                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 597                                                                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 598                                                                                 ( portMPU_REGION_ENABLE );\r
 599 \r
 600                 /* By default allow everything to access the general peripherals.  The\r
 601                 system peripherals and registers are protected. */\r
 602                 portMPU_REGION_BASE_ADDRESS_REG =       ( portPERIPHERALS_START_ADDRESS ) |\r
 603                                                                                         ( portMPU_REGION_VALID ) |\r
 604                                                                                         ( portGENERAL_PERIPHERALS_REGION );\r
 605 \r
 606                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
 607                                                                                 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\r
 608                                                                                 ( portMPU_REGION_ENABLE );\r
 609 \r
 610                 /* Enable the memory fault exception. */\r
 611                 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;\r
 612 \r
 613                 /* Enable the MPU with the background region configured. */\r
 614                 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
 615         }\r
 616 }\r
 617 /*-----------------------------------------------------------*/\r
 618 \r
 619 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )\r
 620 {\r
 621 uint32_t ulRegionSize, ulReturnValue = 4;\r
 622 \r
 623         /* 32 is the smallest region size, 31 is the largest valid value for\r
 624         ulReturnValue. */\r
 625         for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\r
 626         {\r
 627                 if( ulActualSizeInBytes <= ulRegionSize )\r
 628                 {\r
 629                         break;\r
 630                 }\r
 631                 else\r
 632                 {\r
 633                         ulReturnValue++;\r
 634                 }\r
 635         }\r
 636 \r
 637         /* Shift the code by one before returning so it can be written directly\r
 638         into the the correct bit position of the attribute register. */\r
 639         return ( ulReturnValue << 1UL );\r
 640 }\r
 641 /*-----------------------------------------------------------*/\r
 642 \r
 643 BaseType_t xPortRaisePrivilege( void )\r
 644 {\r
 645         __asm volatile\r
 646         (\r
 647                 "       mrs r0, control                                         \n"\r
 648                 "       tst r0, #1                                                      \n" /* Is the task running privileged? */\r
 649                 "       itte ne                                                         \n"\r
 650                 "       movne r0, #0                                            \n" /* CONTROL[0]!=0, return false. */\r
 651                 "       svcne %0                                                        \n" /* Switch to privileged. */\r
 652                 "       moveq r0, #1                                            \n" /* CONTROL[0]==0, return true. */\r
 653                 "       bx lr                                                           \n"\r
 654                 :: "i" (portSVC_RAISE_PRIVILEGE) : "r0", "memory"\r
 655         );\r
 656 \r
 657         return 0;\r
 658 }\r
 659 /*-----------------------------------------------------------*/\r
 660 \r
 661 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
 662 {\r
 663 extern uint32_t __SRAM_segment_start__[];\r
 664 extern uint32_t __SRAM_segment_end__[];\r
 665 extern uint32_t __privileged_data_start__[];\r
 666 extern uint32_t __privileged_data_end__[];\r
 667 int32_t lIndex;\r
 668 uint32_t ul;\r
 669 \r
 670         if( xRegions == NULL )\r
 671         {\r
 672                 /* No MPU regions are specified so allow access to all RAM. */\r
 673                 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 674                                 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */\r
 675                                 ( portMPU_REGION_VALID ) |\r
 676                                 ( portSTACK_REGION );\r
 677 \r
 678                 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 679                                 ( portMPU_REGION_READ_WRITE ) |\r
 680                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 681                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |\r
 682                                 ( portMPU_REGION_ENABLE );\r
 683 \r
 684                 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
 685                 just removed the privileged only parameters. */\r
 686                 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =\r
 687                                 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 688                                 ( portMPU_REGION_VALID ) |\r
 689                                 ( portSTACK_REGION + 1 );\r
 690 \r
 691                 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =\r
 692                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 693                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 694                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 695                                 ( portMPU_REGION_ENABLE );\r
 696 \r
 697                 /* Invalidate all other regions. */\r
 698                 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 699                 {\r
 700                         xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 701                         xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 702                 }\r
 703         }\r
 704         else\r
 705         {\r
 706                 /* This function is called automatically when the task is created - in\r
 707                 which case the stack region parameters will be valid.  At all other\r
 708                 times the stack parameters will not be valid and it is assumed that the\r
 709                 stack region has already been configured. */\r
 710                 if( ulStackDepth > 0 )\r
 711                 {\r
 712                         /* Define the region that allows access to the stack. */\r
 713                         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 714                                         ( ( uint32_t ) pxBottomOfStack ) |\r
 715                                         ( portMPU_REGION_VALID ) |\r
 716                                         ( portSTACK_REGION ); /* Region number. */\r
 717 \r
 718                         xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 719                                         ( portMPU_REGION_READ_WRITE ) | /* Read and write. */\r
 720                                         ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |\r
 721                                         ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 722                                         ( portMPU_REGION_ENABLE );\r
 723                 }\r
 724 \r
 725                 lIndex = 0;\r
 726 \r
 727                 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 728                 {\r
 729                         if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\r
 730                         {\r
 731                                 /* Translate the generic region definition contained in\r
 732                                 xRegions into the CM3 specific MPU settings that are then\r
 733                                 stored in xMPUSettings. */\r
 734                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\r
 735                                                 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |\r
 736                                                 ( portMPU_REGION_VALID ) |\r
 737                                                 ( portSTACK_REGION + ul ); /* Region number. */\r
 738 \r
 739                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute =\r
 740                                                 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\r
 741                                                 ( xRegions[ lIndex ].ulParameters ) |\r
 742                                                 ( portMPU_REGION_ENABLE );\r
 743                         }\r
 744                         else\r
 745                         {\r
 746                                 /* Invalidate the region. */\r
 747                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 748                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 749                         }\r
 750 \r
 751                         lIndex++;\r
 752                 }\r
 753         }\r
 754 }\r
 755 /*-----------------------------------------------------------*/\r
 756 \r
 757 #if( configASSERT_DEFINED == 1 )\r
 758 \r
 759         void vPortValidateInterruptPriority( void )\r
 760         {\r
 761         uint32_t ulCurrentInterrupt;\r
 762         uint8_t ucCurrentPriority;\r
 763 \r
 764                 /* Obtain the number of the currently executing interrupt. */\r
 765                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
 766 \r
 767                 /* Is the interrupt number a user defined interrupt? */\r
 768                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 769                 {\r
 770                         /* Look up the interrupt's priority. */\r
 771                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 772 \r
 773                         /* The following assertion will fail if a service routine (ISR) for\r
 774                         an interrupt that has been assigned a priority above\r
 775                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 776                         function.  ISR safe FreeRTOS API functions must *only* be called\r
 777                         from interrupts that have been assigned a priority at or below\r
 778                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 779 \r
 780                         Numerically low interrupt priority numbers represent logically high\r
 781                         interrupt priorities, therefore the priority of the interrupt must\r
 782                         be set to a value equal to or numerically *higher* than\r
 783                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 784 \r
 785                         Interrupts that use the FreeRTOS API must not be left at their\r
 786                         default priority of     zero as that is the highest possible priority,\r
 787                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
 788                         and     therefore also guaranteed to be invalid.\r
 789 \r
 790                         FreeRTOS maintains separate thread and ISR API functions to ensure\r
 791                         interrupt entry is as fast and simple as possible.\r
 792 \r
 793                         The following links provide detailed information:\r
 794                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 795                         http://www.freertos.org/FAQHelp.html */\r
 796                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 797                 }\r
 798 \r
 799                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits\r
 800                 that define each interrupt's priority to be split between bits that\r
 801                 define the interrupt's pre-emption priority bits and bits that define\r
 802                 the interrupt's sub-priority.  For simplicity all bits must be defined\r
 803                 to be pre-emption priority bits.  The following assertion will fail if\r
 804                 this is not the case (if some bits represent a sub-priority).\r
 805 \r
 806                 If the application only uses CMSIS libraries for interrupt\r
 807                 configuration then the correct setting can be achieved on all Cortex-M\r
 808                 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
 809                 scheduler.  Note however that some vendor specific peripheral libraries\r
 810                 assume a non-zero priority group setting, in which cases using a value\r
 811                 of zero will result in unpredicable behaviour. */\r
 812                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
 813         }\r
 814 \r
 815 #endif /* configASSERT_DEFINED */\r
 816 /*-----------------------------------------------------------*/\r
 817 \r
 818 \r