git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c

   1 /*\r
   2     FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     This file is part of the FreeRTOS distribution.\r
   8 \r
   9     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  10     the terms of the GNU General Public License (version 2) as published by the\r
  11     Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
  12 \r
  13     ***************************************************************************\r
  14     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  15     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  16     >>!   obliged to provide the source code for proprietary components     !<<\r
  17     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  18     ***************************************************************************\r
  19 \r
  20     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  21     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  22     FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
  23     link: http://www.freertos.org/a00114.html\r
  24 \r
  25     ***************************************************************************\r
  26      *                                                                       *\r
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  35      *    http://www.FreeRTOS.org/Documentation                              *\r
  36      *                                                                       *\r
  37     ***************************************************************************\r
  38 \r
  39     http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r
  40     the FAQ page "My application does not run, what could be wrong?".  Have you\r
  41     defined configASSERT()?\r
  42 \r
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  60     Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  61     licenses offer ticketed support, indemnification and commercial middleware.\r
  62 \r
  63     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  64     engineered and independently SIL3 certified version for use in safety and\r
  65     mission critical applications that require provable dependability.\r
  66 \r
  67     1 tab == 4 spaces!\r
  68 */\r
  69 \r
  70 /*-----------------------------------------------------------\r
  71  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  72  *----------------------------------------------------------*/\r
  73 \r
  74 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
  75 all the API functions to use the MPU wrappers.  That should only be done when\r
  76 task.h is included from an application file. */\r
  77 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  78 \r
  79 /* Scheduler includes. */\r
  80 #include "FreeRTOS.h"\r
  81 #include "queue.h"\r
  82 #include "event_groups.h"\r
  83 #include "mpu_prototypes.h"\r
  84 \r
  85 #ifndef __VFP_FP__\r
  86         #error This port can only be used when the project options are configured to enable hardware floating point support.\r
  87 #endif\r
  88 \r
  89 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  90 \r
  91 /* Constants required to access and manipulate the NVIC. */\r
  92 #define portNVIC_SYSTICK_CTRL_REG                               ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
  93 #define portNVIC_SYSTICK_LOAD_REG                               ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
  94 #define portNVIC_SYSTICK_CURRENT_VALUE_REG              ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
  95 #define portNVIC_SYSPRI2_REG                                    ( *     ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
  96 #define portNVIC_SYSPRI1_REG                                    ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )\r
  97 #define portNVIC_SYS_CTRL_STATE_REG                             ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )\r
  98 #define portNVIC_MEM_FAULT_ENABLE                               ( 1UL << 16UL )\r
  99 \r
 100 /* Constants required to access and manipulate the MPU. */\r
 101 #define portMPU_TYPE_REG                                                ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
 102 #define portMPU_REGION_BASE_ADDRESS_REG                 ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )\r
 103 #define portMPU_REGION_ATTRIBUTE_REG                    ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )\r
 104 #define portMPU_CTRL_REG                                                ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
 105 #define portEXPECTED_MPU_TYPE_VALUE                             ( 8UL << 8UL ) /* 8 regions, unified. */\r
 106 #define portMPU_ENABLE                                                  ( 0x01UL )\r
 107 #define portMPU_BACKGROUND_ENABLE                               ( 1UL << 2UL )\r
 108 #define portPRIVILEGED_EXECUTION_START_ADDRESS  ( 0UL )\r
 109 #define portMPU_REGION_VALID                                    ( 0x10UL )\r
 110 #define portMPU_REGION_ENABLE                                   ( 0x01UL )\r
 111 #define portPERIPHERALS_START_ADDRESS                   0x40000000UL\r
 112 #define portPERIPHERALS_END_ADDRESS                             0x5FFFFFFFUL\r
 113 \r
 114 /* Constants required to access and manipulate the SysTick. */\r
 115 #define portNVIC_SYSTICK_CLK                                    ( 0x00000004UL )\r
 116 #define portNVIC_SYSTICK_INT                                    ( 0x00000002UL )\r
 117 #define portNVIC_SYSTICK_ENABLE                                 ( 0x00000001UL )\r
 118 #define portNVIC_PENDSV_PRI                                             ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 119 #define portNVIC_SYSTICK_PRI                                    ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 120 #define portNVIC_SVC_PRI                                                ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )\r
 121 \r
 122 /* Constants required to manipulate the VFP. */\r
 123 #define portFPCCR                                                               ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */\r
 124 #define portASPEN_AND_LSPEN_BITS                                ( 0x3UL << 30UL )\r
 125 \r
 126 /* Constants required to set up the initial stack. */\r
 127 #define portINITIAL_XPSR                                                ( 0x01000000UL )\r
 128 #define portINITIAL_EXEC_RETURN                                 ( 0xfffffffdUL )\r
 129 #define portINITIAL_CONTROL_IF_UNPRIVILEGED             ( 0x03 )\r
 130 #define portINITIAL_CONTROL_IF_PRIVILEGED               ( 0x02 )\r
 131 \r
 132 /* Constants required to check the validity of an interrupt priority. */\r
 133 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
 134 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
 135 #define portAIRCR_REG                                           ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
 136 #define portMAX_8_BIT_VALUE                                     ( ( uint8_t ) 0xff )\r
 137 #define portTOP_BIT_OF_BYTE                                     ( ( uint8_t ) 0x80 )\r
 138 #define portMAX_PRIGROUP_BITS                           ( ( uint8_t ) 7 )\r
 139 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
 140 #define portPRIGROUP_SHIFT                                      ( 8UL )\r
 141 \r
 142 /* Offsets in the stack to the parameters when inside the SVC handler. */\r
 143 #define portOFFSET_TO_PC                                                ( 6 )\r
 144 \r
 145 /* For strict compliance with the Cortex-M spec the task start address should\r
 146 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\r
 147 #define portSTART_ADDRESS_MASK                          ( ( StackType_t ) 0xfffffffeUL )\r
 148 \r
 149 /* Each task maintains its own interrupt status in the critical nesting\r
 150 variable.  Note this is not saved as part of the task context as context\r
 151 switches can only occur when uxCriticalNesting is zero. */\r
 152 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
 153 \r
 154 /*\r
 155  * Setup the timer to generate the tick interrupts.\r
 156  */\r
 157 static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
 158 \r
 159 /*\r
 160  * Configure a number of standard MPU regions that are used by all tasks.\r
 161  */\r
 162 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
 163 \r
 164 /*\r
 165  * Return the smallest MPU region size that a given number of bytes will fit\r
 166  * into.  The region size is returned as the value that should be programmed\r
 167  * into the region attribute register for that region.\r
 168  */\r
 169 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
 170 \r
 171 /*\r
 172  * Checks to see if being called from the context of an unprivileged task, and\r
 173  * if so raises the privilege level and returns false - otherwise does nothing\r
 174  * other than return true.\r
 175  */\r
 176 BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));\r
 177 \r
 178 /*\r
 179  * Standard FreeRTOS exception handlers.\r
 180  */\r
 181 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 182 void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;\r
 183 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 184 \r
 185 /*\r
 186  * Starts the scheduler by restoring the context of the first task to run.\r
 187  */\r
 188 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
 189 \r
 190 /*\r
 191  * C portion of the SVC handler.  The SVC handler is split between an asm entry\r
 192  * and a C wrapper for simplicity of coding and maintenance.\r
 193  */\r
 194 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
 195 \r
 196 /*\r
 197  * Function to enable the VFP.\r
 198  */\r
 199  static void vPortEnableVFP( void ) __attribute__ (( naked ));\r
 200 \r
 201 /*\r
 202  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
 203  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 204  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 205  */\r
 206 #if ( configASSERT_DEFINED == 1 )\r
 207          static uint8_t ucMaxSysCallPriority = 0;\r
 208          static uint32_t ulMaxPRIGROUPValue = 0;\r
 209          static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 210 #endif /* configASSERT_DEFINED */\r
 211 \r
 212 /*-----------------------------------------------------------*/\r
 213 \r
 214 /*\r
 215  * See header file for description.\r
 216  */\r
 217 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )\r
 218 {\r
 219         /* Simulate the stack frame as it would be created by a context switch\r
 220         interrupt. */\r
 221         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 222         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 223         pxTopOfStack--;\r
 224         *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;    /* PC */\r
 225         pxTopOfStack--;\r
 226         *pxTopOfStack = 0;      /* LR */\r
 227         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 228         *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
 229 \r
 230         /* A save method is being used that requires each task to maintain its\r
 231         own exec return value. */\r
 232         pxTopOfStack--;\r
 233         *pxTopOfStack = portINITIAL_EXEC_RETURN;\r
 234 \r
 235         pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 236 \r
 237         if( xRunPrivileged == pdTRUE )\r
 238         {\r
 239                 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\r
 240         }\r
 241         else\r
 242         {\r
 243                 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\r
 244         }\r
 245 \r
 246         return pxTopOfStack;\r
 247 }\r
 248 /*-----------------------------------------------------------*/\r
 249 \r
 250 void vPortSVCHandler( void )\r
 251 {\r
 252         /* Assumes psp was in use. */\r
 253         __asm volatile\r
 254         (\r
 255                 #ifndef USE_PROCESS_STACK       /* Code should not be required if a main() is using the process stack. */\r
 256                         "       tst lr, #4                                              \n"\r
 257                         "       ite eq                                                  \n"\r
 258                         "       mrseq r0, msp                                   \n"\r
 259                         "       mrsne r0, psp                                   \n"\r
 260                 #else\r
 261                         "       mrs r0, psp                                             \n"\r
 262                 #endif\r
 263                         "       b %0                                                    \n"\r
 264                         ::"i"(prvSVCHandler):"r0"\r
 265         );\r
 266 }\r
 267 /*-----------------------------------------------------------*/\r
 268 \r
 269 static void prvSVCHandler(      uint32_t *pulParam )\r
 270 {\r
 271 uint8_t ucSVCNumber;\r
 272 \r
 273         /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and\r
 274         xPSR.  The first argument (r0) is pulParam[ 0 ]. */\r
 275         ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];\r
 276         switch( ucSVCNumber )\r
 277         {\r
 278                 case portSVC_START_SCHEDULER    :       portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;\r
 279                                                                                         prvRestoreContextOfFirstTask();\r
 280                                                                                         break;\r
 281 \r
 282                 case portSVC_YIELD                              :       portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 283                                                                                         /* Barriers are normally not required\r
 284                                                                                         but do ensure the code is completely\r
 285                                                                                         within the specified behaviour for the\r
 286                                                                                         architecture. */\r
 287                                                                                         __asm volatile( "dsb" );\r
 288                                                                                         __asm volatile( "isb" );\r
 289 \r
 290                                                                                         break;\r
 291 \r
 292                 case portSVC_RAISE_PRIVILEGE    :       __asm volatile\r
 293                                                                                         (\r
 294                                                                                                 "       mrs r1, control         \n" /* Obtain current control value. */\r
 295                                                                                                 "       bic r1, #1                      \n" /* Set privilege bit. */\r
 296                                                                                                 "       msr control, r1         \n" /* Write back new control value. */\r
 297                                                                                                 :::"r1"\r
 298                                                                                         );\r
 299                                                                                         break;\r
 300 \r
 301                 default                                                 :       /* Unknown SVC call. */\r
 302                                                                                         break;\r
 303         }\r
 304 }\r
 305 /*-----------------------------------------------------------*/\r
 306 \r
 307 static void prvRestoreContextOfFirstTask( void )\r
 308 {\r
 309         __asm volatile\r
 310         (\r
 311                 "       ldr r0, =0xE000ED08                             \n" /* Use the NVIC offset register to locate the stack. */\r
 312                 "       ldr r0, [r0]                                    \n"\r
 313                 "       ldr r0, [r0]                                    \n"\r
 314                 "       msr msp, r0                                             \n" /* Set the msp back to the start of the stack. */\r
 315                 "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 316                 "       ldr r1, [r3]                                    \n"\r
 317                 "       ldr r0, [r1]                                    \n" /* The first item in the TCB is the task top of stack. */\r
 318                 "       add r1, r1, #4                                  \n" /* Move onto the second item in the TCB... */\r
 319                 "       ldr r2, =0xe000ed9c                             \n" /* Region Base Address register. */\r
 320                 "       ldmia r1!, {r4-r11}                             \n" /* Read 4 sets of MPU registers. */\r
 321                 "       stmia r2!, {r4-r11}                             \n" /* Write 4 sets of MPU registers. */\r
 322                 "       ldmia r0!, {r3-r11, r14}                \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 323                 "       msr control, r3                                 \n"\r
 324                 "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 325                 "       mov r0, #0                                              \n"\r
 326                 "       msr     basepri, r0                                     \n"\r
 327                 "       bx r14                                                  \n"\r
 328                 "                                                                       \n"\r
 329                 "       .align 4                                                \n"\r
 330                 "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
 331         );\r
 332 }\r
 333 /*-----------------------------------------------------------*/\r
 334 \r
 335 /*\r
 336  * See header file for description.\r
 337  */\r
 338 BaseType_t xPortStartScheduler( void )\r
 339 {\r
 340         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See\r
 341         http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 342         configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\r
 343 \r
 344         #if( configASSERT_DEFINED == 1 )\r
 345         {\r
 346                 volatile uint32_t ulOriginalPriority;\r
 347                 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 348                 volatile uint8_t ucMaxPriorityValue;\r
 349 \r
 350                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 351                 functions can be called.  ISR safe functions are those that end in\r
 352                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 353                 ensure interrupt entry is as fast and simple as possible.\r
 354 \r
 355                 Save the interrupt priority value that is about to be clobbered. */\r
 356                 ulOriginalPriority = *pucFirstUserPriorityRegister;\r
 357 \r
 358                 /* Determine the number of priority bits available.  First write to all\r
 359                 possible bits. */\r
 360                 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
 361 \r
 362                 /* Read the value back to see how many bits stuck. */\r
 363                 ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
 364 \r
 365                 /* Use the same mask on the maximum system call priority. */\r
 366                 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
 367 \r
 368                 /* Calculate the maximum acceptable priority group value for the number\r
 369                 of bits read back. */\r
 370                 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
 371                 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
 372                 {\r
 373                         ulMaxPRIGROUPValue--;\r
 374                         ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
 375                 }\r
 376 \r
 377                 /* Shift the priority group value back to its position within the AIRCR\r
 378                 register. */\r
 379                 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
 380                 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
 381 \r
 382                 /* Restore the clobbered interrupt priority register to its original\r
 383                 value. */\r
 384                 *pucFirstUserPriorityRegister = ulOriginalPriority;\r
 385         }\r
 386         #endif /* conifgASSERT_DEFINED */\r
 387 \r
 388         /* Make PendSV and SysTick the same priority as the kernel, and the SVC\r
 389         handler higher priority so it can be used to exit a critical section (where\r
 390         lower priorities are masked). */\r
 391         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 392         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 393 \r
 394         /* Configure the regions in the MPU that are common to all tasks. */\r
 395         prvSetupMPU();\r
 396 \r
 397         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 398         here already. */\r
 399         prvSetupTimerInterrupt();\r
 400 \r
 401         /* Initialise the critical nesting count ready for the first task. */\r
 402         uxCriticalNesting = 0;\r
 403 \r
 404         /* Ensure the VFP is enabled - it should be anyway. */\r
 405         vPortEnableVFP();\r
 406 \r
 407         /* Lazy save always. */\r
 408         *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
 409 \r
 410         /* Start the first task. */\r
 411         __asm volatile(\r
 412                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 413                                         " ldr r0, [r0]                  \n"\r
 414                                         " ldr r0, [r0]                  \n"\r
 415                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 416                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 417                                         " cpsie f                               \n"\r
 418                                         " dsb                                   \n"\r
 419                                         " isb                                   \n"\r
 420                                         " svc %0                                \n" /* System call to start first task. */\r
 421                                         " nop                                   \n"\r
 422                                         :: "i" (portSVC_START_SCHEDULER) );\r
 423 \r
 424         /* Should not get here! */\r
 425         return 0;\r
 426 }\r
 427 /*-----------------------------------------------------------*/\r
 428 \r
 429 void vPortEndScheduler( void )\r
 430 {\r
 431         /* Not implemented in ports where there is nothing to return to.\r
 432         Artificially force an assert. */\r
 433         configASSERT( uxCriticalNesting == 1000UL );\r
 434 }\r
 435 /*-----------------------------------------------------------*/\r
 436 \r
 437 void vPortEnterCritical( void )\r
 438 {\r
 439 BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
 440 \r
 441         portDISABLE_INTERRUPTS();\r
 442         uxCriticalNesting++;\r
 443 \r
 444         vPortResetPrivilege( xRunningPrivileged );\r
 445 }\r
 446 /*-----------------------------------------------------------*/\r
 447 \r
 448 void vPortExitCritical( void )\r
 449 {\r
 450 BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
 451 \r
 452         configASSERT( uxCriticalNesting );\r
 453         uxCriticalNesting--;\r
 454         if( uxCriticalNesting == 0 )\r
 455         {\r
 456                 portENABLE_INTERRUPTS();\r
 457         }\r
 458         vPortResetPrivilege( xRunningPrivileged );\r
 459 }\r
 460 /*-----------------------------------------------------------*/\r
 461 \r
 462 void xPortPendSVHandler( void )\r
 463 {\r
 464         /* This is a naked function. */\r
 465 \r
 466         __asm volatile\r
 467         (\r
 468                 "       mrs r0, psp                                                     \n"\r
 469                 "                                                                               \n"\r
 470                 "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 471                 "       ldr     r2, [r3]                                                \n"\r
 472                 "                                                                               \n"\r
 473                 "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, push high vfp registers. */\r
 474                 "       it eq                                                           \n"\r
 475                 "       vstmdbeq r0!, {s16-s31}                         \n"\r
 476                 "                                                                               \n"\r
 477                 "       mrs r1, control                                         \n"\r
 478                 "       stmdb r0!, {r1, r4-r11, r14}            \n" /* Save the remaining registers. */\r
 479                 "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 480                 "       clrex                                                           \n" /* Ensure thread safety of atomic operations. */\r
 481                 "                                                                               \n"\r
 482                 "       stmdb sp!, {r3}                                         \n"\r
 483                 "       mov r0, %0                                                      \n"\r
 484                 "       msr basepri, r0                                         \n"\r
 485                 "       dsb                                                                     \n"\r
 486                 "       isb                                                                     \n"\r
 487                 "       bl vTaskSwitchContext                           \n"\r
 488                 "       mov r0, #0                                                      \n"\r
 489                 "       msr basepri, r0                                         \n"\r
 490                 "       ldmia sp!, {r3}                                         \n"\r
 491                 "                                                                               \n"     /* Restore the context. */\r
 492                 "       ldr r1, [r3]                                            \n"\r
 493                 "       ldr r0, [r1]                                            \n" /* The first item in the TCB is the task top of stack. */\r
 494                 "       add r1, r1, #4                                          \n" /* Move onto the second item in the TCB... */\r
 495                 "       ldr r2, =0xe000ed9c                                     \n" /* Region Base Address register. */\r
 496                 "       ldmia r1!, {r4-r11}                                     \n" /* Read 4 sets of MPU registers. */\r
 497                 "       stmia r2!, {r4-r11}                                     \n" /* Write 4 sets of MPU registers. */\r
 498                 "       ldmia r0!, {r3-r11, r14}                        \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 499                 "       msr control, r3                                         \n"\r
 500                 "                                                                               \n"\r
 501                 "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\r
 502                 "       it eq                                                           \n"\r
 503                 "       vldmiaeq r0!, {s16-s31}                         \n"\r
 504                 "                                                                               \n"\r
 505                 "       msr psp, r0                                                     \n"\r
 506                 "       bx r14                                                          \n"\r
 507                 "                                                                               \n"\r
 508                 "       .align 4                                                        \n"\r
 509                 "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 510                 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 511         );\r
 512 }\r
 513 /*-----------------------------------------------------------*/\r
 514 \r
 515 void xPortSysTickHandler( void )\r
 516 {\r
 517 uint32_t ulDummy;\r
 518 \r
 519         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
 520         {\r
 521                 /* Increment the RTOS tick. */\r
 522                 if( xTaskIncrementTick() != pdFALSE )\r
 523                 {\r
 524                         /* Pend a context switch. */\r
 525                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 526                 }\r
 527         }\r
 528         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
 529 }\r
 530 /*-----------------------------------------------------------*/\r
 531 \r
 532 /*\r
 533  * Setup the systick timer to generate the tick interrupts at the required\r
 534  * frequency.\r
 535  */\r
 536 static void prvSetupTimerInterrupt( void )\r
 537 {\r
 538         /* Clear the SysTick. */\r
 539         portNVIC_SYSTICK_CTRL_REG = 0UL;\r
 540         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 541 \r
 542         /* Configure SysTick to interrupt at the requested rate. */\r
 543         portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 544         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
 545 }\r
 546 /*-----------------------------------------------------------*/\r
 547 \r
 548 /* This is a naked function. */\r
 549 static void vPortEnableVFP( void )\r
 550 {\r
 551         __asm volatile\r
 552         (\r
 553                 "       ldr.w r0, =0xE000ED88           \n" /* The FPU enable bits are in the CPACR. */\r
 554                 "       ldr r1, [r0]                            \n"\r
 555                 "                                                               \n"\r
 556                 "       orr r1, r1, #( 0xf << 20 )      \n" /* Enable CP10 and CP11 coprocessors, then save back. */\r
 557                 "       str r1, [r0]                            \n"\r
 558                 "       bx r14                                          "\r
 559         );\r
 560 }\r
 561 /*-----------------------------------------------------------*/\r
 562 \r
 563 static void prvSetupMPU( void )\r
 564 {\r
 565 extern uint32_t __privileged_functions_end__[];\r
 566 extern uint32_t __FLASH_segment_start__[];\r
 567 extern uint32_t __FLASH_segment_end__[];\r
 568 extern uint32_t __privileged_data_start__[];\r
 569 extern uint32_t __privileged_data_end__[];\r
 570 \r
 571         /* Check the expected MPU is present. */\r
 572         if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
 573         {\r
 574                 /* First setup the entire flash for unprivileged read only access. */\r
 575                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 576                                                                                         ( portMPU_REGION_VALID ) |\r
 577                                                                                         ( portUNPRIVILEGED_FLASH_REGION );\r
 578 \r
 579                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_ONLY ) |\r
 580                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 581                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 582                                                                                 ( portMPU_REGION_ENABLE );\r
 583 \r
 584                 /* Setup the first 16K for privileged only access (even though less\r
 585                 than 10K is actually being used).  This is where the kernel code is\r
 586                 placed. */\r
 587                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 588                                                                                         ( portMPU_REGION_VALID ) |\r
 589                                                                                         ( portPRIVILEGED_FLASH_REGION );\r
 590 \r
 591                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
 592                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 593                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 594                                                                                 ( portMPU_REGION_ENABLE );\r
 595 \r
 596                 /* Setup the privileged data RAM region.  This is where the kernel data\r
 597                 is placed. */\r
 598                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 599                                                                                         ( portMPU_REGION_VALID ) |\r
 600                                                                                         ( portPRIVILEGED_RAM_REGION );\r
 601 \r
 602                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 603                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 604                                                                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 605                                                                                 ( portMPU_REGION_ENABLE );\r
 606 \r
 607                 /* By default allow everything to access the general peripherals.  The\r
 608                 system peripherals and registers are protected. */\r
 609                 portMPU_REGION_BASE_ADDRESS_REG =       ( portPERIPHERALS_START_ADDRESS ) |\r
 610                                                                                         ( portMPU_REGION_VALID ) |\r
 611                                                                                         ( portGENERAL_PERIPHERALS_REGION );\r
 612 \r
 613                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
 614                                                                                 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\r
 615                                                                                 ( portMPU_REGION_ENABLE );\r
 616 \r
 617                 /* Enable the memory fault exception. */\r
 618                 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;\r
 619 \r
 620                 /* Enable the MPU with the background region configured. */\r
 621                 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
 622         }\r
 623 }\r
 624 /*-----------------------------------------------------------*/\r
 625 \r
 626 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )\r
 627 {\r
 628 uint32_t ulRegionSize, ulReturnValue = 4;\r
 629 \r
 630         /* 32 is the smallest region size, 31 is the largest valid value for\r
 631         ulReturnValue. */\r
 632         for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\r
 633         {\r
 634                 if( ulActualSizeInBytes <= ulRegionSize )\r
 635                 {\r
 636                         break;\r
 637                 }\r
 638                 else\r
 639                 {\r
 640                         ulReturnValue++;\r
 641                 }\r
 642         }\r
 643 \r
 644         /* Shift the code by one before returning so it can be written directly\r
 645         into the the correct bit position of the attribute register. */\r
 646         return ( ulReturnValue << 1UL );\r
 647 }\r
 648 /*-----------------------------------------------------------*/\r
 649 \r
 650 BaseType_t xPortRaisePrivilege( void )\r
 651 {\r
 652         __asm volatile\r
 653         (\r
 654                 "       mrs r0, control                                         \n"\r
 655                 "       tst r0, #1                                                      \n" /* Is the task running privileged? */\r
 656                 "       itte ne                                                         \n"\r
 657                 "       movne r0, #0                                            \n" /* CONTROL[0]!=0, return false. */\r
 658                 "       svcne %0                                                        \n" /* Switch to privileged. */\r
 659                 "       moveq r0, #1                                            \n" /* CONTROL[0]==0, return true. */\r
 660                 "       bx lr                                                           \n"\r
 661                 :: "i" (portSVC_RAISE_PRIVILEGE) : "r0"\r
 662         );\r
 663 \r
 664         return 0;\r
 665 }\r
 666 /*-----------------------------------------------------------*/\r
 667 \r
 668 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
 669 {\r
 670 extern uint32_t __SRAM_segment_start__[];\r
 671 extern uint32_t __SRAM_segment_end__[];\r
 672 extern uint32_t __privileged_data_start__[];\r
 673 extern uint32_t __privileged_data_end__[];\r
 674 int32_t lIndex;\r
 675 uint32_t ul;\r
 676 \r
 677         if( xRegions == NULL )\r
 678         {\r
 679                 /* No MPU regions are specified so allow access to all RAM. */\r
 680                 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 681                                 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */\r
 682                                 ( portMPU_REGION_VALID ) |\r
 683                                 ( portSTACK_REGION );\r
 684 \r
 685                 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 686                                 ( portMPU_REGION_READ_WRITE ) |\r
 687                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 688                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |\r
 689                                 ( portMPU_REGION_ENABLE );\r
 690 \r
 691                 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
 692                 just removed the privileged only parameters. */\r
 693                 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =\r
 694                                 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 695                                 ( portMPU_REGION_VALID ) |\r
 696                                 ( portSTACK_REGION + 1 );\r
 697 \r
 698                 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =\r
 699                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 700                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 701                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 702                                 ( portMPU_REGION_ENABLE );\r
 703 \r
 704                 /* Invalidate all other regions. */\r
 705                 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 706                 {\r
 707                         xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 708                         xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 709                 }\r
 710         }\r
 711         else\r
 712         {\r
 713                 /* This function is called automatically when the task is created - in\r
 714                 which case the stack region parameters will be valid.  At all other\r
 715                 times the stack parameters will not be valid and it is assumed that the\r
 716                 stack region has already been configured. */\r
 717                 if( ulStackDepth > 0 )\r
 718                 {\r
 719                         /* Define the region that allows access to the stack. */\r
 720                         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 721                                         ( ( uint32_t ) pxBottomOfStack ) |\r
 722                                         ( portMPU_REGION_VALID ) |\r
 723                                         ( portSTACK_REGION ); /* Region number. */\r
 724 \r
 725                         xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 726                                         ( portMPU_REGION_READ_WRITE ) | /* Read and write. */\r
 727                                         ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |\r
 728                                         ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 729                                         ( portMPU_REGION_ENABLE );\r
 730                 }\r
 731 \r
 732                 lIndex = 0;\r
 733 \r
 734                 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 735                 {\r
 736                         if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\r
 737                         {\r
 738                                 /* Translate the generic region definition contained in\r
 739                                 xRegions into the CM3 specific MPU settings that are then\r
 740                                 stored in xMPUSettings. */\r
 741                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\r
 742                                                 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |\r
 743                                                 ( portMPU_REGION_VALID ) |\r
 744                                                 ( portSTACK_REGION + ul ); /* Region number. */\r
 745 \r
 746                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute =\r
 747                                                 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\r
 748                                                 ( xRegions[ lIndex ].ulParameters ) |\r
 749                                                 ( portMPU_REGION_ENABLE );\r
 750                         }\r
 751                         else\r
 752                         {\r
 753                                 /* Invalidate the region. */\r
 754                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 755                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 756                         }\r
 757 \r
 758                         lIndex++;\r
 759                 }\r
 760         }\r
 761 }\r
 762 /*-----------------------------------------------------------*/\r
 763 \r
 764 #if( configASSERT_DEFINED == 1 )\r
 765 \r
 766         void vPortValidateInterruptPriority( void )\r
 767         {\r
 768         uint32_t ulCurrentInterrupt;\r
 769         uint8_t ucCurrentPriority;\r
 770 \r
 771                 /* Obtain the number of the currently executing interrupt. */\r
 772                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
 773 \r
 774                 /* Is the interrupt number a user defined interrupt? */\r
 775                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 776                 {\r
 777                         /* Look up the interrupt's priority. */\r
 778                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 779 \r
 780                         /* The following assertion will fail if a service routine (ISR) for\r
 781                         an interrupt that has been assigned a priority above\r
 782                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 783                         function.  ISR safe FreeRTOS API functions must *only* be called\r
 784                         from interrupts that have been assigned a priority at or below\r
 785                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 786 \r
 787                         Numerically low interrupt priority numbers represent logically high\r
 788                         interrupt priorities, therefore the priority of the interrupt must\r
 789                         be set to a value equal to or numerically *higher* than\r
 790                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 791 \r
 792                         Interrupts that use the FreeRTOS API must not be left at their\r
 793                         default priority of     zero as that is the highest possible priority,\r
 794                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
 795                         and     therefore also guaranteed to be invalid.\r
 796 \r
 797                         FreeRTOS maintains separate thread and ISR API functions to ensure\r
 798                         interrupt entry is as fast and simple as possible.\r
 799 \r
 800                         The following links provide detailed information:\r
 801                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 802                         http://www.freertos.org/FAQHelp.html */\r
 803                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 804                 }\r
 805 \r
 806                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits\r
 807                 that define each interrupt's priority to be split between bits that\r
 808                 define the interrupt's pre-emption priority bits and bits that define\r
 809                 the interrupt's sub-priority.  For simplicity all bits must be defined\r
 810                 to be pre-emption priority bits.  The following assertion will fail if\r
 811                 this is not the case (if some bits represent a sub-priority).\r
 812 \r
 813                 If the application only uses CMSIS libraries for interrupt\r
 814                 configuration then the correct setting can be achieved on all Cortex-M\r
 815                 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
 816                 scheduler.  Note however that some vendor specific peripheral libraries\r
 817                 assume a non-zero priority group setting, in which cases using a value\r
 818                 of zero will result in unpredicable behaviour. */\r
 819                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
 820         }\r
 821 \r
 822 #endif /* configASSERT_DEFINED */\r
 823 /*-----------------------------------------------------------*/\r
 824 \r
 825 \r