2 * FreeRTOS Kernel V10.2.1
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /*-----------------------------------------------------------
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29 * Implementation of functions defined in portable.h for the ARM CM4F port.
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30 *----------------------------------------------------------*/
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32 /* Scheduler includes. */
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33 #include "FreeRTOS.h"
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37 #error This port can only be used when the project options are configured to enable hardware floating point support.
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40 #ifndef configSYSTICK_CLOCK_HZ
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41 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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42 /* Ensure the SysTick is clocked at the same frequency as the core. */
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43 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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45 /* The way the SysTick is clocked is not modified in case it is not the same
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47 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
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50 /* Constants required to manipulate the core. Registers first... */
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51 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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52 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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53 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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54 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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55 /* ...then bits in the registers. */
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56 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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57 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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58 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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59 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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60 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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62 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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63 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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65 /* Constants required to check the validity of an interrupt priority. */
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66 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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67 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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68 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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69 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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70 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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71 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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72 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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73 #define portPRIGROUP_SHIFT ( 8UL )
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75 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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76 #define portVECTACTIVE_MASK ( 0xFFUL )
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78 /* Constants required to manipulate the VFP. */
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79 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
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80 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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82 /* Constants required to set up the initial stack. */
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83 #define portINITIAL_XPSR ( 0x01000000 )
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84 #define portINITIAL_EXC_RETURN ( 0xfffffffd )
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86 /* The systick is a 24-bit counter. */
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87 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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89 /* For strict compliance with the Cortex-M spec the task start address should
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90 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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91 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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93 /* A fiddle factor to estimate the number of SysTick counts that would have
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94 occurred while the SysTick counter is stopped during tickless idle
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96 #define portMISSED_COUNTS_FACTOR ( 45UL )
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98 /* Let the user override the pre-loading of the initial LR with the address of
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99 prvTaskExitError() in case it messes up unwinding of the stack in the
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101 #ifdef configTASK_RETURN_ADDRESS
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102 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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104 #define portTASK_RETURN_ADDRESS prvTaskExitError
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108 * Setup the timer to generate the tick interrupts. The implementation in this
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109 * file is weak to allow application writers to change the timer used to
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110 * generate the tick interrupt.
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112 void vPortSetupTimerInterrupt( void );
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115 * Exception handlers.
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117 void xPortPendSVHandler( void ) __attribute__ (( naked ));
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118 void xPortSysTickHandler( void );
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119 void vPortSVCHandler( void ) __attribute__ (( naked ));
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122 * Start first task is a separate function so it can be tested in isolation.
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124 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
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127 * Function to enable the VFP.
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129 static void vPortEnableVFP( void ) __attribute__ (( naked ));
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132 * Used to catch tasks that attempt to return from their implementing function.
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134 static void prvTaskExitError( void );
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136 /*-----------------------------------------------------------*/
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138 /* Each task maintains its own interrupt status in the critical nesting
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140 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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143 * The number of SysTick increments that make up one tick period.
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145 #if( configUSE_TICKLESS_IDLE == 1 )
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146 static uint32_t ulTimerCountsForOneTick = 0;
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147 #endif /* configUSE_TICKLESS_IDLE */
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150 * The maximum number of tick periods that can be suppressed is limited by the
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151 * 24 bit resolution of the SysTick timer.
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153 #if( configUSE_TICKLESS_IDLE == 1 )
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154 static uint32_t xMaximumPossibleSuppressedTicks = 0;
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155 #endif /* configUSE_TICKLESS_IDLE */
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158 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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159 * power functionality only.
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161 #if( configUSE_TICKLESS_IDLE == 1 )
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162 static uint32_t ulStoppedTimerCompensation = 0;
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163 #endif /* configUSE_TICKLESS_IDLE */
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166 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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167 * FreeRTOS API functions are not called from interrupts that have been assigned
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168 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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170 #if( configASSERT_DEFINED == 1 )
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171 static uint8_t ucMaxSysCallPriority = 0;
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172 static uint32_t ulMaxPRIGROUPValue = 0;
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173 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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174 #endif /* configASSERT_DEFINED */
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176 /*-----------------------------------------------------------*/
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179 * See header file for description.
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181 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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183 /* Simulate the stack frame as it would be created by a context switch
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186 /* Offset added to account for the way the MCU uses the stack on entry/exit
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187 of interrupts, and to ensure alignment. */
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190 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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192 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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194 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
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196 /* Save code space by skipping register initialisation. */
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197 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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198 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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200 /* A save method is being used that requires each task to maintain its
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201 own exec return value. */
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203 *pxTopOfStack = portINITIAL_EXC_RETURN;
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205 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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207 return pxTopOfStack;
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209 /*-----------------------------------------------------------*/
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211 static void prvTaskExitError( void )
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213 volatile uint32_t ulDummy = 0;
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215 /* A function that implements a task must not exit or attempt to return to
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216 its caller as there is nothing to return to. If a task wants to exit it
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217 should instead call vTaskDelete( NULL ).
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219 Artificially force an assert() to be triggered if configASSERT() is
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220 defined, then stop here so application writers can catch the error. */
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221 configASSERT( uxCriticalNesting == ~0UL );
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222 portDISABLE_INTERRUPTS();
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223 while( ulDummy == 0 )
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225 /* This file calls prvTaskExitError() after the scheduler has been
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226 started to remove a compiler warning about the function being defined
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227 but never called. ulDummy is used purely to quieten other warnings
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228 about code appearing after this function is called - making ulDummy
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229 volatile makes the compiler think the function could return and
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230 therefore not output an 'unreachable code' warning for code that appears
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234 /*-----------------------------------------------------------*/
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236 void vPortSVCHandler( void )
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239 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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240 " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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241 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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242 " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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243 " msr psp, r0 \n" /* Restore the task stack pointer. */
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246 " msr basepri, r0 \n"
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250 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
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253 /*-----------------------------------------------------------*/
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255 static void prvPortStartFirstTask( void )
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257 /* Start the first task. This also clears the bit that indicates the FPU is
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258 in use in case the FPU was used before the scheduler was started - which
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259 would otherwise result in the unnecessary leaving of space in the SVC stack
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260 for lazy saving of FPU registers. */
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262 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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265 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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266 " mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */
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267 " msr control, r0 \n"
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268 " cpsie i \n" /* Globally enable interrupts. */
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272 " svc 0 \n" /* System call to start first task. */
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276 /*-----------------------------------------------------------*/
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279 * See header file for description.
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281 BaseType_t xPortStartScheduler( void )
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283 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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284 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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285 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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287 #if( configASSERT_DEFINED == 1 )
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289 volatile uint32_t ulOriginalPriority;
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290 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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291 volatile uint8_t ucMaxPriorityValue;
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293 /* Determine the maximum priority from which ISR safe FreeRTOS API
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294 functions can be called. ISR safe functions are those that end in
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295 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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296 ensure interrupt entry is as fast and simple as possible.
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298 Save the interrupt priority value that is about to be clobbered. */
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299 ulOriginalPriority = *pucFirstUserPriorityRegister;
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301 /* Determine the number of priority bits available. First write to all
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303 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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305 /* Read the value back to see how many bits stuck. */
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306 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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308 /* Use the same mask on the maximum system call priority. */
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309 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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311 /* Calculate the maximum acceptable priority group value for the number
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312 of bits read back. */
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313 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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314 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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316 ulMaxPRIGROUPValue--;
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317 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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320 #ifdef __NVIC_PRIO_BITS
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322 /* Check the CMSIS configuration that defines the number of
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323 priority bits matches the number of priority bits actually queried
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324 from the hardware. */
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325 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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329 #ifdef configPRIO_BITS
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331 /* Check the FreeRTOS configuration that defines the number of
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332 priority bits matches the number of priority bits actually queried
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333 from the hardware. */
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334 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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338 /* Shift the priority group value back to its position within the AIRCR
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340 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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341 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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343 /* Restore the clobbered interrupt priority register to its original
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345 *pucFirstUserPriorityRegister = ulOriginalPriority;
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347 #endif /* conifgASSERT_DEFINED */
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349 /* Make PendSV and SysTick the lowest priority interrupts. */
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350 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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351 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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353 /* Start the timer that generates the tick ISR. Interrupts are disabled
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355 vPortSetupTimerInterrupt();
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357 /* Initialise the critical nesting count ready for the first task. */
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358 uxCriticalNesting = 0;
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360 /* Ensure the VFP is enabled - it should be anyway. */
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363 /* Lazy save always. */
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364 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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366 /* Start the first task. */
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367 prvPortStartFirstTask();
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369 /* Should never get here as the tasks will now be executing! Call the task
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370 exit error function to prevent compiler warnings about a static function
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371 not being called in the case that the application writer overrides this
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372 functionality by defining configTASK_RETURN_ADDRESS. Call
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373 vTaskSwitchContext() so link time optimisation does not remove the
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375 vTaskSwitchContext();
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376 prvTaskExitError();
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378 /* Should not get here! */
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381 /*-----------------------------------------------------------*/
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383 void vPortEndScheduler( void )
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385 /* Not implemented in ports where there is nothing to return to.
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386 Artificially force an assert. */
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387 configASSERT( uxCriticalNesting == 1000UL );
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389 /*-----------------------------------------------------------*/
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391 void vPortEnterCritical( void )
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393 portDISABLE_INTERRUPTS();
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394 uxCriticalNesting++;
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396 /* This is not the interrupt safe version of the enter critical function so
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397 assert() if it is being called from an interrupt context. Only API
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398 functions that end in "FromISR" can be used in an interrupt. Only assert if
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399 the critical nesting count is 1 to protect against recursive calls if the
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400 assert function also uses a critical section. */
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401 if( uxCriticalNesting == 1 )
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403 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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406 /*-----------------------------------------------------------*/
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408 void vPortExitCritical( void )
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410 configASSERT( uxCriticalNesting );
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411 uxCriticalNesting--;
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412 if( uxCriticalNesting == 0 )
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414 portENABLE_INTERRUPTS();
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417 /*-----------------------------------------------------------*/
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419 void xPortPendSVHandler( void )
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421 /* This is a naked function. */
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428 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
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431 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
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433 " vstmdbeq r0!, {s16-s31} \n"
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435 " stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */
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436 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
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438 " stmdb sp!, {r0, r3} \n"
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440 " cpsid i \n" /* Errata workaround. */
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441 " msr basepri, r0 \n"
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444 " cpsie i \n" /* Errata workaround. */
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445 " bl vTaskSwitchContext \n"
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447 " msr basepri, r0 \n"
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448 " ldmia sp!, {r0, r3} \n"
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450 " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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453 " ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */
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455 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
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457 " vldmiaeq r0!, {s16-s31} \n"
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462 #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
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463 #if WORKAROUND_PMU_CM001 == 1
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472 "pxCurrentTCBConst: .word pxCurrentTCB \n"
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473 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
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476 /*-----------------------------------------------------------*/
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478 void xPortSysTickHandler( void )
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480 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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481 executes all interrupts must be unmasked. There is therefore no need to
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482 save and then restore the interrupt mask value as its value is already
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484 portDISABLE_INTERRUPTS();
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486 /* Increment the RTOS tick. */
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487 if( xTaskIncrementTick() != pdFALSE )
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489 /* A context switch is required. Context switching is performed in
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490 the PendSV interrupt. Pend the PendSV interrupt. */
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491 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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494 portENABLE_INTERRUPTS();
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496 /*-----------------------------------------------------------*/
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498 #if( configUSE_TICKLESS_IDLE == 1 )
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500 __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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502 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
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503 TickType_t xModifiableIdleTime;
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505 /* Make sure the SysTick reload value does not overflow the counter. */
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506 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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508 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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511 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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512 is accounted for as best it can be, but using the tickless mode will
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513 inevitably result in some tiny drift of the time maintained by the
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514 kernel with respect to calendar time. */
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515 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
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517 /* Calculate the reload value required to wait xExpectedIdleTime
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518 tick periods. -1 is used because this code will execute part way
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519 through one of the tick periods. */
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520 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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521 if( ulReloadValue > ulStoppedTimerCompensation )
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523 ulReloadValue -= ulStoppedTimerCompensation;
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526 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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527 method as that will mask interrupts that should exit sleep mode. */
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528 __asm volatile( "cpsid i" ::: "memory" );
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529 __asm volatile( "dsb" );
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530 __asm volatile( "isb" );
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532 /* If a context switch is pending or a task is waiting for the scheduler
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533 to be unsuspended then abandon the low power entry. */
\r
534 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
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536 /* Restart from whatever is left in the count register to complete
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537 this tick period. */
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538 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
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540 /* Restart SysTick. */
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541 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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543 /* Reset the reload register to the value required for normal tick
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545 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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547 /* Re-enable interrupts - see comments above the cpsid instruction()
\r
549 __asm volatile( "cpsie i" ::: "memory" );
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553 /* Set the new reload value. */
\r
554 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
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556 /* Clear the SysTick count flag and set the count value back to
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558 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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560 /* Restart SysTick. */
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561 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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563 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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564 set its parameter to 0 to indicate that its implementation contains
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565 its own wait for interrupt or wait for event instruction, and so wfi
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566 should not be executed again. However, the original expected idle
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567 time variable must remain unmodified, so a copy is taken. */
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568 xModifiableIdleTime = xExpectedIdleTime;
\r
569 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
\r
570 if( xModifiableIdleTime > 0 )
\r
572 __asm volatile( "dsb" ::: "memory" );
\r
573 __asm volatile( "wfi" );
\r
574 __asm volatile( "isb" );
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576 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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578 /* Re-enable interrupts to allow the interrupt that brought the MCU
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579 out of sleep mode to execute immediately. see comments above
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580 __disable_interrupt() call above. */
\r
581 __asm volatile( "cpsie i" ::: "memory" );
\r
582 __asm volatile( "dsb" );
\r
583 __asm volatile( "isb" );
\r
585 /* Disable interrupts again because the clock is about to be stopped
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586 and interrupts that execute while the clock is stopped will increase
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587 any slippage between the time maintained by the RTOS and calendar
\r
589 __asm volatile( "cpsid i" ::: "memory" );
\r
590 __asm volatile( "dsb" );
\r
591 __asm volatile( "isb" );
\r
593 /* Disable the SysTick clock without reading the
\r
594 portNVIC_SYSTICK_CTRL_REG register to ensure the
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595 portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
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596 the time the SysTick is stopped for is accounted for as best it can
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597 be, but using the tickless mode will inevitably result in some tiny
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598 drift of the time maintained by the kernel with respect to calendar
\r
600 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
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602 /* Determine if the SysTick clock has already counted to zero and
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603 been set back to the current reload value (the reload back being
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604 correct for the entire expected idle time) or if the SysTick is yet
\r
605 to count to zero (in which case an interrupt other than the SysTick
\r
606 must have brought the system out of sleep mode). */
\r
607 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
\r
609 uint32_t ulCalculatedLoadValue;
\r
611 /* The tick interrupt is already pending, and the SysTick count
\r
612 reloaded with ulReloadValue. Reset the
\r
613 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
\r
615 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
\r
617 /* Don't allow a tiny value, or values that have somehow
\r
618 underflowed because the post sleep hook did something
\r
619 that took too long. */
\r
620 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
622 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
\r
625 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
\r
627 /* As the pending tick will be processed as soon as this
\r
628 function exits, the tick value maintained by the tick is stepped
\r
629 forward by one less than the time spent waiting. */
\r
630 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
634 /* Something other than the tick interrupt ended the sleep.
\r
635 Work out how long the sleep lasted rounded to complete tick
\r
636 periods (not the ulReload value which accounted for part
\r
638 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
640 /* How many complete tick periods passed while the processor
\r
642 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
\r
644 /* The reload value is set to whatever fraction of a single tick
\r
646 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
\r
649 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
\r
650 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
\r
652 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
653 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
654 vTaskStepTick( ulCompleteTickPeriods );
\r
655 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
657 /* Exit with interrpts enabled. */
\r
658 __asm volatile( "cpsie i" ::: "memory" );
\r
662 #endif /* #if configUSE_TICKLESS_IDLE */
\r
663 /*-----------------------------------------------------------*/
\r
666 * Setup the systick timer to generate the tick interrupts at the required
\r
669 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
\r
671 /* Calculate the constants required to configure the tick interrupt. */
\r
672 #if( configUSE_TICKLESS_IDLE == 1 )
\r
674 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
675 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
676 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
678 #endif /* configUSE_TICKLESS_IDLE */
\r
680 /* Stop and clear the SysTick. */
\r
681 portNVIC_SYSTICK_CTRL_REG = 0UL;
\r
682 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
684 /* Configure SysTick to interrupt at the requested rate. */
\r
685 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
\r
686 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
\r
688 /*-----------------------------------------------------------*/
\r
690 /* This is a naked function. */
\r
691 static void vPortEnableVFP( void )
\r
695 " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
\r
698 " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
\r
703 /*-----------------------------------------------------------*/
\r
705 #if( configASSERT_DEFINED == 1 )
\r
707 void vPortValidateInterruptPriority( void )
\r
709 uint32_t ulCurrentInterrupt;
\r
710 uint8_t ucCurrentPriority;
\r
712 /* Obtain the number of the currently executing interrupt. */
\r
713 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
\r
715 /* Is the interrupt number a user defined interrupt? */
\r
716 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
718 /* Look up the interrupt's priority. */
\r
719 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
721 /* The following assertion will fail if a service routine (ISR) for
\r
722 an interrupt that has been assigned a priority above
\r
723 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
724 function. ISR safe FreeRTOS API functions must *only* be called
\r
725 from interrupts that have been assigned a priority at or below
\r
726 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
728 Numerically low interrupt priority numbers represent logically high
\r
729 interrupt priorities, therefore the priority of the interrupt must
\r
730 be set to a value equal to or numerically *higher* than
\r
731 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
733 Interrupts that use the FreeRTOS API must not be left at their
\r
734 default priority of zero as that is the highest possible priority,
\r
735 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
736 and therefore also guaranteed to be invalid.
\r
738 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
739 interrupt entry is as fast and simple as possible.
\r
741 The following links provide detailed information:
\r
742 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
743 http://www.freertos.org/FAQHelp.html */
\r
744 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
747 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
748 that define each interrupt's priority to be split between bits that
\r
749 define the interrupt's pre-emption priority bits and bits that define
\r
750 the interrupt's sub-priority. For simplicity all bits must be defined
\r
751 to be pre-emption priority bits. The following assertion will fail if
\r
752 this is not the case (if some bits represent a sub-priority).
\r
754 If the application only uses CMSIS libraries for interrupt
\r
755 configuration then the correct setting can be achieved on all Cortex-M
\r
756 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
757 scheduler. Note however that some vendor specific peripheral libraries
\r
758 assume a non-zero priority group setting, in which cases using a value
\r
759 of zero will result in unpredictable behaviour. */
\r
760 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
763 #endif /* configASSERT_DEFINED */
\r