2 * FreeRTOS Kernel V10.2.1
\r
3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
\r
5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
\r
6 * this software and associated documentation files (the "Software"), to deal in
\r
7 * the Software without restriction, including without limitation the rights to
\r
8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
\r
9 * the Software, and to permit persons to whom the Software is furnished to do so,
\r
10 * subject to the following conditions:
\r
12 * The above copyright notice and this permission notice shall be included in all
\r
13 * copies or substantial portions of the Software.
\r
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
\r
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
\r
17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
\r
18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
\r
19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
\r
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
\r
22 * http://www.FreeRTOS.org
\r
23 * http://aws.amazon.com/freertos
\r
25 * 1 tab == 4 spaces!
\r
28 /* Standard includes. */
\r
31 /* Scheduler includes. */
\r
32 #include "FreeRTOS.h"
\r
35 #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
\r
36 #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
39 #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
\r
40 #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
43 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
\r
44 #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
47 #ifndef configSETUP_TICK_INTERRUPT
\r
48 #error configSETUP_TICK_INTERRUPT() must be defined. Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
49 #endif /* configSETUP_TICK_INTERRUPT */
\r
51 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
\r
52 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
55 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
\r
56 #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
\r
59 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
\r
60 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
\r
63 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
\r
64 /* Check the configuration. */
\r
65 #if( configMAX_PRIORITIES > 32 )
\r
66 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
\r
68 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
\r
70 /* In case security extensions are implemented. */
\r
71 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
\r
72 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
\r
75 /* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
\r
77 #ifndef configCLEAR_TICK_INTERRUPT
\r
78 #define configCLEAR_TICK_INTERRUPT()
\r
81 /* A critical section is exited when the critical section nesting count reaches
\r
83 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
\r
85 /* In all GICs 255 can be written to the priority mask register to unmask all
\r
86 (but the lowest) interrupt priority. */
\r
87 #define portUNMASK_VALUE ( 0xFFUL )
\r
89 /* Tasks are not created with a floating point context, but can be given a
\r
90 floating point context after they have been created. A variable is stored as
\r
91 part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
\r
92 does not have an FPU context, or any other value if the task does have an FPU
\r
94 #define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
\r
96 /* Constants required to setup the initial task context. */
\r
97 #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
\r
98 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
\r
99 #define portINTERRUPT_ENABLE_BIT ( 0x80UL )
\r
100 #define portTHUMB_MODE_ADDRESS ( 0x01UL )
\r
102 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
\r
104 #define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
\r
106 /* Masks all bits in the APSR other than the mode bits. */
\r
107 #define portAPSR_MODE_BITS_MASK ( 0x1F )
\r
109 /* The value of the mode bits in the APSR when the CPU is executing in user
\r
111 #define portAPSR_USER_MODE ( 0x10 )
\r
113 /* The critical section macros only mask interrupts up to an application
\r
114 determined priority level. Sometimes it is necessary to turn interrupt off in
\r
115 the CPU itself before modifying certain hardware registers. */
\r
116 #define portCPU_IRQ_DISABLE() \
\r
117 __asm volatile ( "CPSID i" ::: "memory" ); \
\r
118 __asm volatile ( "DSB" ); \
\r
119 __asm volatile ( "ISB" );
\r
121 #define portCPU_IRQ_ENABLE() \
\r
122 __asm volatile ( "CPSIE i" ::: "memory" ); \
\r
123 __asm volatile ( "DSB" ); \
\r
124 __asm volatile ( "ISB" );
\r
127 /* Macro to unmask all interrupt priorities. */
\r
128 #define portCLEAR_INTERRUPT_MASK() \
\r
130 portCPU_IRQ_DISABLE(); \
\r
131 portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
\r
132 __asm volatile ( "DSB \n" \
\r
134 portCPU_IRQ_ENABLE(); \
\r
137 #define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
\r
138 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
\r
139 #define portBIT_0_SET ( ( uint8_t ) 0x01 )
\r
141 /* Let the user override the pre-loading of the initial LR with the address of
\r
142 prvTaskExitError() in case is messes up unwinding of the stack in the
\r
144 #ifdef configTASK_RETURN_ADDRESS
\r
145 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
\r
147 #define portTASK_RETURN_ADDRESS prvTaskExitError
\r
150 /*-----------------------------------------------------------*/
\r
153 * Starts the first task executing. This function is necessarily written in
\r
154 * assembly code so is implemented in portASM.s.
\r
156 extern void vPortRestoreTaskContext( void );
\r
159 * Used to catch tasks that attempt to return from their implementing function.
\r
161 static void prvTaskExitError( void );
\r
163 /*-----------------------------------------------------------*/
\r
165 /* A variable is used to keep track of the critical section nesting. This
\r
166 variable has to be stored as part of the task context and must be initialised to
\r
167 a non zero value to ensure interrupts don't inadvertently become unmasked before
\r
168 the scheduler starts. As it is stored as part of the task context it will
\r
169 automatically be set to 0 when the first task is started. */
\r
170 volatile uint32_t ulCriticalNesting = 9999UL;
\r
172 /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
\r
173 a floating point context must be saved and restored for the task. */
\r
174 uint32_t ulPortTaskHasFPUContext = pdFALSE;
\r
176 /* Set to 1 to pend a context switch from an ISR. */
\r
177 uint32_t ulPortYieldRequired = pdFALSE;
\r
179 /* Counts the interrupt nesting depth. A context switch is only performed if
\r
180 if the nesting depth is 0. */
\r
181 uint32_t ulPortInterruptNesting = 0UL;
\r
183 /* Used in asm code. */
\r
184 __attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
\r
185 __attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
\r
186 __attribute__(( used )) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
\r
187 __attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
\r
189 /*-----------------------------------------------------------*/
\r
192 * See header file for description.
\r
194 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
\r
196 /* Setup the initial stack of the task. The stack is set exactly as
\r
197 expected by the portRESTORE_CONTEXT() macro.
\r
199 The fist real value on the stack is the status register, which is set for
\r
200 system mode, with interrupts enabled. A few NULLs are added first to ensure
\r
201 GDB does not try decoding a non-existent return address. */
\r
202 *pxTopOfStack = ( StackType_t ) NULL;
\r
204 *pxTopOfStack = ( StackType_t ) NULL;
\r
206 *pxTopOfStack = ( StackType_t ) NULL;
\r
208 *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
\r
210 if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
\r
212 /* The task will start in THUMB mode. */
\r
213 *pxTopOfStack |= portTHUMB_MODE_BIT;
\r
218 /* Next the return address, which in this case is the start of the task. */
\r
219 *pxTopOfStack = ( StackType_t ) pxCode;
\r
222 /* Next all the registers other than the stack pointer. */
\r
223 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
\r
225 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
\r
227 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
\r
229 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
\r
231 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
\r
233 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
\r
235 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
\r
237 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
\r
239 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
\r
241 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
\r
243 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
\r
245 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
\r
247 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
\r
249 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
\r
252 /* The task will start with a critical nesting count of 0 as interrupts are
\r
254 *pxTopOfStack = portNO_CRITICAL_NESTING;
\r
257 /* The task will start without a floating point context. A task that uses
\r
258 the floating point hardware must call vPortTaskUsesFPU() before executing
\r
259 any floating point instructions. */
\r
260 *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
\r
262 return pxTopOfStack;
\r
264 /*-----------------------------------------------------------*/
\r
266 static void prvTaskExitError( void )
\r
268 /* A function that implements a task must not exit or attempt to return to
\r
269 its caller as there is nothing to return to. If a task wants to exit it
\r
270 should instead call vTaskDelete( NULL ).
\r
272 Artificially force an assert() to be triggered if configASSERT() is
\r
273 defined, then stop here so application writers can catch the error. */
\r
274 configASSERT( ulPortInterruptNesting == ~0UL );
\r
275 portDISABLE_INTERRUPTS();
\r
278 /*-----------------------------------------------------------*/
\r
280 BaseType_t xPortStartScheduler( void )
\r
282 uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */
\r
284 #if( configASSERT_DEFINED == 1 )
\r
286 volatile uint32_t ulOriginalPriority;
\r
287 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
\r
288 volatile uint8_t ucMaxPriorityValue;
\r
290 /* Determine how many priority bits are implemented in the GIC.
\r
292 Save the interrupt priority value that is about to be clobbered. */
\r
293 ulOriginalPriority = *pucFirstUserPriorityRegister;
\r
295 /* Determine the number of priority bits available. First write to
\r
296 all possible bits. */
\r
297 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
\r
299 /* Read the value back to see how many bits stuck. */
\r
300 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
\r
302 /* Shift to the least significant bits. */
\r
303 while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
\r
305 ucMaxPriorityValue >>= ( uint8_t ) 0x01;
\r
307 /* If ulCycles reaches 0 then ucMaxPriorityValue must have been
\r
308 read as 0, indicating a misconfiguration. */
\r
310 if( ulCycles == 0 )
\r
316 /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
\r
318 configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
\r
320 /* Restore the clobbered interrupt priority register to its original
\r
322 *pucFirstUserPriorityRegister = ulOriginalPriority;
\r
324 #endif /* conifgASSERT_DEFINED */
\r
326 /* Only continue if the CPU is not in User mode. The CPU must be in a
\r
327 Privileged mode for the scheduler to start. */
\r
328 __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
\r
329 ulAPSR &= portAPSR_MODE_BITS_MASK;
\r
330 configASSERT( ulAPSR != portAPSR_USER_MODE );
\r
332 if( ulAPSR != portAPSR_USER_MODE )
\r
334 /* Only continue if the binary point value is set to its lowest possible
\r
335 setting. See the comments in vPortValidateInterruptPriority() below for
\r
336 more information. */
\r
337 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
\r
339 if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
\r
341 /* Interrupts are turned off in the CPU itself to ensure tick does
\r
342 not execute while the scheduler is being started. Interrupts are
\r
343 automatically turned back on in the CPU when the first task starts
\r
345 portCPU_IRQ_DISABLE();
\r
347 /* Start the timer that generates the tick ISR. */
\r
348 configSETUP_TICK_INTERRUPT();
\r
350 /* Start the first task executing. */
\r
351 vPortRestoreTaskContext();
\r
355 /* Will only get here if vTaskStartScheduler() was called with the CPU in
\r
356 a non-privileged mode or the binary point register was not set to its lowest
\r
357 possible value. prvTaskExitError() is referenced to prevent a compiler
\r
358 warning about it being defined but not referenced in the case that the user
\r
359 defines their own exit address. */
\r
360 ( void ) prvTaskExitError;
\r
363 /*-----------------------------------------------------------*/
\r
365 void vPortEndScheduler( void )
\r
367 /* Not implemented in ports where there is nothing to return to.
\r
368 Artificially force an assert. */
\r
369 configASSERT( ulCriticalNesting == 1000UL );
\r
371 /*-----------------------------------------------------------*/
\r
373 void vPortEnterCritical( void )
\r
375 /* Mask interrupts up to the max syscall interrupt priority. */
\r
376 ulPortSetInterruptMask();
\r
378 /* Now interrupts are disabled ulCriticalNesting can be accessed
\r
379 directly. Increment ulCriticalNesting to keep a count of how many times
\r
380 portENTER_CRITICAL() has been called. */
\r
381 ulCriticalNesting++;
\r
383 /* This is not the interrupt safe version of the enter critical function so
\r
384 assert() if it is being called from an interrupt context. Only API
\r
385 functions that end in "FromISR" can be used in an interrupt. Only assert if
\r
386 the critical nesting count is 1 to protect against recursive calls if the
\r
387 assert function also uses a critical section. */
\r
388 if( ulCriticalNesting == 1 )
\r
390 configASSERT( ulPortInterruptNesting == 0 );
\r
393 /*-----------------------------------------------------------*/
\r
395 void vPortExitCritical( void )
\r
397 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
\r
399 /* Decrement the nesting count as the critical section is being
\r
401 ulCriticalNesting--;
\r
403 /* If the nesting level has reached zero then all interrupt
\r
404 priorities must be re-enabled. */
\r
405 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
\r
407 /* Critical nesting has reached zero so all interrupt priorities
\r
408 should be unmasked. */
\r
409 portCLEAR_INTERRUPT_MASK();
\r
413 /*-----------------------------------------------------------*/
\r
415 void FreeRTOS_Tick_Handler( void )
\r
417 /* Set interrupt mask before altering scheduler structures. The tick
\r
418 handler runs at the lowest priority, so interrupts cannot already be masked,
\r
419 so there is no need to save and restore the current mask value. It is
\r
420 necessary to turn off interrupts in the CPU itself while the ICCPMR is being
\r
422 portCPU_IRQ_DISABLE();
\r
423 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
\r
424 __asm volatile ( "dsb \n"
\r
425 "isb \n" ::: "memory" );
\r
426 portCPU_IRQ_ENABLE();
\r
428 /* Increment the RTOS tick. */
\r
429 if( xTaskIncrementTick() != pdFALSE )
\r
431 ulPortYieldRequired = pdTRUE;
\r
434 /* Ensure all interrupt priorities are active again. */
\r
435 portCLEAR_INTERRUPT_MASK();
\r
436 configCLEAR_TICK_INTERRUPT();
\r
438 /*-----------------------------------------------------------*/
\r
440 void vPortTaskUsesFPU( void )
\r
442 uint32_t ulInitialFPSCR = 0;
\r
444 /* A task is registering the fact that it needs an FPU context. Set the
\r
445 FPU flag (which is saved as part of the task context). */
\r
446 ulPortTaskHasFPUContext = pdTRUE;
\r
448 /* Initialise the floating point status register. */
\r
449 __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
\r
451 /*-----------------------------------------------------------*/
\r
453 void vPortClearInterruptMask( uint32_t ulNewMaskValue )
\r
455 if( ulNewMaskValue == pdFALSE )
\r
457 portCLEAR_INTERRUPT_MASK();
\r
460 /*-----------------------------------------------------------*/
\r
462 uint32_t ulPortSetInterruptMask( void )
\r
466 /* Interrupt in the CPU must be turned off while the ICCPMR is being
\r
468 portCPU_IRQ_DISABLE();
\r
469 if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
\r
471 /* Interrupts were already masked. */
\r
476 ulReturn = pdFALSE;
\r
477 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
\r
478 __asm volatile ( "dsb \n"
\r
479 "isb \n" ::: "memory" );
\r
481 portCPU_IRQ_ENABLE();
\r
485 /*-----------------------------------------------------------*/
\r
487 #if( configASSERT_DEFINED == 1 )
\r
489 void vPortValidateInterruptPriority( void )
\r
491 /* The following assertion will fail if a service routine (ISR) for
\r
492 an interrupt that has been assigned a priority above
\r
493 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
494 function. ISR safe FreeRTOS API functions must *only* be called
\r
495 from interrupts that have been assigned a priority at or below
\r
496 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
498 Numerically low interrupt priority numbers represent logically high
\r
499 interrupt priorities, therefore the priority of the interrupt must
\r
500 be set to a value equal to or numerically *higher* than
\r
501 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
503 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
504 interrupt entry is as fast and simple as possible. */
\r
506 configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
\r
508 /* Priority grouping: The interrupt controller (GIC) allows the bits
\r
509 that define each interrupt's priority to be split between bits that
\r
510 define the interrupt's pre-emption priority bits and bits that define
\r
511 the interrupt's sub-priority. For simplicity all bits must be defined
\r
512 to be pre-emption priority bits. The following assertion will fail if
\r
513 this is not the case (if some bits represent a sub-priority).
\r
515 The priority grouping is configured by the GIC's binary point register
\r
516 (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest
\r
517 possible value (which may be above 0). */
\r
518 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
\r
521 #endif /* configASSERT_DEFINED */
\r
522 /*-----------------------------------------------------------*/
\r