2 FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.
\r
5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
7 This file is part of the FreeRTOS distribution.
\r
9 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
10 the terms of the GNU General Public License (version 2) as published by the
\r
11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
\r
13 ***************************************************************************
\r
14 >>! NOTE: The modification to the GPL is included to allow you to !<<
\r
15 >>! distribute a combined work that includes FreeRTOS without being !<<
\r
16 >>! obliged to provide the source code for proprietary components !<<
\r
17 >>! outside of the FreeRTOS kernel. !<<
\r
18 ***************************************************************************
\r
20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
\r
23 link: http://www.freertos.org/a00114.html
\r
25 ***************************************************************************
\r
27 * FreeRTOS provides completely free yet professionally developed, *
\r
28 * robust, strictly quality controlled, supported, and cross *
\r
29 * platform software that is more than just the market leader, it *
\r
30 * is the industry's de facto standard. *
\r
32 * Help yourself get started quickly while simultaneously helping *
\r
33 * to support the FreeRTOS project by purchasing a FreeRTOS *
\r
34 * tutorial book, reference manual, or both: *
\r
35 * http://www.FreeRTOS.org/Documentation *
\r
37 ***************************************************************************
\r
39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
\r
40 the FAQ page "My application does not run, what could be wrong?". Have you
\r
41 defined configASSERT()?
\r
43 http://www.FreeRTOS.org/support - In return for receiving this top quality
\r
44 embedded software for free we request you assist our global community by
\r
45 participating in the support forum.
\r
47 http://www.FreeRTOS.org/training - Investing in training allows your team to
\r
48 be as productive as possible as early as possible. Now you can receive
\r
49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
\r
50 Ltd, and the world's leading authority on the world's leading RTOS.
\r
52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
\r
57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
\r
59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
\r
60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
61 licenses offer ticketed support, indemnification and commercial middleware.
\r
63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
64 engineered and independently SIL3 certified version for use in safety and
\r
65 mission critical applications that require provable dependability.
\r
70 /* Standard includes. */
\r
73 /* Scheduler includes. */
\r
74 #include "FreeRTOS.h"
\r
77 #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
\r
78 #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
81 #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
\r
82 #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
85 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
\r
86 #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
89 #ifndef configSETUP_TICK_INTERRUPT
\r
90 #error configSETUP_TICK_INTERRUPT() must be defined. Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
91 #endif /* configSETUP_TICK_INTERRUPT */
\r
93 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
\r
94 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
97 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
\r
98 #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
\r
101 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
\r
102 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
\r
105 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
\r
106 /* Check the configuration. */
\r
107 #if( configMAX_PRIORITIES > 32 )
\r
108 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
\r
110 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
\r
112 /* In case security extensions are implemented. */
\r
113 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
\r
114 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
\r
117 /* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
\r
119 #ifndef configCLEAR_TICK_INTERRUPT
\r
120 #define configCLEAR_TICK_INTERRUPT()
\r
123 /* A critical section is exited when the critical section nesting count reaches
\r
125 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
\r
127 /* In all GICs 255 can be written to the priority mask register to unmask all
\r
128 (but the lowest) interrupt priority. */
\r
129 #define portUNMASK_VALUE ( 0xFFUL )
\r
131 /* Tasks are not created with a floating point context, but can be given a
\r
132 floating point context after they have been created. A variable is stored as
\r
133 part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
\r
134 does not have an FPU context, or any other value if the task does have an FPU
\r
136 #define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
\r
138 /* Constants required to setup the initial task context. */
\r
139 #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
\r
140 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
\r
141 #define portINTERRUPT_ENABLE_BIT ( 0x80UL )
\r
142 #define portTHUMB_MODE_ADDRESS ( 0x01UL )
\r
144 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
\r
146 #define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
\r
148 /* Masks all bits in the APSR other than the mode bits. */
\r
149 #define portAPSR_MODE_BITS_MASK ( 0x1F )
\r
151 /* The value of the mode bits in the APSR when the CPU is executing in user
\r
153 #define portAPSR_USER_MODE ( 0x10 )
\r
155 /* The critical section macros only mask interrupts up to an application
\r
156 determined priority level. Sometimes it is necessary to turn interrupt off in
\r
157 the CPU itself before modifying certain hardware registers. */
\r
158 #define portCPU_IRQ_DISABLE() \
\r
159 __asm volatile ( "CPSID i" ); \
\r
160 __asm volatile ( "DSB" ); \
\r
161 __asm volatile ( "ISB" );
\r
163 #define portCPU_IRQ_ENABLE() \
\r
164 __asm volatile ( "CPSIE i" ); \
\r
165 __asm volatile ( "DSB" ); \
\r
166 __asm volatile ( "ISB" );
\r
169 /* Macro to unmask all interrupt priorities. */
\r
170 #define portCLEAR_INTERRUPT_MASK() \
\r
172 portCPU_IRQ_DISABLE(); \
\r
173 portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
\r
176 portCPU_IRQ_ENABLE(); \
\r
179 #define portINTERRUPT_PRIORITY_REGISTER_OFFSET 0x400UL
\r
180 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
\r
181 #define portBIT_0_SET ( ( uint8_t ) 0x01 )
\r
183 /* Let the user override the pre-loading of the initial LR with the address of
\r
184 prvTaskExitError() in case is messes up unwinding of the stack in the
\r
186 #ifdef configTASK_RETURN_ADDRESS
\r
187 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
\r
189 #define portTASK_RETURN_ADDRESS prvTaskExitError
\r
192 /*-----------------------------------------------------------*/
\r
195 * Starts the first task executing. This function is necessarily written in
\r
196 * assembly code so is implemented in portASM.s.
\r
198 extern void vPortRestoreTaskContext( void );
\r
201 * Used to catch tasks that attempt to return from their implementing function.
\r
203 static void prvTaskExitError( void );
\r
205 /*-----------------------------------------------------------*/
\r
207 /* A variable is used to keep track of the critical section nesting. This
\r
208 variable has to be stored as part of the task context and must be initialised to
\r
209 a non zero value to ensure interrupts don't inadvertently become unmasked before
\r
210 the scheduler starts. As it is stored as part of the task context it will
\r
211 automatically be set to 0 when the first task is started. */
\r
212 volatile uint32_t ulCriticalNesting = 9999UL;
\r
214 /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
\r
215 a floating point context must be saved and restored for the task. */
\r
216 uint32_t ulPortTaskHasFPUContext = pdFALSE;
\r
218 /* Set to 1 to pend a context switch from an ISR. */
\r
219 uint32_t ulPortYieldRequired = pdFALSE;
\r
221 /* Counts the interrupt nesting depth. A context switch is only performed if
\r
222 if the nesting depth is 0. */
\r
223 uint32_t ulPortInterruptNesting = 0UL;
\r
225 /* Used in asm code. */
\r
226 __attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
\r
227 __attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
\r
228 __attribute__(( used )) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
\r
229 __attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
\r
231 /*-----------------------------------------------------------*/
\r
234 * See header file for description.
\r
236 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
\r
238 /* Setup the initial stack of the task. The stack is set exactly as
\r
239 expected by the portRESTORE_CONTEXT() macro.
\r
241 The fist real value on the stack is the status register, which is set for
\r
242 system mode, with interrupts enabled. A few NULLs are added first to ensure
\r
243 GDB does not try decoding a non-existent return address. */
\r
244 *pxTopOfStack = ( StackType_t ) NULL;
\r
246 *pxTopOfStack = ( StackType_t ) NULL;
\r
248 *pxTopOfStack = ( StackType_t ) NULL;
\r
250 *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
\r
252 if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
\r
254 /* The task will start in THUMB mode. */
\r
255 *pxTopOfStack |= portTHUMB_MODE_BIT;
\r
260 /* Next the return address, which in this case is the start of the task. */
\r
261 *pxTopOfStack = ( StackType_t ) pxCode;
\r
264 /* Next all the registers other than the stack pointer. */
\r
265 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
\r
267 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
\r
269 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
\r
271 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
\r
273 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
\r
275 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
\r
277 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
\r
279 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
\r
281 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
\r
283 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
\r
285 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
\r
287 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
\r
289 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
\r
291 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
\r
294 /* The task will start with a critical nesting count of 0 as interrupts are
\r
296 *pxTopOfStack = portNO_CRITICAL_NESTING;
\r
299 /* The task will start without a floating point context. A task that uses
\r
300 the floating point hardware must call vPortTaskUsesFPU() before executing
\r
301 any floating point instructions. */
\r
302 *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
\r
304 return pxTopOfStack;
\r
306 /*-----------------------------------------------------------*/
\r
308 static void prvTaskExitError( void )
\r
310 /* A function that implements a task must not exit or attempt to return to
\r
311 its caller as there is nothing to return to. If a task wants to exit it
\r
312 should instead call vTaskDelete( NULL ).
\r
314 Artificially force an assert() to be triggered if configASSERT() is
\r
315 defined, then stop here so application writers can catch the error. */
\r
316 configASSERT( ulPortInterruptNesting == ~0UL );
\r
317 portDISABLE_INTERRUPTS();
\r
320 /*-----------------------------------------------------------*/
\r
322 BaseType_t xPortStartScheduler( void )
\r
324 uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */
\r
326 #if( configASSERT_DEFINED == 1 )
\r
328 volatile uint32_t ulOriginalPriority;
\r
329 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
\r
330 volatile uint8_t ucMaxPriorityValue;
\r
332 /* Determine how many priority bits are implemented in the GIC.
\r
334 Save the interrupt priority value that is about to be clobbered. */
\r
335 ulOriginalPriority = *pucFirstUserPriorityRegister;
\r
337 /* Determine the number of priority bits available. First write to
\r
338 all possible bits. */
\r
339 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
\r
341 /* Read the value back to see how many bits stuck. */
\r
342 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
\r
344 /* Shift to the least significant bits. */
\r
345 while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
\r
347 ucMaxPriorityValue >>= ( uint8_t ) 0x01;
\r
349 /* If ulCycles reaches 0 then ucMaxPriorityValue must have been
\r
350 read as 0, indicating a misconfiguration. */
\r
352 if( ulCycles == 0 )
\r
358 /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
\r
360 // configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
\r
362 /* Restore the clobbered interrupt priority register to its original
\r
364 *pucFirstUserPriorityRegister = ulOriginalPriority;
\r
366 #endif /* conifgASSERT_DEFINED */
\r
368 /* Only continue if the CPU is not in User mode. The CPU must be in a
\r
369 Privileged mode for the scheduler to start. */
\r
370 __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
\r
371 ulAPSR &= portAPSR_MODE_BITS_MASK;
\r
372 configASSERT( ulAPSR != portAPSR_USER_MODE );
\r
374 if( ulAPSR != portAPSR_USER_MODE )
\r
376 /* Only continue if the binary point value is set to its lowest possible
\r
377 setting. See the comments in vPortValidateInterruptPriority() below for
\r
378 more information. */
\r
379 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
\r
381 if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
\r
383 /* Interrupts are turned off in the CPU itself to ensure tick does
\r
384 not execute while the scheduler is being started. Interrupts are
\r
385 automatically turned back on in the CPU when the first task starts
\r
387 portCPU_IRQ_DISABLE();
\r
389 /* Start the timer that generates the tick ISR. */
\r
390 configSETUP_TICK_INTERRUPT();
\r
392 /* Start the first task executing. */
\r
393 vPortRestoreTaskContext();
\r
397 /* Will only get here if xTaskStartScheduler() was called with the CPU in
\r
398 a non-privileged mode or the binary point register was not set to its lowest
\r
399 possible value. prvTaskExitError() is referenced to prevent a compiler
\r
400 warning about it being defined but not referenced in the case that the user
\r
401 defines their own exit address. */
\r
402 ( void ) prvTaskExitError;
\r
405 /*-----------------------------------------------------------*/
\r
407 void vPortEndScheduler( void )
\r
409 /* Not implemented in ports where there is nothing to return to.
\r
410 Artificially force an assert. */
\r
411 configASSERT( ulCriticalNesting == 1000UL );
\r
413 /*-----------------------------------------------------------*/
\r
415 void vPortEnterCritical( void )
\r
417 /* Mask interrupts up to the max syscall interrupt priority. */
\r
418 ulPortSetInterruptMask();
\r
420 /* Now interrupts are disabled ulCriticalNesting can be accessed
\r
421 directly. Increment ulCriticalNesting to keep a count of how many times
\r
422 portENTER_CRITICAL() has been called. */
\r
423 ulCriticalNesting++;
\r
425 /* This is not the interrupt safe version of the enter critical function so
\r
426 assert() if it is being called from an interrupt context. Only API
\r
427 functions that end in "FromISR" can be used in an interrupt. Only assert if
\r
428 the critical nesting count is 1 to protect against recursive calls if the
\r
429 assert function also uses a critical section. */
\r
430 if( ulCriticalNesting == 1 )
\r
432 configASSERT( ulPortInterruptNesting == 0 );
\r
435 /*-----------------------------------------------------------*/
\r
437 void vPortExitCritical( void )
\r
439 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
\r
441 /* Decrement the nesting count as the critical section is being
\r
443 ulCriticalNesting--;
\r
445 /* If the nesting level has reached zero then all interrupt
\r
446 priorities must be re-enabled. */
\r
447 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
\r
449 /* Critical nesting has reached zero so all interrupt priorities
\r
450 should be unmasked. */
\r
451 portCLEAR_INTERRUPT_MASK();
\r
455 /*-----------------------------------------------------------*/
\r
457 void FreeRTOS_Tick_Handler( void )
\r
459 /* Set interrupt mask before altering scheduler structures. The tick
\r
460 handler runs at the lowest priority, so interrupts cannot already be masked,
\r
461 so there is no need to save and restore the current mask value. It is
\r
462 necessary to turn off interrupts in the CPU itself while the ICCPMR is being
\r
464 portCPU_IRQ_DISABLE();
\r
465 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
\r
466 __asm volatile ( "dsb \n"
\r
468 portCPU_IRQ_ENABLE();
\r
470 /* Increment the RTOS tick. */
\r
471 if( xTaskIncrementTick() != pdFALSE )
\r
473 ulPortYieldRequired = pdTRUE;
\r
476 /* Ensure all interrupt priorities are active again. */
\r
477 portCLEAR_INTERRUPT_MASK();
\r
478 configCLEAR_TICK_INTERRUPT();
\r
480 /*-----------------------------------------------------------*/
\r
482 void vPortTaskUsesFPU( void )
\r
484 uint32_t ulInitialFPSCR = 0;
\r
486 /* A task is registering the fact that it needs an FPU context. Set the
\r
487 FPU flag (which is saved as part of the task context). */
\r
488 ulPortTaskHasFPUContext = pdTRUE;
\r
490 /* Initialise the floating point status register. */
\r
491 __asm volatile ( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) );
\r
493 /*-----------------------------------------------------------*/
\r
495 void vPortClearInterruptMask( uint32_t ulNewMaskValue )
\r
497 if( ulNewMaskValue == pdFALSE )
\r
499 portCLEAR_INTERRUPT_MASK();
\r
502 /*-----------------------------------------------------------*/
\r
504 uint32_t ulPortSetInterruptMask( void )
\r
508 /* Interrupt in the CPU must be turned off while the ICCPMR is being
\r
510 portCPU_IRQ_DISABLE();
\r
511 if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
\r
513 /* Interrupts were already masked. */
\r
518 ulReturn = pdFALSE;
\r
519 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
\r
520 __asm volatile ( "dsb \n"
\r
523 portCPU_IRQ_ENABLE();
\r
527 /*-----------------------------------------------------------*/
\r
529 #if( configASSERT_DEFINED == 1 )
\r
531 void vPortValidateInterruptPriority( void )
\r
533 /* The following assertion will fail if a service routine (ISR) for
\r
534 an interrupt that has been assigned a priority above
\r
535 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
536 function. ISR safe FreeRTOS API functions must *only* be called
\r
537 from interrupts that have been assigned a priority at or below
\r
538 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
540 Numerically low interrupt priority numbers represent logically high
\r
541 interrupt priorities, therefore the priority of the interrupt must
\r
542 be set to a value equal to or numerically *higher* than
\r
543 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
545 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
546 interrupt entry is as fast and simple as possible. */
\r
548 configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
\r
550 /* Priority grouping: The interrupt controller (GIC) allows the bits
\r
551 that define each interrupt's priority to be split between bits that
\r
552 define the interrupt's pre-emption priority bits and bits that define
\r
553 the interrupt's sub-priority. For simplicity all bits must be defined
\r
554 to be pre-emption priority bits. The following assertion will fail if
\r
555 this is not the case (if some bits represent a sub-priority).
\r
557 The priority grouping is configured by the GIC's binary point register
\r
558 (ICCBPR). Writing 0 to ICCBPR will ensure it is set to its lowest
\r
559 possible value (which may be above 0). */
\r
560 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
\r
563 #endif /* configASSERT_DEFINED */
\r
564 /*-----------------------------------------------------------*/
\r