1 /*This file has been prepared for Doxygen automatic documentation generation.*/
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2 /*! \file *********************************************************************
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4 * \brief FreeRTOS port source for AVR32 UC3.
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6 * - Compiler: GNU GCC for AVR32
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7 * - Supported devices: All AVR32 devices can be used.
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10 * \author Atmel Corporation: http://www.atmel.com \n
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11 * Support and FAQ: http://support.atmel.no/
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13 *****************************************************************************/
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16 * FreeRTOS Kernel V10.2.0
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17 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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19 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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20 * this software and associated documentation files (the "Software"), to deal in
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21 * the Software without restriction, including without limitation the rights to
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22 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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23 * the Software, and to permit persons to whom the Software is furnished to do so,
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24 * subject to the following conditions:
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26 * The above copyright notice and this permission notice shall be included in all
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27 * copies or substantial portions of the Software.
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29 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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30 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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31 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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32 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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33 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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34 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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36 * http://www.FreeRTOS.org
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37 * http://aws.amazon.com/freertos
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39 * 1 tab == 4 spaces!
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46 /*-----------------------------------------------------------
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47 * Port specific definitions.
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49 * The settings in this file configure FreeRTOS correctly for the
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50 * given hardware and compiler.
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52 * These settings should not be altered.
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53 *-----------------------------------------------------------
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55 #include <avr32/io.h>
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57 #include "compiler.h"
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64 /* Type definitions. */
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65 #define portCHAR char
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66 #define portFLOAT float
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67 #define portDOUBLE double
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68 #define portLONG long
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69 #define portSHORT short
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70 #define portSTACK_TYPE uint32_t
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71 #define portBASE_TYPE long
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73 typedef portSTACK_TYPE StackType_t;
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74 typedef long BaseType_t;
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75 typedef unsigned long UBaseType_t;
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77 #define TASK_DELAY_MS(x) ( (x) /portTICK_PERIOD_MS )
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78 #define TASK_DELAY_S(x) ( (x)*1000 /portTICK_PERIOD_MS )
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79 #define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_PERIOD_MS )
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81 #define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
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83 #if( configUSE_16_BIT_TICKS == 1 )
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84 typedef uint16_t TickType_t;
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85 #define portMAX_DELAY ( TickType_t ) 0xffff
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87 typedef uint32_t TickType_t;
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88 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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90 /*-----------------------------------------------------------*/
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92 /* Architecture specifics. */
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93 #define portSTACK_GROWTH ( -1 )
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94 #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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95 #define portBYTE_ALIGNMENT 4
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96 #define portNOP() {__asm__ __volatile__ ("nop");}
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97 /*-----------------------------------------------------------*/
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100 /*-----------------------------------------------------------*/
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102 /* INTC-specific. */
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103 #define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
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104 #define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
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106 #define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
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107 #define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
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109 #define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev)
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110 #define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev)
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115 * Activated if and only if configDBG is nonzero.
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116 * Prints a formatted string to stdout.
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117 * The current source file name and line number are output with a colon before
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118 * the formatted string.
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119 * A carriage return and a linefeed are appended to the output.
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120 * stdout is redirected to the USART configured by configDBG_USART.
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121 * The parameters are the same as for the standard printf function.
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122 * There is no return value.
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123 * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
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124 * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
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127 #define portDBG_TRACE(...) \
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129 fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);\
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130 printf(__VA_ARGS__);\
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131 fputs("\r\n", stdout);\
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134 #define portDBG_TRACE(...)
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138 /* Critical section management. */
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139 #define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
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140 #define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
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143 extern void vPortEnterCritical( void );
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144 extern void vPortExitCritical( void );
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146 #define portENTER_CRITICAL() vPortEnterCritical();
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147 #define portEXIT_CRITICAL() vPortExitCritical();
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150 /* Added as there is no such function in FreeRTOS. */
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151 extern void *pvPortRealloc( void *pv, size_t xSize );
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152 /*-----------------------------------------------------------*/
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155 /*=============================================================================================*/
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158 * Restore Context for cases other than INTi.
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160 #define portRESTORE_CONTEXT() \
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162 extern volatile uint32_t ulCriticalNesting; \
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163 extern volatile void *volatile pxCurrentTCB; \
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165 __asm__ __volatile__ ( \
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166 /* Set SP to point to new stack */ \
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167 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
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168 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
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169 "ld.w r0, r8[0] \n\t"\
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170 "ld.w sp, r0[0] \n\t"\
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172 /* Restore ulCriticalNesting variable */ \
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173 "ld.w r0, sp++ \n\t"\
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174 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
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175 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
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176 "st.w r8[0], r0 \n\t"\
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178 /* Restore R0..R7 */ \
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179 "ldm sp++, r0-r7 \n\t"\
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180 /* R0-R7 should not be used below this line */ \
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181 /* Skip PC and SR (will do it at the end) */ \
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182 "sub sp, -2*4 \n\t"\
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183 /* Restore R8..R12 and LR */ \
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184 "ldm sp++, r8-r12, lr \n\t"\
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186 "ld.w r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */ \
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187 "mtsr %[SR], r0 \n\t"\
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189 "ld.w r0, sp[-9*4] \n\t"\
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191 "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
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193 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
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194 [pxCurrentTCB] "i" (&pxCurrentTCB), \
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195 [SR] "i" (AVR32_SR) \
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201 * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
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202 * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
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204 * Had to make different versions because registers saved on the system stack
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205 * are not the same between INT0..3 exceptions and the scall exception.
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208 // Task context stack layout:
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225 // ulCriticalNesting
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226 // (*) automatically done for INT0..INT3, but not for SCALL
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229 * The ISR used for the scheduler tick depends on whether the cooperative or
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230 * the preemptive scheduler is being used.
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232 #if configUSE_PREEMPTION == 0
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235 * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
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237 #define portSAVE_CONTEXT_OS_INT() \
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239 /* Save R0..R7 */ \
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240 __asm__ __volatile__ ("stm --sp, r0-r7"); \
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242 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
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243 /* there is also no context save. */ \
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247 * portRESTORE_CONTEXT_OS_INT() for Tick exception.
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249 #define portRESTORE_CONTEXT_OS_INT() \
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251 __asm__ __volatile__ ( \
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252 /* Restore R0..R7 */ \
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253 "ldm sp++, r0-r7\n\t" \
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255 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
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256 /* there is also no context restore. */ \
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264 * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
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266 #define portSAVE_CONTEXT_OS_INT() \
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268 extern volatile uint32_t ulCriticalNesting; \
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269 extern volatile void *volatile pxCurrentTCB; \
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271 /* When we come here */ \
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272 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
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274 __asm__ __volatile__ ( \
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275 /* Save R0..R7 */ \
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276 "stm --sp, r0-r7 \n\t"\
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278 /* Save ulCriticalNesting variable - R0 is overwritten */ \
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279 "mov r8, LO(%[ulCriticalNesting])\n\t" \
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280 "orh r8, HI(%[ulCriticalNesting])\n\t" \
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281 "ld.w r0, r8[0] \n\t"\
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282 "st.w --sp, r0 \n\t"\
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284 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
285 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
286 /* level and allow other lower interrupt level to occur). */ \
\r
287 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
288 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
289 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
290 /* will just be restoring the interrupt handler, no way!!! */ \
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291 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
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292 "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
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293 "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
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294 "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
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295 "brhi LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
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297 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
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298 /* NOTE: we don't enter a critical section here because all interrupt handlers */ \
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299 /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
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300 /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
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301 /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
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302 "mov r8, LO(%[pxCurrentTCB])\n\t" \
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303 "orh r8, HI(%[pxCurrentTCB])\n\t" \
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304 "ld.w r0, r8[0]\n\t" \
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305 "st.w r0[0], sp\n" \
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307 "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:" \
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309 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
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310 [pxCurrentTCB] "i" (&pxCurrentTCB), \
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311 [LINE] "i" (__LINE__) \
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316 * portRESTORE_CONTEXT_OS_INT() for Tick exception.
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318 #define portRESTORE_CONTEXT_OS_INT() \
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320 extern volatile uint32_t ulCriticalNesting; \
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321 extern volatile void *volatile pxCurrentTCB; \
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323 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
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324 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
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325 /* level and allow other lower interrupt level to occur). */ \
\r
326 /* In this case we don't want to do a task switch because we don't know what the stack */ \
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327 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
328 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
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329 /* will just be restoring the interrupt handler, no way!!! */ \
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330 __asm__ __volatile__ ( \
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331 "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
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332 "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
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333 "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
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334 "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]" \
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336 : [LINE] "i" (__LINE__) \
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340 /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
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341 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
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342 portENTER_CRITICAL(); \
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343 vTaskSwitchContext(); \
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344 portEXIT_CRITICAL(); \
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346 /* Restore all registers */ \
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348 __asm__ __volatile__ ( \
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349 /* Set SP to point to new stack */ \
\r
350 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
351 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
352 "ld.w r0, r8[0] \n\t"\
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353 "ld.w sp, r0[0] \n"\
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355 "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
\r
357 /* Restore ulCriticalNesting variable */ \
\r
358 "ld.w r0, sp++ \n\t" \
\r
359 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
360 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
361 "st.w r8[0], r0 \n\t"\
\r
363 /* Restore R0..R7 */ \
\r
364 "ldm sp++, r0-r7 \n\t"\
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366 /* Now, the stack should be R8..R12, LR, PC and SR */ \
\r
369 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
\r
370 [pxCurrentTCB] "i" (&pxCurrentTCB), \
\r
371 [LINE] "i" (__LINE__) \
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379 * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
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381 * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
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384 #define portSAVE_CONTEXT_SCALL() \
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386 extern volatile uint32_t ulCriticalNesting; \
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387 extern volatile void *volatile pxCurrentTCB; \
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389 /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
\r
390 /* If SR[M2:M0] == 001 */ \
\r
391 /* PC and SR are on the stack. */ \
\r
392 /* Else (other modes) */ \
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393 /* Nothing on the stack. */ \
\r
395 /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
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396 /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
\r
397 /* in an interrupt|exception handler. */ \
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399 __asm__ __volatile__ ( \
\r
400 /* in order to save R0-R7 */ \
\r
401 "sub sp, 6*4 \n\t"\
\r
402 /* Save R0..R7 */ \
\r
403 "stm --sp, r0-r7 \n\t"\
\r
405 /* in order to save R8-R12 and LR */ \
\r
406 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
\r
407 "sub r7, sp,-16*4 \n\t"\
\r
408 /* Copy PC and SR in other places in the stack. */ \
\r
409 "ld.w r0, r7[-2*4] \n\t" /* Read SR */\
\r
410 "st.w r7[-8*4], r0 \n\t" /* Copy SR */\
\r
411 "ld.w r0, r7[-1*4] \n\t" /* Read PC */\
\r
412 "st.w r7[-7*4], r0 \n\t" /* Copy PC */\
\r
414 /* Save R8..R12 and LR on the stack. */ \
\r
415 "stm --r7, r8-r12, lr \n\t"\
\r
417 /* Arriving here we have the following stack organizations: */ \
\r
418 /* R8..R12, LR, PC, SR, R0..R7. */ \
\r
420 /* Now we can finalize the save. */ \
\r
422 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
423 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
424 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
425 "ld.w r0, r8[0] \n\t"\
\r
428 : [ulCriticalNesting] "i" (&ulCriticalNesting) \
\r
431 /* Disable the its which may cause a context switch (i.e. cause a change of */ \
\r
432 /* pxCurrentTCB). */ \
\r
433 /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
\r
434 /* critical section because it is a global structure. */ \
\r
435 portENTER_CRITICAL(); \
\r
437 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
438 __asm__ __volatile__ ( \
\r
439 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
440 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
441 "ld.w r0, r8[0] \n\t"\
\r
444 : [pxCurrentTCB] "i" (&pxCurrentTCB) \
\r
449 * portRESTORE_CONTEXT() for SupervisorCALL exception.
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451 #define portRESTORE_CONTEXT_SCALL() \
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453 extern volatile uint32_t ulCriticalNesting; \
\r
454 extern volatile void *volatile pxCurrentTCB; \
\r
456 /* Restore all registers */ \
\r
458 /* Set SP to point to new stack */ \
\r
459 __asm__ __volatile__ ( \
\r
460 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
461 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
462 "ld.w r0, r8[0] \n\t"\
\r
465 : [pxCurrentTCB] "i" (&pxCurrentTCB) \
\r
468 /* Leave pxCurrentTCB variable access critical section */ \
\r
469 portEXIT_CRITICAL(); \
\r
471 __asm__ __volatile__ ( \
\r
472 /* Restore ulCriticalNesting variable */ \
\r
473 "ld.w r0, sp++ \n\t"\
\r
474 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
475 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
476 "st.w r8[0], r0 \n\t"\
\r
478 /* skip PC and SR */ \
\r
479 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
\r
480 "sub r7, sp, -10*4 \n\t"\
\r
481 /* Restore r8-r12 and LR */ \
\r
482 "ldm r7++, r8-r12, lr \n\t"\
\r
484 /* RETS will take care of the extra PC and SR restore. */ \
\r
485 /* So, we have to prepare the stack for this. */ \
\r
486 "ld.w r0, r7[-8*4] \n\t" /* Read SR */\
\r
487 "st.w r7[-2*4], r0 \n\t" /* Copy SR */\
\r
488 "ld.w r0, r7[-7*4] \n\t" /* Read PC */\
\r
489 "st.w r7[-1*4], r0 \n\t" /* Copy PC */\
\r
491 /* Restore R0..R7 */ \
\r
492 "ldm sp++, r0-r7 \n\t"\
\r
494 "sub sp, -6*4 \n\t"\
\r
498 : [ulCriticalNesting] "i" (&ulCriticalNesting) \
\r
504 * The ISR used depends on whether the cooperative or
\r
505 * the preemptive scheduler is being used.
\r
507 #if configUSE_PREEMPTION == 0
\r
510 * ISR entry and exit macros. These are only required if a task switch
\r
511 * is required from the ISR.
\r
513 #define portENTER_SWITCHING_ISR() \
\r
515 /* Save R0..R7 */ \
\r
516 __asm__ __volatile__ ("stm --sp, r0-r7"); \
\r
518 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
519 /* there is also no context save. */ \
\r
523 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
\r
525 #define portEXIT_SWITCHING_ISR() \
\r
527 __asm__ __volatile__ ( \
\r
528 /* Restore R0..R7 */ \
\r
529 "ldm sp++, r0-r7 \n\t"\
\r
531 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
532 /* there is also no context restore. */ \
\r
540 * ISR entry and exit macros. These are only required if a task switch
\r
541 * is required from the ISR.
\r
543 #define portENTER_SWITCHING_ISR() \
\r
545 extern volatile uint32_t ulCriticalNesting; \
\r
546 extern volatile void *volatile pxCurrentTCB; \
\r
548 /* When we come here */ \
\r
549 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
\r
551 __asm__ __volatile__ ( \
\r
552 /* Save R0..R7 */ \
\r
553 "stm --sp, r0-r7 \n\t"\
\r
555 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
556 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
557 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
558 "ld.w r0, r8[0] \n\t"\
\r
559 "st.w --sp, r0 \n\t"\
\r
561 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
562 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
563 /* level and allow other lower interrupt level to occur). */ \
\r
564 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
565 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
566 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
567 /* will just be restoring the interrupt handler, no way!!! */ \
\r
568 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
\r
569 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
570 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
571 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
572 "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
\r
574 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
575 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
576 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
577 "ld.w r0, r8[0] \n\t"\
\r
578 "st.w r0[0], sp \n"\
\r
580 "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \
\r
582 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
\r
583 [pxCurrentTCB] "i" (&pxCurrentTCB), \
\r
584 [LINE] "i" (__LINE__) \
\r
589 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
\r
591 #define portEXIT_SWITCHING_ISR() \
\r
593 extern volatile uint32_t ulCriticalNesting; \
\r
594 extern volatile void *volatile pxCurrentTCB; \
\r
596 __asm__ __volatile__ ( \
\r
597 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
598 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
599 /* level and allow other lower interrupt level to occur). */ \
\r
600 /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
\r
601 /* did not previously save SP in its TCB. */ \
\r
602 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
603 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
604 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
605 "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t"\
\r
607 /* If a switch is required then we just need to call */ \
\r
608 /* vTaskSwitchContext() as the context has already been */ \
\r
610 "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\
\r
611 "brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \
\r
613 : [LINE] "i" (__LINE__) \
\r
616 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
\r
617 portENTER_CRITICAL(); \
\r
618 vTaskSwitchContext(); \
\r
619 portEXIT_CRITICAL(); \
\r
621 __asm__ __volatile__ ( \
\r
622 "LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t"\
\r
623 /* Restore the context of which ever task is now the highest */ \
\r
624 /* priority that is ready to run. */ \
\r
626 /* Restore all registers */ \
\r
628 /* Set SP to point to new stack */ \
\r
629 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
630 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
631 "ld.w r0, r8[0] \n\t"\
\r
632 "ld.w sp, r0[0] \n"\
\r
634 "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
\r
636 /* Restore ulCriticalNesting variable */ \
\r
637 "ld.w r0, sp++ \n\t"\
\r
638 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
639 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
640 "st.w r8[0], r0 \n\t"\
\r
642 /* Restore R0..R7 */ \
\r
643 "ldm sp++, r0-r7 \n\t"\
\r
645 /* Now, the stack should be R8..R12, LR, PC and SR */ \
\r
648 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
\r
649 [pxCurrentTCB] "i" (&pxCurrentTCB), \
\r
650 [LINE] "i" (__LINE__) \
\r
657 #define portYIELD() {__asm__ __volatile__ ("scall");}
\r
659 /* Task function macros as described on the FreeRTOS.org WEB site. */
\r
660 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
\r
661 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
\r
667 #endif /* PORTMACRO_H */
\r