2 * FreeRTOS Kernel V10.3.0
\r
3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
\r
5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
\r
6 * this software and associated documentation files (the "Software"), to deal in
\r
7 * the Software without restriction, including without limitation the rights to
\r
8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
\r
9 * the Software, and to permit persons to whom the Software is furnished to do so,
\r
10 * subject to the following conditions:
\r
12 * The above copyright notice and this permission notice shall be included in all
\r
13 * copies or substantial portions of the Software.
\r
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
\r
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
\r
17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
\r
18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
\r
19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
\r
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
\r
22 * http://www.FreeRTOS.org
\r
23 * http://aws.amazon.com/freertos
\r
25 * 1 tab == 4 spaces!
\r
27 .extern pxCurrentTCB
\r
28 .extern vTaskISRHandler
\r
29 .extern vTaskSwitchContext
\r
30 .extern uxCriticalNesting
\r
33 .global __FreeRTOS_interrupt_handler
\r
34 .global VPortYieldASM
\r
35 .global vStartFirstTask
\r
38 .macro portSAVE_CONTEXT
\r
39 /* Make room for the context on the stack. */
\r
41 /* Save r31 so it can then be used. */
\r
43 /* Copy the msr into r31 - this is stacked later. */
\r
45 /* Stack general registers. */
\r
74 /* Stack the critical section nesting value. */
\r
75 lwi r3, r0, uxCriticalNesting
\r
77 /* Save the top of stack value to the TCB. */
\r
78 lwi r3, r0, pxCurrentTCB
\r
83 .macro portRESTORE_CONTEXT
\r
84 /* Load the top of stack value from the TCB. */
\r
85 lwi r3, r0, pxCurrentTCB
\r
87 /* Restore the general registers. */
\r
118 /* Load the critical nesting value. */
\r
120 swi r3, r0, uxCriticalNesting
\r
122 /* Obtain the MSR value from the stack. */
\r
125 /* Are interrupts enabled in the MSR? If so return using an return from
\r
126 interrupt instruction to ensure interrupts are enabled only once the task
\r
127 is running again. */
\r
132 /* Reload the rmsr from the stack, clear the enable interrupt bit in the
\r
133 value before saving back to rmsr register, then return enabling interrupts
\r
143 /* Reload the rmsr from the stack, place it in the rmsr register, and
\r
144 return without enabling interrupts. */
\r
158 __FreeRTOS_interrupt_handler:
\r
160 /* Entered via an interrupt so interrupts must be enabled in msr. */
\r
164 /* Stack the return address. As we entered via an interrupt we do
\r
165 not need to modify the return address prior to stacking. */
\r
167 /* Now switch to use the ISR stack. */
\r
168 lwi r3, r0, pulISRStack
\r
170 bralid r15, vTaskISRHandler
\r
172 portRESTORE_CONTEXT
\r
179 /* Modify the return address so we return to the instruction after the
\r
183 /* Now switch to use the ISR stack. */
\r
184 lwi r3, r0, pulISRStack
\r
186 bralid r15, vTaskSwitchContext
\r
188 portRESTORE_CONTEXT
\r
191 portRESTORE_CONTEXT
\r