2 FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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13 >>! NOTE: The modification to the GPL is included to allow you to !<<
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14 >>! distribute a combined work that includes FreeRTOS without being !<<
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15 >>! obliged to provide the source code for proprietary components !<<
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16 >>! outside of the FreeRTOS kernel. !<<
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18 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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19 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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20 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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21 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * Having a problem? Start by reading the FAQ "My application does *
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28 * not run, what could be wrong?". Have you defined configASSERT()? *
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30 * http://www.FreeRTOS.org/FAQHelp.html *
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32 ***************************************************************************
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34 ***************************************************************************
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36 * FreeRTOS provides completely free yet professionally developed, *
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37 * robust, strictly quality controlled, supported, and cross *
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38 * platform software that is more than just the market leader, it *
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39 * is the industry's de facto standard. *
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41 * Help yourself get started quickly while simultaneously helping *
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42 * to support the FreeRTOS project by purchasing a FreeRTOS *
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43 * tutorial book, reference manual, or both: *
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44 * http://www.FreeRTOS.org/Documentation *
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46 ***************************************************************************
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48 ***************************************************************************
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50 * Investing in training allows your team to be as productive as *
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51 * possible as early as possible, lowering your overall development *
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52 * cost, and enabling you to bring a more robust product to market *
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53 * earlier than would otherwise be possible. Richard Barry is both *
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54 * the architect and key author of FreeRTOS, and so also the world's *
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55 * leading authority on what is the world's most popular real time *
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56 * kernel for deeply embedded MCU designs. Obtaining your training *
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57 * from Richard ensures your team will gain directly from his in-depth *
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58 * product knowledge and years of usage experience. Contact Real Time *
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59 * Engineers Ltd to enquire about the FreeRTOS Masterclass, presented *
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60 * by Richard Barry: http://www.FreeRTOS.org/contact
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62 ***************************************************************************
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64 ***************************************************************************
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66 * You are receiving this top quality software for free. Please play *
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67 * fair and reciprocate by reporting any suspected issues and *
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68 * participating in the community forum: *
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69 * http://www.FreeRTOS.org/support *
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73 ***************************************************************************
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75 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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76 license and Real Time Engineers Ltd. contact details.
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78 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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79 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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80 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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82 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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83 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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85 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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86 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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87 licenses offer ticketed support, indemnification and commercial middleware.
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89 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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90 engineered and independently SIL3 certified version for use in safety and
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91 mission critical applications that require provable dependability.
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96 /*-----------------------------------------------------------
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97 * Implementation of functions defined in portable.h for the MicroBlaze port.
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98 *----------------------------------------------------------*/
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101 /* Scheduler includes. */
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102 #include "FreeRTOS.h"
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105 /* Standard includes. */
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106 #include <string.h>
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108 /* Hardware includes. */
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109 #include <xintc_i.h>
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110 #include <xil_exception.h>
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111 #include <microblaze_exceptions_g.h>
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113 /* Tasks are started with a critical section nesting of 0 - however, prior to
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114 the scheduler being commenced interrupts should not be enabled, so the critical
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115 nesting variable is initialised to a non-zero value. */
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116 #define portINITIAL_NESTING_VALUE ( 0xff )
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118 /* The bit within the MSR register that enabled/disables interrupts. */
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119 #define portMSR_IE ( 0x02U )
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121 /* If the floating point unit is included in the MicroBlaze build, then the
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122 FSR register is saved as part of the task context. portINITIAL_FSR is the value
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123 given to the FSR register when the initial context is set up for a task being
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125 #define portINITIAL_FSR ( 0U )
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126 /*-----------------------------------------------------------*/
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129 * Initialise the interrupt controller instance.
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131 static int32_t prvInitialiseInterruptController( void );
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133 /* Ensure the interrupt controller instance variable is initialised before it is
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134 * used, and that the initialisation only happens once.
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136 static int32_t prvEnsureInterruptControllerIsInitialised( void );
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138 /*-----------------------------------------------------------*/
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140 /* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
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141 maintains its own count, so this variable is saved as part of the task
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143 volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
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145 /* This port uses a separate stack for interrupts. This prevents the stack of
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146 every task needing to be large enough to hold an entire interrupt stack on top
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147 of the task stack. */
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148 uint32_t *pulISRStack;
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150 /* If an interrupt requests a context switch, then ulTaskSwitchRequested will
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151 get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
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152 handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
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153 will call vTaskSwitchContext() to ensure the task that runs immediately after
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154 the interrupt exists is the highest priority task that is able to run. This is
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155 an unusual mechanism, but is used for this port because a single interrupt can
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156 cause the servicing of multiple peripherals - and it is inefficient to call
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157 vTaskSwitchContext() multiple times as each peripheral is serviced. */
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158 volatile uint32_t ulTaskSwitchRequested = 0UL;
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160 /* The instance of the interrupt controller used by this port. This is required
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161 by the Xilinx library API functions. */
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162 static XIntc xInterruptControllerInstance;
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164 /*-----------------------------------------------------------*/
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167 * Initialise the stack of a task to look exactly as if a call to
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168 * portSAVE_CONTEXT had been made.
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170 * See the portable.h header file.
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172 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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174 extern void *_SDA2_BASE_, *_SDA_BASE_;
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175 const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
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176 const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
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178 /* Place a few bytes of known values on the bottom of the stack.
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179 This is essential for the Microblaze port and these lines must
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181 *pxTopOfStack = ( StackType_t ) 0x00000000;
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183 *pxTopOfStack = ( StackType_t ) 0x00000000;
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185 *pxTopOfStack = ( StackType_t ) 0x00000000;
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188 #if XPAR_MICROBLAZE_0_USE_FPU != 0
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189 /* The FSR value placed in the initial task context is just 0. */
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190 *pxTopOfStack = portINITIAL_FSR;
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194 /* The MSR value placed in the initial task context should have interrupts
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195 disabled. Each task will enable interrupts automatically when it enters
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196 the running state for the first time. */
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197 *pxTopOfStack = mfmsr() & ~portMSR_IE;
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200 /* First stack an initial value for the critical section nesting. This
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201 is initialised to zero. */
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202 *pxTopOfStack = ( StackType_t ) 0x00;
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204 /* R0 is always zero. */
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205 /* R1 is the SP. */
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207 /* Place an initial value for all the general purpose registers. */
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209 *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */
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211 *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */
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213 *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */
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215 *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
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217 #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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219 *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. Used as the return address from vPortTaskEntryPoint. */
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221 *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */
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223 *pxTopOfStack = ( StackType_t ) 0x08; /* R8 - other parameters and temporaries. */
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225 *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */
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227 *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */
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229 *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */
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231 *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */
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237 *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
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239 *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
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241 *pxTopOfStack = ( StackType_t ) NULL; /* R15 - return address for subroutine. */
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243 #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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245 *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */
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247 *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */
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249 *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */
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255 *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
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257 #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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259 *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */
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261 *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */
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263 *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */
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265 *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */
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267 *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */
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269 *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */
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271 *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */
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273 *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */
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275 *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */
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277 *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */
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279 *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */
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281 *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */
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284 pxTopOfStack -= 13;
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287 /* Return a pointer to the top of the stack that has been generated so this
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288 can be stored in the task control block for the task. */
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289 return pxTopOfStack;
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291 /*-----------------------------------------------------------*/
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293 BaseType_t xPortStartScheduler( void )
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295 extern void ( vPortStartFirstTask )( void );
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296 extern uint32_t _stack[];
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298 /* Setup the hardware to generate the tick. Interrupts are disabled when
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299 this function is called.
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301 This port uses an application defined callback function to install the tick
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302 interrupt handler because the kernel will run on lots of different
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303 MicroBlaze and FPGA configurations - not all of which will have the same
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304 timer peripherals defined or available. An example definition of
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305 vApplicationSetupTimerInterrupt() is provided in the official demo
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306 application that accompanies this port. */
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307 vApplicationSetupTimerInterrupt();
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309 /* Reuse the stack from main() as the stack for the interrupts/exceptions. */
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310 pulISRStack = ( uint32_t * ) _stack;
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312 /* Ensure there is enough space for the functions called from the interrupt
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313 service routines to write back into the stack frame of the caller. */
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316 /* Restore the context of the first task that is going to run. From here
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317 on, the created tasks will be executing. */
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318 vPortStartFirstTask();
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320 /* Should not get here as the tasks are now running! */
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323 /*-----------------------------------------------------------*/
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325 void vPortEndScheduler( void )
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327 /* Not implemented in ports where there is nothing to return to.
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328 Artificially force an assert. */
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329 configASSERT( uxCriticalNesting == 1000UL );
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331 /*-----------------------------------------------------------*/
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334 * Manual context switch called by portYIELD or taskYIELD.
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336 void vPortYield( void )
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338 extern void VPortYieldASM( void );
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340 /* Perform the context switch in a critical section to assure it is
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341 not interrupted by the tick ISR. It is not a problem to do this as
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342 each task maintains its own interrupt status. */
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343 portENTER_CRITICAL();
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345 /* Jump directly to the yield function to ensure there is no
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346 compiler generated prologue code. */
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347 asm volatile ( "bralid r14, VPortYieldASM \n\t" \
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348 "or r0, r0, r0 \n\t" );
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350 portEXIT_CRITICAL();
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352 /*-----------------------------------------------------------*/
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354 void vPortEnableInterrupt( uint8_t ucInterruptID )
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358 /* An API function is provided to enable an interrupt in the interrupt
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359 controller because the interrupt controller instance variable is private
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361 lReturn = prvEnsureInterruptControllerIsInitialised();
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362 if( lReturn == pdPASS )
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364 XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
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367 configASSERT( lReturn );
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369 /*-----------------------------------------------------------*/
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371 void vPortDisableInterrupt( uint8_t ucInterruptID )
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375 /* An API function is provided to disable an interrupt in the interrupt
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376 controller because the interrupt controller instance variable is private
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378 lReturn = prvEnsureInterruptControllerIsInitialised();
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380 if( lReturn == pdPASS )
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382 XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
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385 configASSERT( lReturn );
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387 /*-----------------------------------------------------------*/
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389 BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
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393 /* An API function is provided to install an interrupt handler because the
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394 interrupt controller instance variable is private to this file. */
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396 lReturn = prvEnsureInterruptControllerIsInitialised();
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398 if( lReturn == pdPASS )
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400 lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
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403 if( lReturn == XST_SUCCESS )
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408 configASSERT( lReturn == pdPASS );
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412 /*-----------------------------------------------------------*/
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414 static int32_t prvEnsureInterruptControllerIsInitialised( void )
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416 static int32_t lInterruptControllerInitialised = pdFALSE;
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419 /* Ensure the interrupt controller instance variable is initialised before
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420 it is used, and that the initialisation only happens once. */
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421 if( lInterruptControllerInitialised != pdTRUE )
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423 lReturn = prvInitialiseInterruptController();
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425 if( lReturn == pdPASS )
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427 lInterruptControllerInitialised = pdTRUE;
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437 /*-----------------------------------------------------------*/
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440 * Handler for the timer interrupt. This is the handler that the application
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441 * defined callback function vApplicationSetupTimerInterrupt() should install.
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443 void vPortTickISR( void *pvUnused )
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445 extern void vApplicationClearTimerInterrupt( void );
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447 /* Ensure the unused parameter does not generate a compiler warning. */
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450 /* This port uses an application defined callback function to clear the tick
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451 interrupt because the kernel will run on lots of different MicroBlaze and
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452 FPGA configurations - not all of which will have the same timer peripherals
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453 defined or available. An example definition of
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454 vApplicationClearTimerInterrupt() is provided in the official demo
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455 application that accompanies this port. */
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456 vApplicationClearTimerInterrupt();
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458 /* Increment the RTOS tick - this might cause a task to unblock. */
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459 if( xTaskIncrementTick() != pdFALSE )
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461 /* Force vTaskSwitchContext() to be called as the interrupt exits. */
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462 ulTaskSwitchRequested = 1;
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465 /*-----------------------------------------------------------*/
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467 static int32_t prvInitialiseInterruptController( void )
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471 lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
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473 if( lStatus == XST_SUCCESS )
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475 /* Initialise the exception table. */
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476 Xil_ExceptionInit();
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478 /* Service all pending interrupts each time the handler is entered. */
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479 XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
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481 /* Install exception handlers if the MicroBlaze is configured to handle
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482 exceptions, and the application defined constant
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483 configINSTALL_EXCEPTION_HANDLERS is set to 1. */
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484 #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
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486 vPortExceptionsInstallHandlers();
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488 #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
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490 /* Start the interrupt controller. Interrupts are enabled when the
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491 scheduler starts. */
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492 lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
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494 if( lStatus == XST_SUCCESS )
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504 configASSERT( lStatus == pdPASS );
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508 /*-----------------------------------------------------------*/
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