2 * FreeRTOS Kernel V10.0.1
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /* Scheduler includes. */
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29 #include "FreeRTOS.h"
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32 /* Hardware includes. */
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33 #include <microblaze_exceptions_i.h>
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34 #include <microblaze_exceptions_g.h>
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36 /* The Xilinx library defined exception entry point stacks a number of
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37 registers. These definitions are offsets from the stack pointer to the various
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38 stacked register values. */
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39 #define portexR3_STACK_OFFSET 4
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40 #define portexR4_STACK_OFFSET 5
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41 #define portexR5_STACK_OFFSET 6
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42 #define portexR6_STACK_OFFSET 7
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43 #define portexR7_STACK_OFFSET 8
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44 #define portexR8_STACK_OFFSET 9
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45 #define portexR9_STACK_OFFSET 10
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46 #define portexR10_STACK_OFFSET 11
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47 #define portexR11_STACK_OFFSET 12
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48 #define portexR12_STACK_OFFSET 13
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49 #define portexR15_STACK_OFFSET 16
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50 #define portexR18_STACK_OFFSET 19
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51 #define portexMSR_STACK_OFFSET 20
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52 #define portexR19_STACK_OFFSET -1
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54 /* This is defined to equal the size, in bytes, of the stack frame generated by
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55 the Xilinx standard library exception entry point. It is required to determine
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56 the stack pointer value prior to the exception being entered. */
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57 #define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
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59 /* The number of bytes a MicroBlaze instruction consumes. */
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60 #define portexINSTRUCTION_SIZE 4
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62 /* Exclude this entire file if the MicroBlaze is not configured to handle
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63 exceptions, or the application defined configuration constant
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64 configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
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65 #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
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67 /* This variable is set in the exception entry code, before
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68 vPortExceptionHandler is called. */
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69 uint32_t *pulStackPointerOnFunctionEntry = NULL;
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71 /* This is the structure that is filled with the MicroBlaze context as it
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72 existed immediately prior to the exception occurrence. A pointer to this
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73 structure is passed into the vApplicationExceptionRegisterDump() callback
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74 function, if one is defined. */
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75 static xPortRegisterDump xRegisterDump;
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77 /* This is the FreeRTOS exception handler that is installed for all exception
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78 types. It is called from vPortExceptionHanlderEntry() - which is itself defined
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80 void vPortExceptionHandler( void *pvExceptionID );
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81 extern void vPortExceptionHandlerEntry( void *pvExceptionID );
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83 /*-----------------------------------------------------------*/
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85 /* vApplicationExceptionRegisterDump() is a callback function that the
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86 application can optionally define to receive a populated xPortRegisterDump
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87 structure. If the application chooses not to define a version of
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88 vApplicationExceptionRegisterDump() then this weekly defined default
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89 implementation will be called instead. */
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90 extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));
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91 void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
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93 ( void ) xRegisterDump;
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100 /*-----------------------------------------------------------*/
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102 void vPortExceptionHandler( void *pvExceptionID )
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104 extern void *pxCurrentTCB;
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106 /* Fill an xPortRegisterDump structure with the MicroBlaze context as it
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107 was immediately before the exception occurrence. */
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109 /* First fill in the name and handle of the task that was in the Running
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110 state when the exception occurred. */
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111 xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
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112 xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
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114 configASSERT( pulStackPointerOnFunctionEntry );
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116 /* Obtain the values of registers that were stacked prior to this function
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117 being called, and may have changed since they were stacked. */
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118 xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
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119 xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
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120 xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
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121 xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
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122 xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
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123 xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
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124 xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
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125 xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
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126 xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
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127 xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
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128 xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
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129 xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
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130 xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
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131 xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
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133 /* Obtain the value of all other registers. */
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134 xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
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135 xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
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136 xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
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137 xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
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138 xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
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139 xRegisterDump.ulR20 = mfgpr( R20 );
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140 xRegisterDump.ulR21 = mfgpr( R21 );
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141 xRegisterDump.ulR22 = mfgpr( R22 );
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142 xRegisterDump.ulR23 = mfgpr( R23 );
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143 xRegisterDump.ulR24 = mfgpr( R24 );
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144 xRegisterDump.ulR25 = mfgpr( R25 );
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145 xRegisterDump.ulR26 = mfgpr( R26 );
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146 xRegisterDump.ulR27 = mfgpr( R27 );
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147 xRegisterDump.ulR28 = mfgpr( R28 );
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148 xRegisterDump.ulR29 = mfgpr( R29 );
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149 xRegisterDump.ulR30 = mfgpr( R30 );
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150 xRegisterDump.ulR31 = mfgpr( R31 );
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151 xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
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152 xRegisterDump.ulEAR = mfear();
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153 xRegisterDump.ulESR = mfesr();
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154 xRegisterDump.ulEDR = mfedr();
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156 /* Move the saved program counter back to the instruction that was executed
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157 when the exception occurred. This is only valid for certain types of
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159 xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
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161 #if( XPAR_MICROBLAZE_USE_FPU != 0 )
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163 xRegisterDump.ulFSR = mffsr();
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167 xRegisterDump.ulFSR = 0UL;
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171 /* Also fill in a string that describes what type of exception this is.
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172 The string uses the same ID names as defined in the MicroBlaze standard
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173 library exception header files. */
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174 switch( ( uint32_t ) pvExceptionID )
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177 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
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180 case XEXC_ID_UNALIGNED_ACCESS :
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181 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
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184 case XEXC_ID_ILLEGAL_OPCODE :
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185 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
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188 case XEXC_ID_M_AXI_I_EXCEPTION :
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189 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
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192 case XEXC_ID_M_AXI_D_EXCEPTION :
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193 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
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196 case XEXC_ID_DIV_BY_ZERO :
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197 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
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200 case XEXC_ID_STACK_VIOLATION :
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201 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
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204 #if( XPAR_MICROBLAZE_USE_FPU != 0 )
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207 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
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210 #endif /* XPAR_MICROBLAZE_USE_FPU */
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213 /* vApplicationExceptionRegisterDump() is a callback function that the
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214 application can optionally define to receive the populated xPortRegisterDump
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215 structure. If the application chooses not to define a version of
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216 vApplicationExceptionRegisterDump() then the weekly defined default
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217 implementation within this file will be called instead. */
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218 vApplicationExceptionRegisterDump( &xRegisterDump );
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220 /* Must not attempt to leave this function! */
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226 /*-----------------------------------------------------------*/
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228 void vPortExceptionsInstallHandlers( void )
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230 static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
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232 if( ulHandlersAlreadyInstalled == pdFALSE )
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234 ulHandlersAlreadyInstalled = pdTRUE;
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236 #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
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237 microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
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238 #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
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240 #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
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241 microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
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242 #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
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244 #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
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245 microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
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246 #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
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248 #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
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249 microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
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250 #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
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252 #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
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253 microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
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254 #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
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256 #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
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257 microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
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258 #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
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260 #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
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261 microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
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262 #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
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264 #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
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265 microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
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266 #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
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268 #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
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269 microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
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270 #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
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272 microblaze_enable_exceptions();
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276 /* Exclude the entire file if the MicroBlaze is not configured to handle
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277 exceptions, or the application defined configuration item
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278 configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
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279 #endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
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