2 FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 /*-----------------------------------------------------------
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71 * Implementation of functions defined in portable.h for the MicroBlaze port.
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72 *----------------------------------------------------------*/
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75 /* Scheduler includes. */
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76 #include "FreeRTOS.h"
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79 /* Standard includes. */
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82 /* Hardware includes. */
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83 #include <xintc_i.h>
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84 #include <xil_exception.h>
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85 #include <microblaze_exceptions_g.h>
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87 /* Tasks are started with a critical section nesting of 0 - however, prior to
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88 the scheduler being commenced interrupts should not be enabled, so the critical
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89 nesting variable is initialised to a non-zero value. */
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90 #define portINITIAL_NESTING_VALUE ( 0xff )
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92 /* The bit within the MSR register that enabled/disables interrupts and
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93 exceptions respectively. */
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94 #define portMSR_IE ( 0x02U )
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95 #define portMSR_EE ( 0x100U )
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97 /* If the floating point unit is included in the MicroBlaze build, then the
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98 FSR register is saved as part of the task context. portINITIAL_FSR is the value
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99 given to the FSR register when the initial context is set up for a task being
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101 #define portINITIAL_FSR ( 0U )
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103 /*-----------------------------------------------------------*/
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106 * Initialise the interrupt controller instance.
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108 static int32_t prvInitialiseInterruptController( void );
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110 /* Ensure the interrupt controller instance variable is initialised before it is
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111 * used, and that the initialisation only happens once.
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113 static int32_t prvEnsureInterruptControllerIsInitialised( void );
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115 /*-----------------------------------------------------------*/
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117 /* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
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118 maintains its own count, so this variable is saved as part of the task
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120 volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
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122 /* This port uses a separate stack for interrupts. This prevents the stack of
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123 every task needing to be large enough to hold an entire interrupt stack on top
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124 of the task stack. */
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125 uint32_t *pulISRStack;
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127 /* If an interrupt requests a context switch, then ulTaskSwitchRequested will
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128 get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
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129 handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
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130 will call vTaskSwitchContext() to ensure the task that runs immediately after
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131 the interrupt exists is the highest priority task that is able to run. This is
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132 an unusual mechanism, but is used for this port because a single interrupt can
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133 cause the servicing of multiple peripherals - and it is inefficient to call
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134 vTaskSwitchContext() multiple times as each peripheral is serviced. */
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135 volatile uint32_t ulTaskSwitchRequested = 0UL;
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137 /* The instance of the interrupt controller used by this port. This is required
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138 by the Xilinx library API functions. */
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139 static XIntc xInterruptControllerInstance;
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141 /*-----------------------------------------------------------*/
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144 * Initialise the stack of a task to look exactly as if a call to
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145 * portSAVE_CONTEXT had been made.
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147 * See the portable.h header file.
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149 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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151 extern void *_SDA2_BASE_, *_SDA_BASE_;
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152 const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
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153 const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
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154 extern void _start1( void );
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156 /* Place a few bytes of known values on the bottom of the stack.
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157 This is essential for the Microblaze port and these lines must
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159 *pxTopOfStack = ( StackType_t ) 0x00000000;
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161 *pxTopOfStack = ( StackType_t ) 0x00000000;
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163 *pxTopOfStack = ( StackType_t ) 0x00000000;
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166 #if( XPAR_MICROBLAZE_USE_FPU != 0 )
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167 /* The FSR value placed in the initial task context is just 0. */
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168 *pxTopOfStack = portINITIAL_FSR;
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172 /* The MSR value placed in the initial task context should have interrupts
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173 disabled. Each task will enable interrupts automatically when it enters
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174 the running state for the first time. */
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175 *pxTopOfStack = mfmsr() & ~portMSR_IE;
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177 #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
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179 /* Ensure exceptions are enabled for the task. */
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180 *pxTopOfStack |= portMSR_EE;
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186 /* First stack an initial value for the critical section nesting. This
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187 is initialised to zero. */
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188 *pxTopOfStack = ( StackType_t ) 0x00;
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190 /* R0 is always zero. */
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191 /* R1 is the SP. */
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193 /* Place an initial value for all the general purpose registers. */
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195 *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */
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197 *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */
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199 *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */
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201 *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
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203 #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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205 *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. */
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207 *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */
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209 *pxTopOfStack = ( StackType_t ) NULL; /* R8 - other parameters and temporaries. */
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211 *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */
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213 *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */
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215 *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */
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217 *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */
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223 *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
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225 *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
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227 *pxTopOfStack = ( StackType_t ) _start1; /* R15 - return address for subroutine. */
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229 #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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231 *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */
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233 *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */
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235 *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */
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241 *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
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243 #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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245 *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */
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247 *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */
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249 *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */
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251 *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */
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253 *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */
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255 *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */
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257 *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */
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259 *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */
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261 *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */
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263 *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */
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265 *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */
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267 *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */
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270 pxTopOfStack -= 13;
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273 /* Return a pointer to the top of the stack that has been generated so this
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274 can be stored in the task control block for the task. */
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275 return pxTopOfStack;
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277 /*-----------------------------------------------------------*/
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279 BaseType_t xPortStartScheduler( void )
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281 extern void ( vPortStartFirstTask )( void );
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282 extern uint32_t _stack[];
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284 /* Setup the hardware to generate the tick. Interrupts are disabled when
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285 this function is called.
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287 This port uses an application defined callback function to install the tick
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288 interrupt handler because the kernel will run on lots of different
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289 MicroBlaze and FPGA configurations - not all of which will have the same
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290 timer peripherals defined or available. An example definition of
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291 vApplicationSetupTimerInterrupt() is provided in the official demo
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292 application that accompanies this port. */
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293 vApplicationSetupTimerInterrupt();
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295 /* Reuse the stack from main() as the stack for the interrupts/exceptions. */
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296 pulISRStack = ( uint32_t * ) _stack;
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298 /* Ensure there is enough space for the functions called from the interrupt
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299 service routines to write back into the stack frame of the caller. */
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302 /* Restore the context of the first task that is going to run. From here
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303 on, the created tasks will be executing. */
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304 vPortStartFirstTask();
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306 /* Should not get here as the tasks are now running! */
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309 /*-----------------------------------------------------------*/
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311 void vPortEndScheduler( void )
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313 /* Not implemented in ports where there is nothing to return to.
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314 Artificially force an assert. */
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315 configASSERT( uxCriticalNesting == 1000UL );
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317 /*-----------------------------------------------------------*/
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320 * Manual context switch called by portYIELD or taskYIELD.
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322 void vPortYield( void )
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324 extern void VPortYieldASM( void );
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326 /* Perform the context switch in a critical section to assure it is
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327 not interrupted by the tick ISR. It is not a problem to do this as
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328 each task maintains its own interrupt status. */
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329 portENTER_CRITICAL();
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331 /* Jump directly to the yield function to ensure there is no
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332 compiler generated prologue code. */
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333 asm volatile ( "bralid r14, VPortYieldASM \n\t" \
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334 "or r0, r0, r0 \n\t" );
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336 portEXIT_CRITICAL();
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338 /*-----------------------------------------------------------*/
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340 void vPortEnableInterrupt( uint8_t ucInterruptID )
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344 /* An API function is provided to enable an interrupt in the interrupt
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345 controller because the interrupt controller instance variable is private
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347 lReturn = prvEnsureInterruptControllerIsInitialised();
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348 if( lReturn == pdPASS )
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350 XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
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353 configASSERT( lReturn );
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355 /*-----------------------------------------------------------*/
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357 void vPortDisableInterrupt( uint8_t ucInterruptID )
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361 /* An API function is provided to disable an interrupt in the interrupt
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362 controller because the interrupt controller instance variable is private
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364 lReturn = prvEnsureInterruptControllerIsInitialised();
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366 if( lReturn == pdPASS )
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368 XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
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371 configASSERT( lReturn );
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373 /*-----------------------------------------------------------*/
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375 BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
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379 /* An API function is provided to install an interrupt handler because the
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380 interrupt controller instance variable is private to this file. */
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382 lReturn = prvEnsureInterruptControllerIsInitialised();
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384 if( lReturn == pdPASS )
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386 lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
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389 if( lReturn == XST_SUCCESS )
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394 configASSERT( lReturn == pdPASS );
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398 /*-----------------------------------------------------------*/
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400 static int32_t prvEnsureInterruptControllerIsInitialised( void )
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402 static int32_t lInterruptControllerInitialised = pdFALSE;
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405 /* Ensure the interrupt controller instance variable is initialised before
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406 it is used, and that the initialisation only happens once. */
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407 if( lInterruptControllerInitialised != pdTRUE )
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409 lReturn = prvInitialiseInterruptController();
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411 if( lReturn == pdPASS )
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413 lInterruptControllerInitialised = pdTRUE;
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423 /*-----------------------------------------------------------*/
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426 * Handler for the timer interrupt. This is the handler that the application
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427 * defined callback function vApplicationSetupTimerInterrupt() should install.
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429 void vPortTickISR( void *pvUnused )
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431 extern void vApplicationClearTimerInterrupt( void );
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433 /* Ensure the unused parameter does not generate a compiler warning. */
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436 /* This port uses an application defined callback function to clear the tick
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437 interrupt because the kernel will run on lots of different MicroBlaze and
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438 FPGA configurations - not all of which will have the same timer peripherals
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439 defined or available. An example definition of
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440 vApplicationClearTimerInterrupt() is provided in the official demo
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441 application that accompanies this port. */
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442 vApplicationClearTimerInterrupt();
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444 /* Increment the RTOS tick - this might cause a task to unblock. */
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445 if( xTaskIncrementTick() != pdFALSE )
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447 /* Force vTaskSwitchContext() to be called as the interrupt exits. */
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448 ulTaskSwitchRequested = 1;
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451 /*-----------------------------------------------------------*/
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453 static int32_t prvInitialiseInterruptController( void )
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457 lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
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459 if( lStatus == XST_SUCCESS )
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461 /* Initialise the exception table. */
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462 Xil_ExceptionInit();
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464 /* Service all pending interrupts each time the handler is entered. */
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465 XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
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467 /* Install exception handlers if the MicroBlaze is configured to handle
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468 exceptions, and the application defined constant
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469 configINSTALL_EXCEPTION_HANDLERS is set to 1. */
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470 #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
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472 vPortExceptionsInstallHandlers();
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474 #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
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476 /* Start the interrupt controller. Interrupts are enabled when the
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477 scheduler starts. */
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478 lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
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480 if( lStatus == XST_SUCCESS )
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490 configASSERT( lStatus == pdPASS );
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494 /*-----------------------------------------------------------*/
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