git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/NiosII/port_asm.S

   1 /*\r
   2     FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.\r
   3         \r
   4 \r
   5     ***************************************************************************\r
   6      *                                                                       *\r
   7      *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
   8      *    Complete, revised, and edited pdf reference manuals are also       *\r
   9      *    available.                                                         *\r
  10      *                                                                       *\r
  11      *    Purchasing FreeRTOS documentation will not only help you, by       *\r
  12      *    ensuring you get running as quickly as possible and with an        *\r
  13      *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
  14      *    the FreeRTOS project to continue with its mission of providing     *\r
  15      *    professional grade, cross platform, de facto standard solutions    *\r
  16      *    for microcontrollers - completely free of charge!                  *\r
  17      *                                                                       *\r
  18      *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
  19      *                                                                       *\r
  20      *    Thank you for using FreeRTOS, and thank you for your support!      *\r
  21      *                                                                       *\r
  22     ***************************************************************************\r
  23 \r
  24 \r
  25     This file is part of the FreeRTOS distribution.\r
  26 \r
  27     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  28     the terms of the GNU General Public License (version 2) as published by the\r
  29     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
  30     >>>NOTE<<< The modification to the GPL is included to allow you to\r
  31     distribute a combined work that includes FreeRTOS without being obliged to\r
  32     provide the source code for proprietary components outside of the FreeRTOS\r
  33     kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
  34     WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
  35     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
  36     more details. You should have received a copy of the GNU General Public\r
  37     License and the FreeRTOS license exception along with FreeRTOS; if not it\r
  38     can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
  39     by writing to Richard Barry, contact details for whom are available on the\r
  40     FreeRTOS WEB site.\r
  41 \r
  42     1 tab == 4 spaces!\r
  43     \r
  44     ***************************************************************************\r
  45      *                                                                       *\r
  46      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  47      *    not run, what could be wrong?                                      *\r
  48      *                                                                       *\r
  49      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  50      *                                                                       *\r
  51     ***************************************************************************\r
  52 \r
  53     \r
  54     http://www.FreeRTOS.org - Documentation, training, latest information, \r
  55     license and contact details.\r
  56     \r
  57     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  58     including FreeRTOS+Trace - an indispensable productivity tool.\r
  59 \r
  60     Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
  61     the code with commercial support, indemnification, and middleware, under \r
  62     the OpenRTOS brand: http://www.OpenRTOS.com.  High Integrity Systems also\r
  63     provide a safety engineered and independently SIL3 certified version under \r
  64     the SafeRTOS brand: http://www.SafeRTOS.com.\r
  65 */\r
  66 \r
  67 .extern         vTaskSwitchContext\r
  68         \r
  69 .set noat\r
  70 \r
  71 # Exported to start the first task.\r
  72 .globl restore_sp_from_pxCurrentTCB             \r
  73         \r
  74 # Entry point for exceptions.\r
  75 .section .exceptions.entry, "xa"                \r
  76 \r
  77 # Save the entire context of a task.\r
  78 save_context:\r
  79         addi    ea, ea, -4                      # Point to the next instruction.\r
  80         addi    sp,     sp, -116                # Create space on the stack.\r
  81         stw             ra, 0(sp)\r
  82                                                                 # Leave a gap for muldiv 0\r
  83         stw             at, 8(sp)                \r
  84         stw             r2, 12(sp)\r
  85         stw             r3, 16(sp)\r
  86         stw             r4, 20(sp)\r
  87         stw             r5, 24(sp) \r
  88         stw             r6, 28(sp) \r
  89         stw             r7, 32(sp) \r
  90         stw             r8, 36(sp) \r
  91         stw             r9, 40(sp) \r
  92         stw             r10, 44(sp)\r
  93         stw             r11, 48(sp)\r
  94         stw             r12, 52(sp)\r
  95         stw             r13, 56(sp)\r
  96         stw             r14, 60(sp)\r
  97         stw             r15, 64(sp)\r
  98         rdctl   r5, estatus             # Save the eStatus\r
  99         stw             r5, 68(sp)\r
 100         stw             ea, 72(sp)                      # Save the PC\r
 101         stw             r16, 76(sp)                     # Save the remaining registers\r
 102         stw             r17, 80(sp)\r
 103         stw             r18, 84(sp)\r
 104         stw             r19, 88(sp)\r
 105         stw             r20, 92(sp)\r
 106         stw             r21, 96(sp)\r
 107         stw             r22, 100(sp)\r
 108         stw             r23, 104(sp)\r
 109         stw             gp, 108(sp)\r
 110         stw             fp, 112(sp)\r
 111 \r
 112 save_sp_to_pxCurrentTCB:\r
 113         movia   et, pxCurrentTCB        # Load the address of the pxCurrentTCB pointer\r
 114         ldw             et, (et)                        # Load the value of the pxCurrentTCB pointer\r
 115         stw             sp, (et)                        # Store the stack pointer into the top of the TCB\r
 116         \r
 117         .section .exceptions.irqtest, "xa"      \r
 118 hw_irq_test:\r
 119         /*\r
 120      * Test to see if the exception was a software exception or caused \r
 121      * by an external interrupt, and vector accordingly.\r
 122      */\r
 123     rdctl       r4, ipending            # Load the Pending Interrupts indication\r
 124         rdctl   r5, estatus             # Load the eStatus (enabled interrupts).\r
 125     andi        r2, r5, 1                       # Are interrupts enabled globally.\r
 126     beq         r2, zero, soft_exceptions               # Interrupts are not enabled.\r
 127     beq         r4, zero, soft_exceptions               # There are no interrupts triggered.\r
 128 \r
 129         .section .exceptions.irqhandler, "xa"\r
 130 hw_irq_handler:\r
 131         call    alt_irq_handler                                 # Call the alt_irq_handler to deliver to the registered interrupt handler.\r
 132 \r
 133     .section .exceptions.irqreturn, "xa"\r
 134 restore_sp_from_pxCurrentTCB:\r
 135         movia   et, pxCurrentTCB                # Load the address of the pxCurrentTCB pointer\r
 136         ldw             et, (et)                                # Load the value of the pxCurrentTCB pointer\r
 137         ldw             sp, (et)                                # Load the stack pointer with the top value of the TCB\r
 138 \r
 139 restore_context:\r
 140         ldw             ra, 0(sp)               # Restore the registers.\r
 141                                                         # Leave a gap for muldiv 0.\r
 142         ldw             at, 8(sp)\r
 143         ldw             r2, 12(sp)\r
 144         ldw             r3, 16(sp)\r
 145         ldw             r4, 20(sp)\r
 146         ldw             r5, 24(sp) \r
 147         ldw             r6, 28(sp) \r
 148         ldw             r7, 32(sp) \r
 149         ldw             r8, 36(sp) \r
 150         ldw             r9, 40(sp) \r
 151         ldw             r10, 44(sp)\r
 152         ldw             r11, 48(sp)\r
 153         ldw             r12, 52(sp)\r
 154         ldw             r13, 56(sp)\r
 155         ldw             r14, 60(sp)\r
 156         ldw             r15, 64(sp)\r
 157         ldw             et, 68(sp)              # Load the eStatus\r
 158         wrctl   estatus, et     # Write the eStatus\r
 159         ldw             ea, 72(sp)              # Load the Program Counter\r
 160         ldw             r16, 76(sp)\r
 161         ldw             r17, 80(sp)\r
 162         ldw             r18, 84(sp)\r
 163         ldw             r19, 88(sp)\r
 164         ldw             r20, 92(sp)\r
 165         ldw             r21, 96(sp)\r
 166         ldw             r22, 100(sp)\r
 167         ldw             r23, 104(sp)\r
 168         ldw             gp, 108(sp)\r
 169         ldw             fp, 112(sp)\r
 170         addi    sp,     sp, 116         # Release stack space\r
 171 \r
 172     eret                                        # Return to address ea, loading eStatus into Status.\r
 173    \r
 174         .section .exceptions.soft, "xa"\r
 175 soft_exceptions:\r
 176         ldw             et, 0(ea)                               # Load the instruction where the interrupt occured.\r
 177         movhi   at, %hi(0x003B683A)             # Load the registers with the trap instruction code\r
 178         ori             at, at, %lo(0x003B683A)\r
 179         cmpne   et, et, at                              # Compare the trap instruction code to the last excuted instruction\r
 180         beq             et, r0, call_scheduler  # its a trap so switchcontext\r
 181         break                                                   # This is an un-implemented instruction or muldiv problem.\r
 182         br              restore_context                 # its something else\r
 183 \r
 184 call_scheduler:\r
 185         addi    ea, ea, 4                                               # A trap was called, increment the program counter so it is not called again.\r
 186         stw             ea, 72(sp)                                              # Save the new program counter to the context.\r
 187         call    vTaskSwitchContext                              # Pick the next context.\r
 188         br              restore_sp_from_pxCurrentTCB    # Switch in the task context and restore. \r