2 * FreeRTOS Kernel V10.1.1
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3 * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 #if __riscv_xlen == 64
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29 #error Not implemented yet - change lw to ld, and sw to sd.
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30 #define portWORD_SIZE 8
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31 #elif __riscv_xlen == 32
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32 #define portWORD_SIZE 4
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34 #error Assembler did not define __riscv_xlen
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38 * The FreeRTOS kernel's RISC-V port is split between the the code that is
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39 * common across all currently supported RISC-V chips (implementations of the
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40 * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
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42 * + The code that is common to all RISC-V chips is implemented in
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43 * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
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44 * portASM.S file because the same file is used no matter which RISC-V chip is
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47 * + The code that tailors the kernel's RISC-V port to a specific RISC-V
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48 * chip is implemented in freertos_risc_v_chip_specific_extensions.h. There
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49 * is one freertos_risc_v_chip_specific_extensions.h that can be used with any
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50 * RISC-V chip that both includes a standard CLINT and does not add to the
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51 * base set of RISC-V registers. There are additional
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52 * freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
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53 * that do not include a standard CLINT or do add to the base set of RISC-V
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56 * CARE MUST BE TAKEN TO INCLDUE THE CORRECT
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57 * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
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58 * IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h
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59 * header file ensure the path to the correct header file is in the assembler's
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62 * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
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63 * that include a standard CLINT and do not add to the base set of RISC-V
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67 #include "freertos_risc_v_chip_specific_extensions.h"
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69 /* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
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71 #ifndef portasmHAS_CLINT
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72 #error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_CLINT to either 1 (CLINT present) or 0 (clint not present).
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75 #ifndef portasmHANDLE_INTERRUPT
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76 #error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file.
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79 /* Only the standard core registers are stored by default. Any additional
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80 registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
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81 portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
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82 specific version of freertos_risc_v_chip_specific_extensions.h. See the notes
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83 at the top of this file. */
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84 #define portCONTEXT_SIZE ( 30 * portWORD_SIZE )
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86 .global xPortStartFirstTask
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87 .global freertos_risc_v_trap_handler
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88 .global pxPortInitialiseStack
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89 .extern pxCurrentTCB
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90 .extern ulPortTrapHandler
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91 .extern vTaskSwitchContext
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92 .extern Timer_IRQHandler
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93 .extern pullMachineTimerCompareRegister
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94 .extern pullNextTime
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95 .extern ulTimerIncrementsForOneTick
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96 .extern xISRStackTop
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98 /*-----------------------------------------------------------*/
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102 freertos_risc_v_trap_handler:
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103 addi sp, sp, -portCONTEXT_SIZE
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104 sw x1, 1 * portWORD_SIZE( sp )
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105 sw x5, 2 * portWORD_SIZE( sp )
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106 sw x6, 3 * portWORD_SIZE( sp )
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107 sw x7, 4 * portWORD_SIZE( sp )
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108 sw x8, 5 * portWORD_SIZE( sp )
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109 sw x9, 6 * portWORD_SIZE( sp )
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110 sw x10, 7 * portWORD_SIZE( sp )
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111 sw x11, 8 * portWORD_SIZE( sp )
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112 sw x12, 9 * portWORD_SIZE( sp )
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113 sw x13, 10 * portWORD_SIZE( sp )
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114 sw x14, 11 * portWORD_SIZE( sp )
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115 sw x15, 12 * portWORD_SIZE( sp )
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116 sw x16, 13 * portWORD_SIZE( sp )
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117 sw x17, 14 * portWORD_SIZE( sp )
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118 sw x18, 15 * portWORD_SIZE( sp )
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119 sw x19, 16 * portWORD_SIZE( sp )
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120 sw x20, 17 * portWORD_SIZE( sp )
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121 sw x21, 18 * portWORD_SIZE( sp )
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122 sw x22, 19 * portWORD_SIZE( sp )
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123 sw x23, 20 * portWORD_SIZE( sp )
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124 sw x24, 21 * portWORD_SIZE( sp )
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125 sw x25, 22 * portWORD_SIZE( sp )
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126 sw x26, 23 * portWORD_SIZE( sp )
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127 sw x27, 24 * portWORD_SIZE( sp )
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128 sw x28, 25 * portWORD_SIZE( sp )
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129 sw x29, 26 * portWORD_SIZE( sp )
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130 sw x30, 27 * portWORD_SIZE( sp )
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131 sw x31, 28 * portWORD_SIZE( sp )
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133 csrr t0, mstatus /* Required for MPIE bit. */
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134 sw t0, 29 * portWORD_SIZE( sp )
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136 portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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138 lw t0, pxCurrentTCB /* Load pxCurrentTCB. */
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139 sw sp, 0( t0 ) /* Write sp to first TCB member. */
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144 test_if_asynchronous:
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145 srli a2, a0, 0x1f /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */
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146 beq a2, x0, handle_synchronous /* Branch past interrupt handing if not asynchronous. */
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147 sw a1, 0( sp ) /* Asynch so save unmodified exception return address. */
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149 handle_asynchronous:
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151 #if( portasmHAS_CLINT != 0 )
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153 test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
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155 addi t1, t0, 7 /* 0x80000007 == machine timer interrupt. */
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156 bne a0, t1, test_if_external_interrupt
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158 lw t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */
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159 lw t1, pullNextTime /* Load the address of ullNextTime into t1. */
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160 lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */
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161 lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */
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162 sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */
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163 sw t3, 4(t0) /* Store high word of ullNextTime into compare register. */
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164 lw t0, ulTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
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165 add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits. */
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166 sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */
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167 add t6, t3, t5 /* Add overflow to high word of ullNextTime. */
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168 sw t4, 0(t1) /* Store new low word of ullNextTime. */
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169 sw t6, 4(t1) /* Store new high word of ullNextTime. */
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170 lw sp, xISRStackTop /* Switch to ISR stack before function call. */
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171 jal xTaskIncrementTick
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172 beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */
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173 jal vTaskSwitchContext
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176 test_if_external_interrupt: /* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */
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177 addi t1, t1, 4 /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
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178 bne a0, t1, as_yet_unhandled /* Something as yet unhandled. */
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180 #endif /* portasmHAS_CLINT */
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182 lw sp, xISRStackTop /* Switch to ISR stack before function call. */
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183 jal portasmHANDLE_INTERRUPT /* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */
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186 handle_synchronous:
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187 addi a1, a1, 4 /* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */
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188 sw a1, 0( sp ) /* Save updated exception return address. */
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190 test_if_environment_call:
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191 li t0, 11 /* 11 == environment call. */
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192 bne a0, t0, is_exception /* Not an M environment call, so some other exception. */
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193 lw sp, xISRStackTop /* Switch to ISR stack before function call. */
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194 jal vTaskSwitchContext
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206 lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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207 lw sp, 0( sp ) /* Read sp from first TCB member. */
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209 /* Load mret with the address of the next instruction in the task to run next. */
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213 portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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215 /* Load mstatus with the interrupt enable bits used by the task. */
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216 lw t0, 29 * portWORD_SIZE( sp )
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217 csrw mstatus, t0 /* Required for MPIE bit. */
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219 lw x1, 1 * portWORD_SIZE( sp )
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220 lw x5, 2 * portWORD_SIZE( sp ) /* t0 */
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221 lw x6, 3 * portWORD_SIZE( sp ) /* t1 */
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222 lw x7, 4 * portWORD_SIZE( sp ) /* t2 */
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223 lw x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
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224 lw x9, 6 * portWORD_SIZE( sp ) /* s1 */
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225 lw x10, 7 * portWORD_SIZE( sp ) /* a0 */
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226 lw x11, 8 * portWORD_SIZE( sp ) /* a1 */
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227 lw x12, 9 * portWORD_SIZE( sp ) /* a2 */
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228 lw x13, 10 * portWORD_SIZE( sp ) /* a3 */
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229 lw x14, 11 * portWORD_SIZE( sp ) /* a4 */
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230 lw x15, 12 * portWORD_SIZE( sp ) /* a5 */
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231 lw x16, 13 * portWORD_SIZE( sp ) /* a6 */
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232 lw x17, 14 * portWORD_SIZE( sp ) /* a7 */
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233 lw x18, 15 * portWORD_SIZE( sp ) /* s2 */
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234 lw x19, 16 * portWORD_SIZE( sp ) /* s3 */
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235 lw x20, 17 * portWORD_SIZE( sp ) /* s4 */
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236 lw x21, 18 * portWORD_SIZE( sp ) /* s5 */
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237 lw x22, 19 * portWORD_SIZE( sp ) /* s6 */
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238 lw x23, 20 * portWORD_SIZE( sp ) /* s7 */
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239 lw x24, 21 * portWORD_SIZE( sp ) /* s8 */
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240 lw x25, 22 * portWORD_SIZE( sp ) /* s9 */
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241 lw x26, 23 * portWORD_SIZE( sp ) /* s10 */
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242 lw x27, 24 * portWORD_SIZE( sp ) /* s11 */
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243 lw x28, 25 * portWORD_SIZE( sp ) /* t3 */
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244 lw x29, 26 * portWORD_SIZE( sp ) /* t4 */
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245 lw x30, 27 * portWORD_SIZE( sp ) /* t5 */
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246 lw x31, 28 * portWORD_SIZE( sp ) /* t6 */
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247 addi sp, sp, portCONTEXT_SIZE
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251 /*-----------------------------------------------------------*/
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255 xPortStartFirstTask:
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257 #if( portasmHAS_CLINT != 0 )
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258 /* If there is a clint then interrupts can branch directly to the FreeRTOS
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259 trap handler. Otherwise the interrupt controller will need to be configured
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260 outside of this file. */
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261 la t0, freertos_risc_v_trap_handler
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263 #endif /* portasmHAS_CLILNT */
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265 lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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266 lw sp, 0( sp ) /* Read sp from first TCB member. */
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268 lw x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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270 portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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272 lw t0, 29 * portWORD_SIZE( sp ) /* mstatus */
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273 csrrw x0, mstatus, t0 /* Interrupts enabled from here! */
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275 lw x5, 2 * portWORD_SIZE( sp ) /* t0 */
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276 lw x6, 3 * portWORD_SIZE( sp ) /* t1 */
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277 lw x7, 4 * portWORD_SIZE( sp ) /* t2 */
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278 lw x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
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279 lw x9, 6 * portWORD_SIZE( sp ) /* s1 */
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280 lw x10, 7 * portWORD_SIZE( sp ) /* a0 */
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281 lw x11, 8 * portWORD_SIZE( sp ) /* a1 */
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282 lw x12, 9 * portWORD_SIZE( sp ) /* a2 */
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283 lw x13, 10 * portWORD_SIZE( sp ) /* a3 */
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284 lw x14, 11 * portWORD_SIZE( sp ) /* a4 */
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285 lw x15, 12 * portWORD_SIZE( sp ) /* a5 */
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286 lw x16, 13 * portWORD_SIZE( sp ) /* a6 */
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287 lw x17, 14 * portWORD_SIZE( sp ) /* a7 */
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288 lw x18, 15 * portWORD_SIZE( sp ) /* s2 */
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289 lw x19, 16 * portWORD_SIZE( sp ) /* s3 */
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290 lw x20, 17 * portWORD_SIZE( sp ) /* s4 */
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291 lw x21, 18 * portWORD_SIZE( sp ) /* s5 */
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292 lw x22, 19 * portWORD_SIZE( sp ) /* s6 */
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293 lw x23, 20 * portWORD_SIZE( sp ) /* s7 */
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294 lw x24, 21 * portWORD_SIZE( sp ) /* s8 */
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295 lw x25, 22 * portWORD_SIZE( sp ) /* s9 */
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296 lw x26, 23 * portWORD_SIZE( sp ) /* s10 */
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297 lw x27, 24 * portWORD_SIZE( sp ) /* s11 */
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298 lw x28, 25 * portWORD_SIZE( sp ) /* t3 */
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299 lw x29, 26 * portWORD_SIZE( sp ) /* t4 */
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300 lw x30, 27 * portWORD_SIZE( sp ) /* t5 */
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301 lw x31, 28 * portWORD_SIZE( sp ) /* t6 */
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302 addi sp, sp, portCONTEXT_SIZE
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305 /*-----------------------------------------------------------*/
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308 * Unlike other ports pxPortInitialiseStack() is written in assembly code as it
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309 * needs access to the portasmADDITIONAL_CONTEXT_SIZE constant. The prototype
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310 * for the function is as per the other ports:
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311 * StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
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313 * As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
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314 * a1, and pvParameters in a2. The new top of stack is passed out in a0.
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316 * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
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317 * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
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319 * Register ABI Name Description Saver
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320 * x0 zero Hard-wired zero -
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321 * x1 ra Return address Caller
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322 * x2 sp Stack pointer Callee
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323 * x3 gp Global pointer -
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324 * x4 tp Thread pointer -
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325 * x5-7 t0-2 Temporaries Caller
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326 * x8 s0/fp Saved register/Frame pointer Callee
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327 * x9 s1 Saved register Callee
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328 * x10-11 a0-1 Function Arguments/return values Caller
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329 * x12-17 a2-7 Function arguments Caller
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330 * x18-27 s2-11 Saved registers Callee
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331 * x28-31 t3-6 Temporaries Caller
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333 * The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
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334 * where the global and thread pointers are currently assumed to be constant so
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365 * portTASK_RETURN_ADDRESS
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366 * [chip specific registers go here]
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371 pxPortInitialiseStack:
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373 csrr t0, mstatus /* Obtain current mstatus value. */
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374 addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
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376 or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
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378 addi a0, a0, -portWORD_SIZE
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379 sw t0, 0(a0) /* mstatus onto the stack. */
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380 addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */
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381 sw a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
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382 addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */
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383 sw x0, 0(a0) /* Return address onto the stack, could be portTASK_RETURN_ADDRESS */
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384 addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
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385 chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
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386 beq t0, x0, 1f /* No more chip specific registers to save. */
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387 addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
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388 sw x0, 0(a0) /* Give the chip specific register an initial value of zero. */
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389 addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
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390 j chip_specific_stack_frame /* Until no more chip specific registers. */
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392 addi a0, a0, -portWORD_SIZE
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393 sw a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
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396 /*-----------------------------------------------------------*/
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