2 * FreeRTOS Kernel V10.1.1
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3 * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and t
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11 o permit persons to whom the Software is furnished to do so,
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12 * subject to the following conditions:
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14 * The above copyright notice and this permission notice shall be included in all
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15 * copies or substantial portions of the Software.
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17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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24 * http://www.FreeRTOS.org
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25 * http://aws.amazon.com/freertos
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27 * 1 tab == 4 spaces!
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30 #if __riscv_xlen == 64
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31 #error Not implemented yet - change lw to ld, and sw to sd.
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33 #elif __riscv_xlen == 32
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36 #error Assembler has not defined __riscv_xlen
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39 #define CONTEXT_SIZE ( 28 * WORD_SIZE )
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41 .global xPortStartScheduler
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42 .global vPortTrapHandler
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43 .extern pxCurrentTCB
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46 /*-----------------------------------------------------------*/
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49 xPortStartScheduler:
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50 lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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51 lw sp, 0( sp ) /* Read sp from first TCB member. */
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53 lw x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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54 lw x5, 2 * WORD_SIZE( sp ) /* t0 */
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55 lw x6, 3 * WORD_SIZE( sp ) /* t1 */
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56 lw x7, 4 * WORD_SIZE( sp ) /* t2 */
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57 lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
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58 lw x9, 6 * WORD_SIZE( sp ) /* s1 */
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59 lw x10, 7 * WORD_SIZE( sp ) /* a0 */
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60 lw x11, 8 * WORD_SIZE( sp ) /* a1 */
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61 lw x12, 9 * WORD_SIZE( sp ) /* a2 */
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62 lw x13, 10 * WORD_SIZE( sp ) /* a3 */
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63 lw x14, 11 * WORD_SIZE( sp ) /* a4 */
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64 lw x15, 12 * WORD_SIZE( sp ) /* a5 */
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65 lw x16, 13 * WORD_SIZE( sp ) /* a6 */
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66 lw x17, 14 * WORD_SIZE( sp ) /* a7 */
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67 lw x18, 15 * WORD_SIZE( sp ) /* s2 */
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68 lw x19, 16 * WORD_SIZE( sp ) /* s3 */
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69 lw x20, 17 * WORD_SIZE( sp ) /* s4 */
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70 lw x21, 18 * WORD_SIZE( sp ) /* s5 */
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71 lw x22, 19 * WORD_SIZE( sp ) /* s6 */
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72 lw x23, 20 * WORD_SIZE( sp ) /* s7 */
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73 lw x24, 21 * WORD_SIZE( sp ) /* s8 */
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74 lw x25, 22 * WORD_SIZE( sp ) /* s9 */
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75 lw x26, 23 * WORD_SIZE( sp ) /* s10 */
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76 lw x27, 24 * WORD_SIZE( sp ) /* s11 */
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77 lw x28, 25 * WORD_SIZE( sp ) /* t3 */
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78 lw x29, 26 * WORD_SIZE( sp ) /* t4 */
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79 lw x30, 27 * WORD_SIZE( sp ) /* t5 */
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80 lw x31, 28 * WORD_SIZE( sp ) /* t6 */
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81 addi sp, sp, CONTEXT_SIZE
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82 csrs mstatus, 8 /* Enable machine interrupts. */
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83 csrs mie, 8 /* Enable soft interrupt. */
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86 /*-----------------------------------------------------------*/
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90 addi sp, sp, -CONTEXT_SIZE
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92 sw x5, 2 * WORD_SIZE( sp )
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93 sw x6, 3 * WORD_SIZE( sp )
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94 sw x7, 4 * WORD_SIZE( sp )
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95 sw x8, 5 * WORD_SIZE( sp )
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96 sw x9, 6 * WORD_SIZE( sp )
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97 sw x10, 7 * WORD_SIZE( sp )
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98 sw x11, 8 * WORD_SIZE( sp )
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99 sw x12, 9 * WORD_SIZE( sp )
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100 sw x13, 10 * WORD_SIZE( sp )
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101 sw x14, 11 * WORD_SIZE( sp )
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102 sw x15, 12 * WORD_SIZE( sp )
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103 sw x16, 13 * WORD_SIZE( sp )
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104 sw x17, 14 * WORD_SIZE( sp )
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105 sw x18, 15 * WORD_SIZE( sp )
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106 sw x19, 16 * WORD_SIZE( sp )
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107 sw x20, 17 * WORD_SIZE( sp )
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108 sw x21, 18 * WORD_SIZE( sp )
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109 sw x22, 19 * WORD_SIZE( sp )
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110 sw x23, 20 * WORD_SIZE( sp )
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111 sw x24, 21 * WORD_SIZE( sp )
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112 sw x25, 22 * WORD_SIZE( sp )
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113 sw x26, 23 * WORD_SIZE( sp )
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114 sw x27, 24 * WORD_SIZE( sp )
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115 sw x28, 25 * WORD_SIZE( sp )
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116 sw x29, 26 * WORD_SIZE( sp )
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117 sw x30, 27 * WORD_SIZE( sp )
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118 sw x31, 28 * WORD_SIZE( sp )
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120 /* Save exception return address. */
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124 lw t0, pxCurrentTCB /* Load pxCurrentTCB. */
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125 sw sp, 0( t0 ) /* Write sp from first TCB member. */
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133 # Remain in M-mode after mret
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134 li t0, 0x00001800 /* MSTATUS MPP */
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137 lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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138 lw sp, 0( sp ) /* Read sp from first TCB member. */
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140 /* Load mret with the address of the first task. */
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145 lw x5, 2 * WORD_SIZE( sp ) /* t0 */
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146 lw x6, 3 * WORD_SIZE( sp ) /* t1 */
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147 lw x7, 4 * WORD_SIZE( sp ) /* t2 */
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148 lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
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149 lw x9, 6 * WORD_SIZE( sp ) /* s1 */
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150 lw x10, 7 * WORD_SIZE( sp ) /* a0 */
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151 lw x11, 8 * WORD_SIZE( sp ) /* a1 */
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152 lw x12, 9 * WORD_SIZE( sp ) /* a2 */
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153 lw x13, 10 * WORD_SIZE( sp ) /* a3 */
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154 lw x14, 11 * WORD_SIZE( sp ) /* a4 */
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155 lw x15, 12 * WORD_SIZE( sp ) /* a5 */
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156 lw x16, 13 * WORD_SIZE( sp ) /* a6 */
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157 lw x17, 14 * WORD_SIZE( sp ) /* a7 */
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158 lw x18, 15 * WORD_SIZE( sp ) /* s2 */
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159 lw x19, 16 * WORD_SIZE( sp ) /* s3 */
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160 lw x20, 17 * WORD_SIZE( sp ) /* s4 */
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161 lw x21, 18 * WORD_SIZE( sp ) /* s5 */
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162 lw x22, 19 * WORD_SIZE( sp ) /* s6 */
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163 lw x23, 20 * WORD_SIZE( sp ) /* s7 */
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164 lw x24, 21 * WORD_SIZE( sp ) /* s8 */
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165 lw x25, 22 * WORD_SIZE( sp ) /* s9 */
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166 lw x26, 23 * WORD_SIZE( sp ) /* s10 */
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167 lw x27, 24 * WORD_SIZE( sp ) /* s11 */
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168 lw x28, 25 * WORD_SIZE( sp ) /* t3 */
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169 lw x29, 26 * WORD_SIZE( sp ) /* t4 */
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170 lw x30, 27 * WORD_SIZE( sp ) /* t5 */
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171 lw x31, 28 * WORD_SIZE( sp ) /* t6 */
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172 addi sp, sp, CONTEXT_SIZE
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