2 FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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13 >>! NOTE: The modification to the GPL is included to allow you to !<<
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14 >>! distribute a combined work that includes FreeRTOS without being !<<
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15 >>! obliged to provide the source code for proprietary components !<<
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16 >>! outside of the FreeRTOS kernel. !<<
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18 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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19 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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20 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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21 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * Having a problem? Start by reading the FAQ "My application does *
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28 * not run, what could be wrong?". Have you defined configASSERT()? *
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30 * http://www.FreeRTOS.org/FAQHelp.html *
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32 ***************************************************************************
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34 ***************************************************************************
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36 * FreeRTOS provides completely free yet professionally developed, *
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37 * robust, strictly quality controlled, supported, and cross *
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38 * platform software that is more than just the market leader, it *
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39 * is the industry's de facto standard. *
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41 * Help yourself get started quickly while simultaneously helping *
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42 * to support the FreeRTOS project by purchasing a FreeRTOS *
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43 * tutorial book, reference manual, or both: *
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44 * http://www.FreeRTOS.org/Documentation *
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46 ***************************************************************************
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48 ***************************************************************************
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50 * Investing in training allows your team to be as productive as *
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51 * possible as early as possible, lowering your overall development *
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52 * cost, and enabling you to bring a more robust product to market *
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53 * earlier than would otherwise be possible. Richard Barry is both *
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54 * the architect and key author of FreeRTOS, and so also the world's *
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55 * leading authority on what is the world's most popular real time *
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56 * kernel for deeply embedded MCU designs. Obtaining your training *
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57 * from Richard ensures your team will gain directly from his in-depth *
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58 * product knowledge and years of usage experience. Contact Real Time *
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59 * Engineers Ltd to enquire about the FreeRTOS Masterclass, presented *
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60 * by Richard Barry: http://www.FreeRTOS.org/contact
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62 ***************************************************************************
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64 ***************************************************************************
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66 * You are receiving this top quality software for free. Please play *
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67 * fair and reciprocate by reporting any suspected issues and *
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68 * participating in the community forum: *
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69 * http://www.FreeRTOS.org/support *
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73 ***************************************************************************
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75 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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76 license and Real Time Engineers Ltd. contact details.
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78 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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79 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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80 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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82 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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83 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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85 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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86 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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87 licenses offer ticketed support, indemnification and commercial middleware.
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89 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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90 engineered and independently SIL3 certified version for use in safety and
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91 mission critical applications that require provable dependability.
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96 /*-----------------------------------------------------------
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97 * Implementation of functions defined in portable.h for the SH2A port.
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98 *----------------------------------------------------------*/
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100 /* Standard C includes. */
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101 #include "limits.h"
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103 /* Scheduler includes. */
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104 #include "FreeRTOS.h"
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107 /* Library includes. */
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108 #include "string.h"
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110 /* Hardware specifics. */
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111 #include "iodefine.h"
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113 /*-----------------------------------------------------------*/
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115 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
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116 PSW is set with U and I set, and PM and IPL clear. */
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117 #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
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119 /* The peripheral clock is divided by this value before being supplying the
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121 #if ( configUSE_TICKLESS_IDLE == 0 )
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122 /* If tickless idle is not used then the divisor can be fixed. */
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123 #define portCLOCK_DIVISOR 8UL
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124 #elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
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125 #define portCLOCK_DIVISOR 512UL
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126 #elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
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127 #define portCLOCK_DIVISOR 128UL
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128 #elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
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129 #define portCLOCK_DIVISOR 32UL
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131 #define portCLOCK_DIVISOR 8UL
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134 /* These macros allow a critical section to be added around the call to
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135 xTaskIncrementTick(), which is only ever called from interrupts at the kernel
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136 priority - ie a known priority. Therefore these local macros are a slight
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137 optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
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138 which would require the old IPL to be read first and stored in a local variable. */
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139 #define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
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140 #define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
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142 /* Keys required to lock and unlock access to certain system registers
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144 #define portUNLOCK_KEY 0xA50B
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145 #define portLOCK_KEY 0xA500
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147 /*-----------------------------------------------------------*/
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150 * Function to start the first task executing - written in asm code as direct
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151 * access to registers is required.
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153 static void prvStartFirstTask( void ) __attribute__((naked));
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156 * Software interrupt handler. Performs the actual context switch (saving and
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157 * restoring of registers). Written in asm code as direct register access is
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160 void vPortSoftwareInterruptISR( void ) __attribute__((naked));
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163 * The tick interrupt handler.
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165 void vPortTickISR( void ) __attribute__((interrupt));
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168 * Sets up the periodic ISR used for the RTOS tick using the CMT.
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169 * The application writer can define configSETUP_TICK_INTERRUPT() (in
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170 * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
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171 * in place of prvSetupTimerInterrupt().
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173 static void prvSetupTimerInterrupt( void );
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174 #ifndef configSETUP_TICK_INTERRUPT
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175 /* The user has not provided their own tick interrupt configuration so use
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176 the definition in this file (which uses the interval timer). */
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177 #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
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178 #endif /* configSETUP_TICK_INTERRUPT */
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181 * Called after the sleep mode registers have been configured, prvSleep()
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182 * executes the pre and post sleep macros, and actually calls the wait
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185 #if configUSE_TICKLESS_IDLE == 1
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186 static void prvSleep( TickType_t xExpectedIdleTime );
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187 #endif /* configUSE_TICKLESS_IDLE */
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189 /*-----------------------------------------------------------*/
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191 /* Used in the context save and restore code. */
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192 extern void *pxCurrentTCB;
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194 /* Calculate how many clock increments make up a single tick period. */
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195 static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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197 #if configUSE_TICKLESS_IDLE == 1
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199 /* Holds the maximum number of ticks that can be suppressed - which is
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200 basically how far into the future an interrupt can be generated. Set
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201 during initialisation. This is the maximum possible value that the
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202 compare match register can hold divided by ulMatchValueForOneTick. */
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203 static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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205 /* Flag set from the tick interrupt to allow the sleep processing to know if
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206 sleep mode was exited because of a tick interrupt, or an interrupt
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207 generated by something else. */
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208 static volatile uint32_t ulTickFlag = pdFALSE;
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210 /* The CMT counter is stopped temporarily each time it is re-programmed.
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211 The following constant offsets the CMT counter match value by the number of
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212 CMT counts that would typically be missed while the counter was stopped to
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213 compensate for the lost time. The large difference between the divided CMT
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214 clock and the CPU clock means it is likely ulStoppedTimerCompensation will
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215 equal zero - and be optimised away. */
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216 static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
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220 /*-----------------------------------------------------------*/
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223 * See header file for description.
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225 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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227 /* Offset to end up on 8 byte boundary. */
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230 /* R0 is not included as it is the stack pointer. */
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231 *pxTopOfStack = 0x00;
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233 *pxTopOfStack = 0x00;
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235 *pxTopOfStack = portINITIAL_PSW;
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237 *pxTopOfStack = ( StackType_t ) pxCode;
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239 /* When debugging it can be useful if every register is set to a known
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240 value. Otherwise code space can be saved by just setting the registers
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241 that need to be set. */
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242 #ifdef USE_FULL_REGISTER_INITIALISATION
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245 *pxTopOfStack = 0x12345678; /* r15. */
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247 *pxTopOfStack = 0xaaaabbbb;
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249 *pxTopOfStack = 0xdddddddd;
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251 *pxTopOfStack = 0xcccccccc;
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253 *pxTopOfStack = 0xbbbbbbbb;
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255 *pxTopOfStack = 0xaaaaaaaa;
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257 *pxTopOfStack = 0x99999999;
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259 *pxTopOfStack = 0x88888888;
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261 *pxTopOfStack = 0x77777777;
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263 *pxTopOfStack = 0x66666666;
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265 *pxTopOfStack = 0x55555555;
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267 *pxTopOfStack = 0x44444444;
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269 *pxTopOfStack = 0x33333333;
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271 *pxTopOfStack = 0x22222222;
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276 /* Leave space for the registers that will get popped from the stack
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277 when the task first starts executing. */
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278 pxTopOfStack -= 15;
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282 *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
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284 *pxTopOfStack = 0x12345678; /* Accumulator. */
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286 *pxTopOfStack = 0x87654321; /* Accumulator. */
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288 return pxTopOfStack;
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290 /*-----------------------------------------------------------*/
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292 BaseType_t xPortStartScheduler( void )
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294 /* Use pxCurrentTCB just so it does not get optimised away. */
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295 if( pxCurrentTCB != NULL )
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297 /* Call an application function to set up the timer that will generate
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298 the tick interrupt. This way the application can decide which
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299 peripheral to use. If tickless mode is used then the default
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300 implementation defined in this file (which uses CMT0) should not be
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302 configSETUP_TICK_INTERRUPT();
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304 /* Enable the software interrupt. */
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305 _IEN( _ICU_SWINT ) = 1;
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307 /* Ensure the software interrupt is clear. */
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308 _IR( _ICU_SWINT ) = 0;
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310 /* Ensure the software interrupt is set to the kernel priority. */
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311 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
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313 /* Start the first task. */
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314 prvStartFirstTask();
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317 /* Execution should not reach here as the tasks are now running!
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318 prvSetupTimerInterrupt() is called here to prevent the compiler outputting
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319 a warning about a statically declared function not being referenced in the
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320 case that the application writer has provided their own tick interrupt
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321 configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
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322 their own routine will be called in place of prvSetupTimerInterrupt()). */
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323 prvSetupTimerInterrupt();
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325 /* Should not get here. */
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328 /*-----------------------------------------------------------*/
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330 void vPortEndScheduler( void )
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332 /* Not implemented in ports where there is nothing to return to.
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333 Artificially force an assert. */
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334 configASSERT( pxCurrentTCB == NULL );
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336 /*-----------------------------------------------------------*/
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338 static void prvStartFirstTask( void )
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342 /* When starting the scheduler there is nothing that needs moving to the
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343 interrupt stack because the function is not called from an interrupt.
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344 Just ensure the current stack is the user stack. */
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347 /* Obtain the location of the stack associated with which ever task
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348 pxCurrentTCB is currently pointing to. */
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349 "MOV.L #_pxCurrentTCB, R15 \n" \
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350 "MOV.L [R15], R15 \n" \
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351 "MOV.L [R15], R0 \n" \
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353 /* Restore the registers from the stack of the task pointed to by
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357 /* Accumulator low 32 bits. */
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361 /* Accumulator high 32 bits. */
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364 /* R1 to R15 - R0 is not included as it is the SP. */
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367 /* This pops the remaining registers. */
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373 /*-----------------------------------------------------------*/
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375 void vPortSoftwareInterruptISR( void )
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379 /* Re-enable interrupts. */
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382 /* Move the data that was automatically pushed onto the interrupt stack when
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383 the interrupt occurred from the interrupt stack to the user stack.
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385 R15 is saved before it is clobbered. */
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388 /* Read the user stack pointer. */
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389 "MVFC USP, R15 \n" \
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391 /* Move the address down to the data being moved. */
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392 "SUB #12, R15 \n" \
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393 "MVTC R15, USP \n" \
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395 /* Copy the data across, R15, then PC, then PSW. */
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396 "MOV.L [ R0 ], [ R15 ] \n" \
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397 "MOV.L 4[ R0 ], 4[ R15 ] \n" \
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398 "MOV.L 8[ R0 ], 8[ R15 ] \n" \
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400 /* Move the interrupt stack pointer to its new correct position. */
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403 /* All the rest of the registers are saved directly to the user stack. */
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406 /* Save the rest of the general registers (R15 has been saved already). */
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407 "PUSHM R1-R14 \n" \
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409 /* Save the accumulator. */
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416 /* Shifted left as it is restored to the low order word. */
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417 "SHLL #16, R15 \n" \
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420 /* Save the stack pointer to the TCB. */
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421 "MOV.L #_pxCurrentTCB, R15 \n" \
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422 "MOV.L [ R15 ], R15 \n" \
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423 "MOV.L R0, [ R15 ] \n" \
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425 /* Ensure the interrupt mask is set to the syscall priority while the kernel
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426 structures are being accessed. */
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429 /* Select the next task to run. */
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430 "BSR.A _vTaskSwitchContext \n" \
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432 /* Reset the interrupt mask as no more data structure access is required. */
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435 /* Load the stack pointer of the task that is now selected as the Running
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436 state task from its TCB. */
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437 "MOV.L #_pxCurrentTCB,R15 \n" \
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438 "MOV.L [ R15 ], R15 \n" \
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439 "MOV.L [ R15 ], R0 \n" \
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441 /* Restore the context of the new task. The PSW (Program Status Word) and
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442 PC will be popped by the RTE instruction. */
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451 :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
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454 /*-----------------------------------------------------------*/
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456 void vPortTickISR( void )
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458 /* Re-enabled interrupts. */
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459 __asm volatile( "SETPSW I" );
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461 /* Increment the tick, and perform any processing the new tick value
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462 necessitates. Ensure IPL is at the max syscall value first. */
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463 portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
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465 if( xTaskIncrementTick() != pdFALSE )
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470 portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
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472 #if configUSE_TICKLESS_IDLE == 1
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474 /* The CPU woke because of a tick. */
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475 ulTickFlag = pdTRUE;
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477 /* If this is the first tick since exiting tickless mode then the CMT
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478 compare match value needs resetting. */
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479 CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
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483 /*-----------------------------------------------------------*/
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485 uint32_t ulPortGetIPL( void )
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489 "MVFC PSW, R1 \n" \
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490 "SHLR #24, R1 \n" \
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494 /* This will never get executed, but keeps the compiler from complaining. */
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497 /*-----------------------------------------------------------*/
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499 void vPortSetIPL( uint32_t ulNewIPL )
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504 "MVFC PSW, R5 \n" \
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505 "SHLL #24, R1 \n" \
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506 "AND #-0F000001H, R5 \n" \
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508 "MVTC R5, PSW \n" \
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513 /*-----------------------------------------------------------*/
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515 static void prvSetupTimerInterrupt( void )
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518 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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524 SYSTEM.PRCR.WORD = portLOCK_KEY;
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526 /* Interrupt on compare match. */
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527 CMT0.CMCR.BIT.CMIE = 1;
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529 /* Set the compare match value. */
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530 CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
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532 /* Divide the PCLK. */
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533 #if portCLOCK_DIVISOR == 512
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535 CMT0.CMCR.BIT.CKS = 3;
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537 #elif portCLOCK_DIVISOR == 128
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539 CMT0.CMCR.BIT.CKS = 2;
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541 #elif portCLOCK_DIVISOR == 32
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543 CMT0.CMCR.BIT.CKS = 1;
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545 #elif portCLOCK_DIVISOR == 8
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547 CMT0.CMCR.BIT.CKS = 0;
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551 #error Invalid portCLOCK_DIVISOR setting
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555 /* Enable the interrupt... */
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556 _IEN( _CMT0_CMI0 ) = 1;
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558 /* ...and set its priority to the application defined kernel priority. */
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559 _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
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561 /* Start the timer. */
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562 CMT.CMSTR0.BIT.STR0 = 1;
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564 /*-----------------------------------------------------------*/
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566 #if configUSE_TICKLESS_IDLE == 1
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568 static void prvSleep( TickType_t xExpectedIdleTime )
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570 /* Allow the application to define some pre-sleep processing. */
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571 configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
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573 /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
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574 means the application defined code has already executed the WAIT
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576 if( xExpectedIdleTime > 0 )
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578 __asm volatile( "WAIT" );
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581 /* Allow the application to define some post sleep processing. */
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582 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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585 #endif /* configUSE_TICKLESS_IDLE */
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586 /*-----------------------------------------------------------*/
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588 #if configUSE_TICKLESS_IDLE == 1
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590 void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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592 uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
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593 eSleepModeStatus eSleepAction;
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595 /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
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597 /* Make sure the CMT reload value does not overflow the counter. */
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598 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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600 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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603 /* Calculate the reload value required to wait xExpectedIdleTime tick
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605 ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
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606 if( ulMatchValue > ulStoppedTimerCompensation )
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608 /* Compensate for the fact that the CMT is going to be stopped
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610 ulMatchValue -= ulStoppedTimerCompensation;
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613 /* Stop the CMT momentarily. The time the CMT is stopped for is
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614 accounted for as best it can be, but using the tickless mode will
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615 inevitably result in some tiny drift of the time maintained by the
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616 kernel with respect to calendar time. */
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617 CMT.CMSTR0.BIT.STR0 = 0;
\r
618 while( CMT.CMSTR0.BIT.STR0 == 1 )
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620 /* Nothing to do here. */
\r
623 /* Critical section using the global interrupt bit as the i bit is
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624 automatically reset by the WAIT instruction. */
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625 __asm volatile( "CLRPSW i" );
\r
627 /* The tick flag is set to false before sleeping. If it is true when
\r
628 sleep mode is exited then sleep mode was probably exited because the
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629 tick was suppressed for the entire xExpectedIdleTime period. */
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630 ulTickFlag = pdFALSE;
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632 /* If a context switch is pending then abandon the low power entry as
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633 the context switch might have been pended by an external interrupt that
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634 requires processing. */
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635 eSleepAction = eTaskConfirmSleepModeStatus();
\r
636 if( eSleepAction == eAbortSleep )
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638 /* Restart tick. */
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639 CMT.CMSTR0.BIT.STR0 = 1;
\r
640 __asm volatile( "SETPSW i" );
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642 else if( eSleepAction == eNoTasksWaitingTimeout )
\r
644 /* Protection off. */
\r
645 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
\r
647 /* Ready for software standby with all clocks stopped. */
\r
648 SYSTEM.SBYCR.BIT.SSBY = 1;
\r
650 /* Protection on. */
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651 SYSTEM.PRCR.WORD = portLOCK_KEY;
\r
653 /* Sleep until something happens. Calling prvSleep() will
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654 automatically reset the i bit in the PSW. */
\r
655 prvSleep( xExpectedIdleTime );
\r
657 /* Restart the CMT. */
\r
658 CMT.CMSTR0.BIT.STR0 = 1;
\r
662 /* Protection off. */
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663 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
\r
665 /* Ready for deep sleep mode. */
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666 SYSTEM.MSTPCRC.BIT.DSLPE = 1;
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667 SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
\r
668 SYSTEM.SBYCR.BIT.SSBY = 0;
\r
670 /* Protection on. */
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671 SYSTEM.PRCR.WORD = portLOCK_KEY;
\r
673 /* Adjust the match value to take into account that the current
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674 time slice is already partially complete. */
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675 ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
\r
676 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
\r
678 /* Restart the CMT to count up to the new match value. */
\r
680 CMT.CMSTR0.BIT.STR0 = 1;
\r
682 /* Sleep until something happens. Calling prvSleep() will
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683 automatically reset the i bit in the PSW. */
\r
684 prvSleep( xExpectedIdleTime );
\r
686 /* Stop CMT. Again, the time the SysTick is stopped for is
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687 accounted for as best it can be, but using the tickless mode will
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688 inevitably result in some tiny drift of the time maintained by the
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689 kernel with respect to calendar time. */
\r
690 CMT.CMSTR0.BIT.STR0 = 0;
\r
691 while( CMT.CMSTR0.BIT.STR0 == 1 )
\r
693 /* Nothing to do here. */
\r
696 ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
\r
698 if( ulTickFlag != pdFALSE )
\r
700 /* The tick interrupt has already executed, although because
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701 this function is called with the scheduler suspended the actual
\r
702 tick processing will not occur until after this function has
\r
703 exited. Reset the match value with whatever remains of this
\r
705 ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
\r
706 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
\r
708 /* The tick interrupt handler will already have pended the tick
\r
709 processing in the kernel. As the pending tick will be
\r
710 processed as soon as this function exits, the tick value
\r
711 maintained by the tick is stepped forward by one less than the
\r
712 time spent sleeping. The actual stepping of the tick appears
\r
713 later in this function. */
\r
714 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
718 /* Something other than the tick interrupt ended the sleep.
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719 How many complete tick periods passed while the processor was
\r
721 ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
\r
723 /* The match value is set to whatever fraction of a single tick
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725 ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
\r
726 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
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729 /* Restart the CMT so it runs up to the match value. The match value
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730 will get set to the value required to generate exactly one tick period
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731 the next time the CMT interrupt executes. */
\r
733 CMT.CMSTR0.BIT.STR0 = 1;
\r
735 /* Wind the tick forward by the number of tick periods that the CPU
\r
736 remained in a low power state. */
\r
737 vTaskStepTick( ulCompleteTickPeriods );
\r
741 #endif /* configUSE_TICKLESS_IDLE */
\r