2 FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 /*-----------------------------------------------------------
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71 * Implementation of functions defined in portable.h for the SH2A port.
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72 *----------------------------------------------------------*/
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74 /* Standard C includes. */
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77 /* Scheduler includes. */
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78 #include "FreeRTOS.h"
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81 /* Library includes. */
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84 /* Hardware specifics. */
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85 #include "iodefine.h"
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87 /*-----------------------------------------------------------*/
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89 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
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90 PSW is set with U and I set, and PM and IPL clear. */
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91 #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
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93 /* The peripheral clock is divided by this value before being supplying the
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95 #if ( configUSE_TICKLESS_IDLE == 0 )
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96 /* If tickless idle is not used then the divisor can be fixed. */
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97 #define portCLOCK_DIVISOR 8UL
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98 #elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
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99 #define portCLOCK_DIVISOR 512UL
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100 #elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
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101 #define portCLOCK_DIVISOR 128UL
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102 #elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
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103 #define portCLOCK_DIVISOR 32UL
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105 #define portCLOCK_DIVISOR 8UL
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108 /* These macros allow a critical section to be added around the call to
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109 xTaskIncrementTick(), which is only ever called from interrupts at the kernel
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110 priority - ie a known priority. Therefore these local macros are a slight
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111 optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
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112 which would require the old IPL to be read first and stored in a local variable. */
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113 #define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
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114 #define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
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116 /* Keys required to lock and unlock access to certain system registers
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118 #define portUNLOCK_KEY 0xA50B
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119 #define portLOCK_KEY 0xA500
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121 /*-----------------------------------------------------------*/
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124 * Function to start the first task executing - written in asm code as direct
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125 * access to registers is required.
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127 static void prvStartFirstTask( void ) __attribute__((naked));
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130 * Software interrupt handler. Performs the actual context switch (saving and
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131 * restoring of registers). Written in asm code as direct register access is
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134 void vPortSoftwareInterruptISR( void ) __attribute__((naked));
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137 * The tick interrupt handler.
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139 void vPortTickISR( void ) __attribute__((interrupt));
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142 * Sets up the periodic ISR used for the RTOS tick using the CMT.
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143 * The application writer can define configSETUP_TICK_INTERRUPT() (in
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144 * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
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145 * in place of prvSetupTimerInterrupt().
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147 static void prvSetupTimerInterrupt( void );
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148 #ifndef configSETUP_TICK_INTERRUPT
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149 /* The user has not provided their own tick interrupt configuration so use
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150 the definition in this file (which uses the interval timer). */
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151 #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
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152 #endif /* configSETUP_TICK_INTERRUPT */
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155 * Called after the sleep mode registers have been configured, prvSleep()
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156 * executes the pre and post sleep macros, and actually calls the wait
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159 #if configUSE_TICKLESS_IDLE == 1
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160 static void prvSleep( TickType_t xExpectedIdleTime );
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161 #endif /* configUSE_TICKLESS_IDLE */
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163 /*-----------------------------------------------------------*/
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165 /* Used in the context save and restore code. */
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166 extern void *pxCurrentTCB;
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168 /* Calculate how many clock increments make up a single tick period. */
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169 static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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171 #if configUSE_TICKLESS_IDLE == 1
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173 /* Holds the maximum number of ticks that can be suppressed - which is
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174 basically how far into the future an interrupt can be generated. Set
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175 during initialisation. This is the maximum possible value that the
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176 compare match register can hold divided by ulMatchValueForOneTick. */
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177 static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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179 /* Flag set from the tick interrupt to allow the sleep processing to know if
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180 sleep mode was exited because of a tick interrupt, or an interrupt
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181 generated by something else. */
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182 static volatile uint32_t ulTickFlag = pdFALSE;
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184 /* The CMT counter is stopped temporarily each time it is re-programmed.
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185 The following constant offsets the CMT counter match value by the number of
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186 CMT counts that would typically be missed while the counter was stopped to
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187 compensate for the lost time. The large difference between the divided CMT
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188 clock and the CPU clock means it is likely ulStoppedTimerCompensation will
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189 equal zero - and be optimised away. */
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190 static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
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194 /*-----------------------------------------------------------*/
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197 * See header file for description.
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199 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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201 /* Offset to end up on 8 byte boundary. */
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204 /* R0 is not included as it is the stack pointer. */
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205 *pxTopOfStack = 0x00;
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207 *pxTopOfStack = 0x00;
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209 *pxTopOfStack = portINITIAL_PSW;
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211 *pxTopOfStack = ( StackType_t ) pxCode;
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213 /* When debugging it can be useful if every register is set to a known
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214 value. Otherwise code space can be saved by just setting the registers
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215 that need to be set. */
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216 #ifdef USE_FULL_REGISTER_INITIALISATION
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219 *pxTopOfStack = 0x12345678; /* r15. */
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221 *pxTopOfStack = 0xaaaabbbb;
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223 *pxTopOfStack = 0xdddddddd;
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225 *pxTopOfStack = 0xcccccccc;
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227 *pxTopOfStack = 0xbbbbbbbb;
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229 *pxTopOfStack = 0xaaaaaaaa;
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231 *pxTopOfStack = 0x99999999;
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233 *pxTopOfStack = 0x88888888;
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235 *pxTopOfStack = 0x77777777;
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237 *pxTopOfStack = 0x66666666;
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239 *pxTopOfStack = 0x55555555;
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241 *pxTopOfStack = 0x44444444;
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243 *pxTopOfStack = 0x33333333;
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245 *pxTopOfStack = 0x22222222;
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250 /* Leave space for the registers that will get popped from the stack
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251 when the task first starts executing. */
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252 pxTopOfStack -= 15;
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256 *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
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258 *pxTopOfStack = 0x12345678; /* Accumulator. */
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260 *pxTopOfStack = 0x87654321; /* Accumulator. */
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262 return pxTopOfStack;
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264 /*-----------------------------------------------------------*/
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266 BaseType_t xPortStartScheduler( void )
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268 /* Use pxCurrentTCB just so it does not get optimised away. */
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269 if( pxCurrentTCB != NULL )
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271 /* Call an application function to set up the timer that will generate
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272 the tick interrupt. This way the application can decide which
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273 peripheral to use. If tickless mode is used then the default
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274 implementation defined in this file (which uses CMT0) should not be
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276 configSETUP_TICK_INTERRUPT();
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278 /* Enable the software interrupt. */
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279 _IEN( _ICU_SWINT ) = 1;
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281 /* Ensure the software interrupt is clear. */
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282 _IR( _ICU_SWINT ) = 0;
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284 /* Ensure the software interrupt is set to the kernel priority. */
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285 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
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287 /* Start the first task. */
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288 prvStartFirstTask();
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291 /* Execution should not reach here as the tasks are now running!
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292 prvSetupTimerInterrupt() is called here to prevent the compiler outputting
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293 a warning about a statically declared function not being referenced in the
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294 case that the application writer has provided their own tick interrupt
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295 configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
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296 their own routine will be called in place of prvSetupTimerInterrupt()). */
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297 prvSetupTimerInterrupt();
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299 /* Should not get here. */
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302 /*-----------------------------------------------------------*/
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304 void vPortEndScheduler( void )
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306 /* Not implemented in ports where there is nothing to return to.
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307 Artificially force an assert. */
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308 configASSERT( pxCurrentTCB == NULL );
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310 /*-----------------------------------------------------------*/
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312 static void prvStartFirstTask( void )
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316 /* When starting the scheduler there is nothing that needs moving to the
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317 interrupt stack because the function is not called from an interrupt.
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318 Just ensure the current stack is the user stack. */
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321 /* Obtain the location of the stack associated with which ever task
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322 pxCurrentTCB is currently pointing to. */
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323 "MOV.L #_pxCurrentTCB, R15 \n" \
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324 "MOV.L [R15], R15 \n" \
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325 "MOV.L [R15], R0 \n" \
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327 /* Restore the registers from the stack of the task pointed to by
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331 /* Accumulator low 32 bits. */
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335 /* Accumulator high 32 bits. */
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338 /* R1 to R15 - R0 is not included as it is the SP. */
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341 /* This pops the remaining registers. */
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347 /*-----------------------------------------------------------*/
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349 void vPortSoftwareInterruptISR( void )
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353 /* Re-enable interrupts. */
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356 /* Move the data that was automatically pushed onto the interrupt stack when
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357 the interrupt occurred from the interrupt stack to the user stack.
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359 R15 is saved before it is clobbered. */
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362 /* Read the user stack pointer. */
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363 "MVFC USP, R15 \n" \
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365 /* Move the address down to the data being moved. */
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366 "SUB #12, R15 \n" \
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367 "MVTC R15, USP \n" \
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369 /* Copy the data across, R15, then PC, then PSW. */
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370 "MOV.L [ R0 ], [ R15 ] \n" \
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371 "MOV.L 4[ R0 ], 4[ R15 ] \n" \
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372 "MOV.L 8[ R0 ], 8[ R15 ] \n" \
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374 /* Move the interrupt stack pointer to its new correct position. */
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377 /* All the rest of the registers are saved directly to the user stack. */
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380 /* Save the rest of the general registers (R15 has been saved already). */
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381 "PUSHM R1-R14 \n" \
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383 /* Save the accumulator. */
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390 /* Shifted left as it is restored to the low order word. */
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391 "SHLL #16, R15 \n" \
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394 /* Save the stack pointer to the TCB. */
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395 "MOV.L #_pxCurrentTCB, R15 \n" \
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396 "MOV.L [ R15 ], R15 \n" \
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397 "MOV.L R0, [ R15 ] \n" \
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399 /* Ensure the interrupt mask is set to the syscall priority while the kernel
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400 structures are being accessed. */
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403 /* Select the next task to run. */
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404 "BSR.A _vTaskSwitchContext \n" \
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406 /* Reset the interrupt mask as no more data structure access is required. */
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409 /* Load the stack pointer of the task that is now selected as the Running
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410 state task from its TCB. */
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411 "MOV.L #_pxCurrentTCB,R15 \n" \
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412 "MOV.L [ R15 ], R15 \n" \
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413 "MOV.L [ R15 ], R0 \n" \
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415 /* Restore the context of the new task. The PSW (Program Status Word) and
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416 PC will be popped by the RTE instruction. */
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425 :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
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428 /*-----------------------------------------------------------*/
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430 void vPortTickISR( void )
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432 /* Re-enabled interrupts. */
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433 __asm volatile( "SETPSW I" );
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435 /* Increment the tick, and perform any processing the new tick value
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436 necessitates. Ensure IPL is at the max syscall value first. */
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437 portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
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439 if( xTaskIncrementTick() != pdFALSE )
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444 portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
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446 #if configUSE_TICKLESS_IDLE == 1
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448 /* The CPU woke because of a tick. */
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449 ulTickFlag = pdTRUE;
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451 /* If this is the first tick since exiting tickless mode then the CMT
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452 compare match value needs resetting. */
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453 CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
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457 /*-----------------------------------------------------------*/
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459 uint32_t ulPortGetIPL( void )
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463 "MVFC PSW, R1 \n" \
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464 "SHLR #24, R1 \n" \
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468 /* This will never get executed, but keeps the compiler from complaining. */
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471 /*-----------------------------------------------------------*/
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473 void vPortSetIPL( uint32_t ulNewIPL )
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478 "MVFC PSW, R5 \n" \
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479 "SHLL #24, R1 \n" \
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480 "AND #-0F000001H, R5 \n" \
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482 "MVTC R5, PSW \n" \
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487 /*-----------------------------------------------------------*/
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489 static void prvSetupTimerInterrupt( void )
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492 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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498 SYSTEM.PRCR.WORD = portLOCK_KEY;
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500 /* Interrupt on compare match. */
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501 CMT0.CMCR.BIT.CMIE = 1;
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503 /* Set the compare match value. */
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504 CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
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506 /* Divide the PCLK. */
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507 #if portCLOCK_DIVISOR == 512
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509 CMT0.CMCR.BIT.CKS = 3;
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511 #elif portCLOCK_DIVISOR == 128
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513 CMT0.CMCR.BIT.CKS = 2;
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515 #elif portCLOCK_DIVISOR == 32
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517 CMT0.CMCR.BIT.CKS = 1;
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519 #elif portCLOCK_DIVISOR == 8
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521 CMT0.CMCR.BIT.CKS = 0;
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525 #error Invalid portCLOCK_DIVISOR setting
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529 /* Enable the interrupt... */
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530 _IEN( _CMT0_CMI0 ) = 1;
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532 /* ...and set its priority to the application defined kernel priority. */
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533 _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
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535 /* Start the timer. */
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536 CMT.CMSTR0.BIT.STR0 = 1;
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538 /*-----------------------------------------------------------*/
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540 #if configUSE_TICKLESS_IDLE == 1
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542 static void prvSleep( TickType_t xExpectedIdleTime )
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544 /* Allow the application to define some pre-sleep processing. */
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545 configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
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547 /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
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548 means the application defined code has already executed the WAIT
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550 if( xExpectedIdleTime > 0 )
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552 __asm volatile( "WAIT" );
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555 /* Allow the application to define some post sleep processing. */
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556 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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559 #endif /* configUSE_TICKLESS_IDLE */
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560 /*-----------------------------------------------------------*/
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562 #if configUSE_TICKLESS_IDLE == 1
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564 void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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566 uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
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567 eSleepModeStatus eSleepAction;
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569 /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
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571 /* Make sure the CMT reload value does not overflow the counter. */
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572 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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574 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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577 /* Calculate the reload value required to wait xExpectedIdleTime tick
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579 ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
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580 if( ulMatchValue > ulStoppedTimerCompensation )
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582 /* Compensate for the fact that the CMT is going to be stopped
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584 ulMatchValue -= ulStoppedTimerCompensation;
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587 /* Stop the CMT momentarily. The time the CMT is stopped for is
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588 accounted for as best it can be, but using the tickless mode will
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589 inevitably result in some tiny drift of the time maintained by the
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590 kernel with respect to calendar time. */
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591 CMT.CMSTR0.BIT.STR0 = 0;
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592 while( CMT.CMSTR0.BIT.STR0 == 1 )
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594 /* Nothing to do here. */
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597 /* Critical section using the global interrupt bit as the i bit is
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598 automatically reset by the WAIT instruction. */
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599 __asm volatile( "CLRPSW i" );
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601 /* The tick flag is set to false before sleeping. If it is true when
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602 sleep mode is exited then sleep mode was probably exited because the
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603 tick was suppressed for the entire xExpectedIdleTime period. */
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604 ulTickFlag = pdFALSE;
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606 /* If a context switch is pending then abandon the low power entry as
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607 the context switch might have been pended by an external interrupt that
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608 requires processing. */
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609 eSleepAction = eTaskConfirmSleepModeStatus();
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610 if( eSleepAction == eAbortSleep )
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612 /* Restart tick. */
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613 CMT.CMSTR0.BIT.STR0 = 1;
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614 __asm volatile( "SETPSW i" );
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616 else if( eSleepAction == eNoTasksWaitingTimeout )
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618 /* Protection off. */
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619 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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621 /* Ready for software standby with all clocks stopped. */
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622 SYSTEM.SBYCR.BIT.SSBY = 1;
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624 /* Protection on. */
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625 SYSTEM.PRCR.WORD = portLOCK_KEY;
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627 /* Sleep until something happens. Calling prvSleep() will
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628 automatically reset the i bit in the PSW. */
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629 prvSleep( xExpectedIdleTime );
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631 /* Restart the CMT. */
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632 CMT.CMSTR0.BIT.STR0 = 1;
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636 /* Protection off. */
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637 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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639 /* Ready for deep sleep mode. */
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640 SYSTEM.MSTPCRC.BIT.DSLPE = 1;
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641 SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
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642 SYSTEM.SBYCR.BIT.SSBY = 0;
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644 /* Protection on. */
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645 SYSTEM.PRCR.WORD = portLOCK_KEY;
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647 /* Adjust the match value to take into account that the current
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648 time slice is already partially complete. */
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649 ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
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650 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
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652 /* Restart the CMT to count up to the new match value. */
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654 CMT.CMSTR0.BIT.STR0 = 1;
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656 /* Sleep until something happens. Calling prvSleep() will
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657 automatically reset the i bit in the PSW. */
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658 prvSleep( xExpectedIdleTime );
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660 /* Stop CMT. Again, the time the SysTick is stopped for is
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661 accounted for as best it can be, but using the tickless mode will
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662 inevitably result in some tiny drift of the time maintained by the
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663 kernel with respect to calendar time. */
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664 CMT.CMSTR0.BIT.STR0 = 0;
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665 while( CMT.CMSTR0.BIT.STR0 == 1 )
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667 /* Nothing to do here. */
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670 ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
\r
672 if( ulTickFlag != pdFALSE )
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674 /* The tick interrupt has already executed, although because
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675 this function is called with the scheduler suspended the actual
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676 tick processing will not occur until after this function has
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677 exited. Reset the match value with whatever remains of this
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679 ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
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680 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
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682 /* The tick interrupt handler will already have pended the tick
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683 processing in the kernel. As the pending tick will be
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684 processed as soon as this function exits, the tick value
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685 maintained by the tick is stepped forward by one less than the
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686 time spent sleeping. The actual stepping of the tick appears
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687 later in this function. */
\r
688 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
692 /* Something other than the tick interrupt ended the sleep.
\r
693 How many complete tick periods passed while the processor was
\r
695 ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
\r
697 /* The match value is set to whatever fraction of a single tick
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699 ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
\r
700 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
\r
703 /* Restart the CMT so it runs up to the match value. The match value
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704 will get set to the value required to generate exactly one tick period
\r
705 the next time the CMT interrupt executes. */
\r
707 CMT.CMSTR0.BIT.STR0 = 1;
\r
709 /* Wind the tick forward by the number of tick periods that the CPU
\r
710 remained in a low power state. */
\r
711 vTaskStepTick( ulCompleteTickPeriods );
\r
715 #endif /* configUSE_TICKLESS_IDLE */
\r