2 * FreeRTOS Kernel V10.3.0
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3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /*-----------------------------------------------------------
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29 * Implementation of functions defined in portable.h for the SH2A port.
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30 *----------------------------------------------------------*/
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32 /* Standard C includes. */
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35 /* Scheduler includes. */
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36 #include "FreeRTOS.h"
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39 /* Library includes. */
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42 /* Hardware specifics. */
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43 #include "iodefine.h"
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45 /*-----------------------------------------------------------*/
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47 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
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48 PSW is set with U and I set, and PM and IPL clear. */
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49 #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
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51 /* The peripheral clock is divided by this value before being supplying the
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53 #if ( configUSE_TICKLESS_IDLE == 0 )
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54 /* If tickless idle is not used then the divisor can be fixed. */
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55 #define portCLOCK_DIVISOR 8UL
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56 #elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
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57 #define portCLOCK_DIVISOR 512UL
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58 #elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
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59 #define portCLOCK_DIVISOR 128UL
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60 #elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
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61 #define portCLOCK_DIVISOR 32UL
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63 #define portCLOCK_DIVISOR 8UL
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66 /* These macros allow a critical section to be added around the call to
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67 xTaskIncrementTick(), which is only ever called from interrupts at the kernel
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68 priority - ie a known priority. Therefore these local macros are a slight
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69 optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
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70 which would require the old IPL to be read first and stored in a local variable. */
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71 #define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
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72 #define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
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74 /* Keys required to lock and unlock access to certain system registers
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76 #define portUNLOCK_KEY 0xA50B
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77 #define portLOCK_KEY 0xA500
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79 /*-----------------------------------------------------------*/
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82 * Function to start the first task executing - written in asm code as direct
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83 * access to registers is required.
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85 static void prvStartFirstTask( void ) __attribute__((naked));
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88 * Software interrupt handler. Performs the actual context switch (saving and
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89 * restoring of registers). Written in asm code as direct register access is
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92 void vPortSoftwareInterruptISR( void ) __attribute__((naked));
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95 * The tick interrupt handler.
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97 void vPortTickISR( void ) __attribute__((interrupt));
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100 * Sets up the periodic ISR used for the RTOS tick using the CMT.
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101 * The application writer can define configSETUP_TICK_INTERRUPT() (in
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102 * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
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103 * in place of prvSetupTimerInterrupt().
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105 static void prvSetupTimerInterrupt( void );
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106 #ifndef configSETUP_TICK_INTERRUPT
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107 /* The user has not provided their own tick interrupt configuration so use
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108 the definition in this file (which uses the interval timer). */
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109 #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
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110 #endif /* configSETUP_TICK_INTERRUPT */
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113 * Called after the sleep mode registers have been configured, prvSleep()
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114 * executes the pre and post sleep macros, and actually calls the wait
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117 #if configUSE_TICKLESS_IDLE == 1
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118 static void prvSleep( TickType_t xExpectedIdleTime );
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119 #endif /* configUSE_TICKLESS_IDLE */
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121 /*-----------------------------------------------------------*/
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123 /* Used in the context save and restore code. */
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124 extern void *pxCurrentTCB;
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126 /* Calculate how many clock increments make up a single tick period. */
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127 static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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129 #if configUSE_TICKLESS_IDLE == 1
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131 /* Holds the maximum number of ticks that can be suppressed - which is
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132 basically how far into the future an interrupt can be generated. Set
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133 during initialisation. This is the maximum possible value that the
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134 compare match register can hold divided by ulMatchValueForOneTick. */
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135 static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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137 /* Flag set from the tick interrupt to allow the sleep processing to know if
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138 sleep mode was exited because of a tick interrupt, or an interrupt
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139 generated by something else. */
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140 static volatile uint32_t ulTickFlag = pdFALSE;
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142 /* The CMT counter is stopped temporarily each time it is re-programmed.
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143 The following constant offsets the CMT counter match value by the number of
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144 CMT counts that would typically be missed while the counter was stopped to
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145 compensate for the lost time. The large difference between the divided CMT
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146 clock and the CPU clock means it is likely ulStoppedTimerCompensation will
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147 equal zero - and be optimised away. */
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148 static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
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152 /*-----------------------------------------------------------*/
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155 * See header file for description.
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157 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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159 /* Offset to end up on 8 byte boundary. */
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162 /* R0 is not included as it is the stack pointer. */
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163 *pxTopOfStack = 0x00;
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165 *pxTopOfStack = 0x00;
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167 *pxTopOfStack = portINITIAL_PSW;
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169 *pxTopOfStack = ( StackType_t ) pxCode;
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171 /* When debugging it can be useful if every register is set to a known
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172 value. Otherwise code space can be saved by just setting the registers
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173 that need to be set. */
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174 #ifdef USE_FULL_REGISTER_INITIALISATION
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177 *pxTopOfStack = 0x12345678; /* r15. */
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179 *pxTopOfStack = 0xaaaabbbb;
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181 *pxTopOfStack = 0xdddddddd;
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183 *pxTopOfStack = 0xcccccccc;
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185 *pxTopOfStack = 0xbbbbbbbb;
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187 *pxTopOfStack = 0xaaaaaaaa;
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189 *pxTopOfStack = 0x99999999;
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191 *pxTopOfStack = 0x88888888;
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193 *pxTopOfStack = 0x77777777;
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195 *pxTopOfStack = 0x66666666;
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197 *pxTopOfStack = 0x55555555;
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199 *pxTopOfStack = 0x44444444;
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201 *pxTopOfStack = 0x33333333;
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203 *pxTopOfStack = 0x22222222;
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208 /* Leave space for the registers that will get popped from the stack
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209 when the task first starts executing. */
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210 pxTopOfStack -= 15;
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214 *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
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216 *pxTopOfStack = 0x12345678; /* Accumulator. */
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218 *pxTopOfStack = 0x87654321; /* Accumulator. */
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220 return pxTopOfStack;
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222 /*-----------------------------------------------------------*/
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224 BaseType_t xPortStartScheduler( void )
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226 /* Use pxCurrentTCB just so it does not get optimised away. */
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227 if( pxCurrentTCB != NULL )
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229 /* Call an application function to set up the timer that will generate
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230 the tick interrupt. This way the application can decide which
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231 peripheral to use. If tickless mode is used then the default
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232 implementation defined in this file (which uses CMT0) should not be
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234 configSETUP_TICK_INTERRUPT();
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236 /* Enable the software interrupt. */
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237 _IEN( _ICU_SWINT ) = 1;
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239 /* Ensure the software interrupt is clear. */
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240 _IR( _ICU_SWINT ) = 0;
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242 /* Ensure the software interrupt is set to the kernel priority. */
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243 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
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245 /* Start the first task. */
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246 prvStartFirstTask();
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249 /* Execution should not reach here as the tasks are now running!
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250 prvSetupTimerInterrupt() is called here to prevent the compiler outputting
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251 a warning about a statically declared function not being referenced in the
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252 case that the application writer has provided their own tick interrupt
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253 configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
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254 their own routine will be called in place of prvSetupTimerInterrupt()). */
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255 prvSetupTimerInterrupt();
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257 /* Should not get here. */
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260 /*-----------------------------------------------------------*/
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262 void vPortEndScheduler( void )
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264 /* Not implemented in ports where there is nothing to return to.
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265 Artificially force an assert. */
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266 configASSERT( pxCurrentTCB == NULL );
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268 /*-----------------------------------------------------------*/
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270 static void prvStartFirstTask( void )
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274 /* When starting the scheduler there is nothing that needs moving to the
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275 interrupt stack because the function is not called from an interrupt.
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276 Just ensure the current stack is the user stack. */
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279 /* Obtain the location of the stack associated with which ever task
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280 pxCurrentTCB is currently pointing to. */
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281 "MOV.L #_pxCurrentTCB, R15 \n" \
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282 "MOV.L [R15], R15 \n" \
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283 "MOV.L [R15], R0 \n" \
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285 /* Restore the registers from the stack of the task pointed to by
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289 /* Accumulator low 32 bits. */
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293 /* Accumulator high 32 bits. */
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296 /* R1 to R15 - R0 is not included as it is the SP. */
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299 /* This pops the remaining registers. */
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305 /*-----------------------------------------------------------*/
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307 void vPortSoftwareInterruptISR( void )
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311 /* Re-enable interrupts. */
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314 /* Move the data that was automatically pushed onto the interrupt stack when
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315 the interrupt occurred from the interrupt stack to the user stack.
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317 R15 is saved before it is clobbered. */
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320 /* Read the user stack pointer. */
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321 "MVFC USP, R15 \n" \
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323 /* Move the address down to the data being moved. */
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324 "SUB #12, R15 \n" \
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325 "MVTC R15, USP \n" \
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327 /* Copy the data across, R15, then PC, then PSW. */
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328 "MOV.L [ R0 ], [ R15 ] \n" \
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329 "MOV.L 4[ R0 ], 4[ R15 ] \n" \
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330 "MOV.L 8[ R0 ], 8[ R15 ] \n" \
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332 /* Move the interrupt stack pointer to its new correct position. */
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335 /* All the rest of the registers are saved directly to the user stack. */
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338 /* Save the rest of the general registers (R15 has been saved already). */
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339 "PUSHM R1-R14 \n" \
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341 /* Save the accumulator. */
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348 /* Shifted left as it is restored to the low order word. */
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349 "SHLL #16, R15 \n" \
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352 /* Save the stack pointer to the TCB. */
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353 "MOV.L #_pxCurrentTCB, R15 \n" \
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354 "MOV.L [ R15 ], R15 \n" \
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355 "MOV.L R0, [ R15 ] \n" \
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357 /* Ensure the interrupt mask is set to the syscall priority while the kernel
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358 structures are being accessed. */
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361 /* Select the next task to run. */
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362 "BSR.A _vTaskSwitchContext \n" \
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364 /* Reset the interrupt mask as no more data structure access is required. */
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367 /* Load the stack pointer of the task that is now selected as the Running
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368 state task from its TCB. */
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369 "MOV.L #_pxCurrentTCB,R15 \n" \
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370 "MOV.L [ R15 ], R15 \n" \
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371 "MOV.L [ R15 ], R0 \n" \
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373 /* Restore the context of the new task. The PSW (Program Status Word) and
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374 PC will be popped by the RTE instruction. */
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383 :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
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386 /*-----------------------------------------------------------*/
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388 void vPortTickISR( void )
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390 /* Re-enabled interrupts. */
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391 __asm volatile( "SETPSW I" );
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393 /* Increment the tick, and perform any processing the new tick value
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394 necessitates. Ensure IPL is at the max syscall value first. */
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395 portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
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397 if( xTaskIncrementTick() != pdFALSE )
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402 portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
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404 #if configUSE_TICKLESS_IDLE == 1
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406 /* The CPU woke because of a tick. */
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407 ulTickFlag = pdTRUE;
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409 /* If this is the first tick since exiting tickless mode then the CMT
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410 compare match value needs resetting. */
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411 CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
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415 /*-----------------------------------------------------------*/
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417 uint32_t ulPortGetIPL( void )
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421 "MVFC PSW, R1 \n" \
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422 "SHLR #24, R1 \n" \
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426 /* This will never get executed, but keeps the compiler from complaining. */
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429 /*-----------------------------------------------------------*/
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431 void vPortSetIPL( uint32_t ulNewIPL )
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436 "MVFC PSW, R5 \n" \
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437 "SHLL #24, R1 \n" \
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438 "AND #-0F000001H, R5 \n" \
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440 "MVTC R5, PSW \n" \
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445 /*-----------------------------------------------------------*/
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447 static void prvSetupTimerInterrupt( void )
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450 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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456 SYSTEM.PRCR.WORD = portLOCK_KEY;
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458 /* Interrupt on compare match. */
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459 CMT0.CMCR.BIT.CMIE = 1;
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461 /* Set the compare match value. */
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462 CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
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464 /* Divide the PCLK. */
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465 #if portCLOCK_DIVISOR == 512
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467 CMT0.CMCR.BIT.CKS = 3;
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469 #elif portCLOCK_DIVISOR == 128
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471 CMT0.CMCR.BIT.CKS = 2;
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473 #elif portCLOCK_DIVISOR == 32
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475 CMT0.CMCR.BIT.CKS = 1;
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477 #elif portCLOCK_DIVISOR == 8
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479 CMT0.CMCR.BIT.CKS = 0;
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483 #error Invalid portCLOCK_DIVISOR setting
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487 /* Enable the interrupt... */
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488 _IEN( _CMT0_CMI0 ) = 1;
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490 /* ...and set its priority to the application defined kernel priority. */
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491 _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
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493 /* Start the timer. */
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494 CMT.CMSTR0.BIT.STR0 = 1;
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496 /*-----------------------------------------------------------*/
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498 #if configUSE_TICKLESS_IDLE == 1
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500 static void prvSleep( TickType_t xExpectedIdleTime )
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502 /* Allow the application to define some pre-sleep processing. */
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503 configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
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505 /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
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506 means the application defined code has already executed the WAIT
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508 if( xExpectedIdleTime > 0 )
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510 __asm volatile( "WAIT" );
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513 /* Allow the application to define some post sleep processing. */
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514 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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517 #endif /* configUSE_TICKLESS_IDLE */
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518 /*-----------------------------------------------------------*/
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520 #if configUSE_TICKLESS_IDLE == 1
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522 void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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524 uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
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525 eSleepModeStatus eSleepAction;
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527 /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
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529 /* Make sure the CMT reload value does not overflow the counter. */
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530 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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532 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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535 /* Calculate the reload value required to wait xExpectedIdleTime tick
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537 ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
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538 if( ulMatchValue > ulStoppedTimerCompensation )
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540 /* Compensate for the fact that the CMT is going to be stopped
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542 ulMatchValue -= ulStoppedTimerCompensation;
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545 /* Stop the CMT momentarily. The time the CMT is stopped for is
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546 accounted for as best it can be, but using the tickless mode will
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547 inevitably result in some tiny drift of the time maintained by the
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548 kernel with respect to calendar time. */
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549 CMT.CMSTR0.BIT.STR0 = 0;
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550 while( CMT.CMSTR0.BIT.STR0 == 1 )
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552 /* Nothing to do here. */
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555 /* Critical section using the global interrupt bit as the i bit is
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556 automatically reset by the WAIT instruction. */
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557 __asm volatile( "CLRPSW i" );
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559 /* The tick flag is set to false before sleeping. If it is true when
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560 sleep mode is exited then sleep mode was probably exited because the
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561 tick was suppressed for the entire xExpectedIdleTime period. */
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562 ulTickFlag = pdFALSE;
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564 /* If a context switch is pending then abandon the low power entry as
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565 the context switch might have been pended by an external interrupt that
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566 requires processing. */
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567 eSleepAction = eTaskConfirmSleepModeStatus();
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568 if( eSleepAction == eAbortSleep )
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570 /* Restart tick. */
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571 CMT.CMSTR0.BIT.STR0 = 1;
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572 __asm volatile( "SETPSW i" );
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574 else if( eSleepAction == eNoTasksWaitingTimeout )
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576 /* Protection off. */
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577 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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579 /* Ready for software standby with all clocks stopped. */
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580 SYSTEM.SBYCR.BIT.SSBY = 1;
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582 /* Protection on. */
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583 SYSTEM.PRCR.WORD = portLOCK_KEY;
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585 /* Sleep until something happens. Calling prvSleep() will
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586 automatically reset the i bit in the PSW. */
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587 prvSleep( xExpectedIdleTime );
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589 /* Restart the CMT. */
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590 CMT.CMSTR0.BIT.STR0 = 1;
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594 /* Protection off. */
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595 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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597 /* Ready for deep sleep mode. */
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598 SYSTEM.MSTPCRC.BIT.DSLPE = 1;
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599 SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
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600 SYSTEM.SBYCR.BIT.SSBY = 0;
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602 /* Protection on. */
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603 SYSTEM.PRCR.WORD = portLOCK_KEY;
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605 /* Adjust the match value to take into account that the current
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606 time slice is already partially complete. */
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607 ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
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608 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
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610 /* Restart the CMT to count up to the new match value. */
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612 CMT.CMSTR0.BIT.STR0 = 1;
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614 /* Sleep until something happens. Calling prvSleep() will
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615 automatically reset the i bit in the PSW. */
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616 prvSleep( xExpectedIdleTime );
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618 /* Stop CMT. Again, the time the SysTick is stopped for is
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619 accounted for as best it can be, but using the tickless mode will
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620 inevitably result in some tiny drift of the time maintained by the
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621 kernel with respect to calendar time. */
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622 CMT.CMSTR0.BIT.STR0 = 0;
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623 while( CMT.CMSTR0.BIT.STR0 == 1 )
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625 /* Nothing to do here. */
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628 ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
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630 if( ulTickFlag != pdFALSE )
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632 /* The tick interrupt has already executed, although because
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633 this function is called with the scheduler suspended the actual
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634 tick processing will not occur until after this function has
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635 exited. Reset the match value with whatever remains of this
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637 ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
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638 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
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640 /* The tick interrupt handler will already have pended the tick
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641 processing in the kernel. As the pending tick will be
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642 processed as soon as this function exits, the tick value
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643 maintained by the tick is stepped forward by one less than the
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644 time spent sleeping. The actual stepping of the tick appears
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645 later in this function. */
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646 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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650 /* Something other than the tick interrupt ended the sleep.
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651 How many complete tick periods passed while the processor was
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653 ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
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655 /* The match value is set to whatever fraction of a single tick
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657 ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
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658 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
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661 /* Restart the CMT so it runs up to the match value. The match value
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662 will get set to the value required to generate exactly one tick period
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663 the next time the CMT interrupt executes. */
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665 CMT.CMSTR0.BIT.STR0 = 1;
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667 /* Wind the tick forward by the number of tick periods that the CPU
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668 remained in a low power state. */
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669 vTaskStepTick( ulCompleteTickPeriods );
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673 #endif /* configUSE_TICKLESS_IDLE */
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