2 FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 distribute a combined work that includes FreeRTOS without being obliged to
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35 provide the source code for proprietary components outside of the FreeRTOS
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38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 details. You should have received a copy of the GNU General Public License
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42 and the FreeRTOS license exception along with FreeRTOS; if not it can be
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43 viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 writing to Real Time Engineers Ltd., contact details for whom are available
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45 on the FreeRTOS WEB site.
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49 ***************************************************************************
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51 * Having a problem? Start by reading the FAQ "My application does *
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52 * not run, what could be wrong?" *
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54 * http://www.FreeRTOS.org/FAQHelp.html *
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56 ***************************************************************************
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59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 license and Real Time Engineers Ltd. contact details.
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62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 fully thread aware and reentrant UDP/IP stack.
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66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 Integrity Systems, who sell the code with commercial support,
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68 indemnification and middleware, under the OpenRTOS brand.
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70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 engineered and independently SIL3 certified version for use in safety and
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72 mission critical applications that require provable dependability.
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75 /*-----------------------------------------------------------
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76 * Implementation of functions defined in portable.h for the SH2A port.
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77 *----------------------------------------------------------*/
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79 /* Standard C includes. */
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82 /* Scheduler includes. */
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83 #include "FreeRTOS.h"
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86 /* Library includes. */
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89 /* Hardware specifics. */
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90 #include "iodefine.h"
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92 /*-----------------------------------------------------------*/
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94 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
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95 PSW is set with U and I set, and PM and IPL clear. */
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96 #define portINITIAL_PSW ( ( portSTACK_TYPE ) 0x00030000 )
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98 /* The peripheral clock is divided by this value before being supplying the
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100 #if ( configUSE_TICKLESS_IDLE == 0 )
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101 /* If tickless idle is not used then the divisor can be fixed. */
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102 #define portCLOCK_DIVISOR 8UL
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103 #elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
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104 #define portCLOCK_DIVISOR 512UL
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105 #elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
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106 #define portCLOCK_DIVISOR 128UL
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107 #elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
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108 #define portCLOCK_DIVISOR 32UL
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110 #define portCLOCK_DIVISOR 8UL
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113 /* These macros allow a critical section to be added around the call to
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114 vTaskIncrementTick(), which is only ever called from interrupts at the kernel
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115 priority - ie a known priority. Therefore these local macros are a slight
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116 optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
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117 which would require the old IPL to be read first and stored in a local variable. */
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118 #define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
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119 #define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
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121 /* Keys required to lock and unlock access to certain system registers
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123 #define portUNLOCK_KEY 0xA50B
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124 #define portLOCK_KEY 0xA500
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126 /*-----------------------------------------------------------*/
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129 * Function to start the first task executing - written in asm code as direct
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130 * access to registers is required.
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132 static void prvStartFirstTask( void ) __attribute__((naked));
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135 * Software interrupt handler. Performs the actual context switch (saving and
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136 * restoring of registers). Written in asm code as direct register access is
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139 void vPortSoftwareInterruptISR( void ) __attribute__((naked));
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142 * The tick interrupt handler.
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144 void vPortTickISR( void ) __attribute__((interrupt));
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147 * Sets up the periodic ISR used for the RTOS tick using the CMT.
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148 * The application writer can define configSETUP_TICK_INTERRUPT() (in
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149 * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
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150 * in place of prvSetupTimerInterrupt().
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152 static void prvSetupTimerInterrupt( void );
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153 #ifndef configSETUP_TICK_INTERRUPT
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154 /* The user has not provided their own tick interrupt configuration so use
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155 the definition in this file (which uses the interval timer). */
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156 #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
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157 #endif /* configSETUP_TICK_INTERRUPT */
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160 * Called after the sleep mode registers have been configured, prvSleep()
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161 * executes the pre and post sleep macros, and actually calls the wait
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164 #if configUSE_TICKLESS_IDLE == 1
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165 static void prvSleep( portTickType xExpectedIdleTime );
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166 #endif /* configUSE_TICKLESS_IDLE */
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168 /*-----------------------------------------------------------*/
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170 /* Used in the context save and restore code. */
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171 extern void *pxCurrentTCB;
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173 /* Calculate how many clock increments make up a single tick period. */
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174 static const unsigned long ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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176 #if configUSE_TICKLESS_IDLE == 1
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178 /* Holds the maximum number of ticks that can be suppressed - which is
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179 basically how far into the future an interrupt can be generated. Set
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180 during initialisation. This is the maximum possible value that the
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181 compare match register can hold divided by ulMatchValueForOneTick. */
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182 static const portTickType xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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184 /* Flag set from the tick interrupt to allow the sleep processing to know if
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185 sleep mode was exited because of a tick interrupt, or an interrupt
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186 generated by something else. */
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187 static volatile uint32_t ulTickFlag = pdFALSE;
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189 /* The CMT counter is stopped temporarily each time it is re-programmed.
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190 The following constant offsets the CMT counter match value by the number of
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191 CMT counts that would typically be missed while the counter was stopped to
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192 compensate for the lost time. The large difference between the divided CMT
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193 clock and the CPU clock means it is likely ulStoppedTimerCompensation will
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194 equal zero - and be optimised away. */
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195 static const unsigned long ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
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199 /*-----------------------------------------------------------*/
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202 * See header file for description.
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204 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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206 /* Offset to end up on 8 byte boundary. */
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209 /* R0 is not included as it is the stack pointer. */
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210 *pxTopOfStack = 0x00;
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212 *pxTopOfStack = 0x00;
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214 *pxTopOfStack = portINITIAL_PSW;
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216 *pxTopOfStack = ( portSTACK_TYPE ) pxCode;
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218 /* When debugging it can be useful if every register is set to a known
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219 value. Otherwise code space can be saved by just setting the registers
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220 that need to be set. */
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221 #ifdef USE_FULL_REGISTER_INITIALISATION
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224 *pxTopOfStack = 0x12345678; /* r15. */
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226 *pxTopOfStack = 0xaaaabbbb;
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228 *pxTopOfStack = 0xdddddddd;
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230 *pxTopOfStack = 0xcccccccc;
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232 *pxTopOfStack = 0xbbbbbbbb;
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234 *pxTopOfStack = 0xaaaaaaaa;
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236 *pxTopOfStack = 0x99999999;
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238 *pxTopOfStack = 0x88888888;
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240 *pxTopOfStack = 0x77777777;
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242 *pxTopOfStack = 0x66666666;
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244 *pxTopOfStack = 0x55555555;
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246 *pxTopOfStack = 0x44444444;
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248 *pxTopOfStack = 0x33333333;
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250 *pxTopOfStack = 0x22222222;
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255 /* Leave space for the registers that will get popped from the stack
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256 when the task first starts executing. */
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257 pxTopOfStack -= 15;
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261 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R1 */
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263 *pxTopOfStack = 0x12345678; /* Accumulator. */
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265 *pxTopOfStack = 0x87654321; /* Accumulator. */
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267 return pxTopOfStack;
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269 /*-----------------------------------------------------------*/
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271 portBASE_TYPE xPortStartScheduler( void )
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273 /* Use pxCurrentTCB just so it does not get optimised away. */
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274 if( pxCurrentTCB != NULL )
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276 /* Call an application function to set up the timer that will generate
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277 the tick interrupt. This way the application can decide which
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278 peripheral to use. If tickless mode is used then the default
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279 implementation defined in this file (which uses CMT0) should not be
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281 configSETUP_TICK_INTERRUPT();
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283 /* Enable the software interrupt. */
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284 _IEN( _ICU_SWINT ) = 1;
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286 /* Ensure the software interrupt is clear. */
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287 _IR( _ICU_SWINT ) = 0;
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289 /* Ensure the software interrupt is set to the kernel priority. */
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290 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
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292 /* Start the first task. */
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293 prvStartFirstTask();
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296 /* Execution should not reach here as the tasks are now running!
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297 prvSetupTimerInterrupt() is called here to prevent the compiler outputting
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298 a warning about a statically declared function not being referenced in the
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299 case that the application writer has provided their own tick interrupt
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300 configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
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301 their own routine will be called in place of prvSetupTimerInterrupt()). */
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302 prvSetupTimerInterrupt();
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304 /* Should not get here. */
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307 /*-----------------------------------------------------------*/
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309 void vPortEndScheduler( void )
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311 /* Not implemented as there is nothing to return to. */
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313 /*-----------------------------------------------------------*/
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315 static void prvStartFirstTask( void )
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319 /* When starting the scheduler there is nothing that needs moving to the
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320 interrupt stack because the function is not called from an interrupt.
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321 Just ensure the current stack is the user stack. */
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324 /* Obtain the location of the stack associated with which ever task
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325 pxCurrentTCB is currently pointing to. */
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326 "MOV.L #_pxCurrentTCB, R15 \n" \
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327 "MOV.L [R15], R15 \n" \
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328 "MOV.L [R15], R0 \n" \
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330 /* Restore the registers from the stack of the task pointed to by
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334 /* Accumulator low 32 bits. */
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338 /* Accumulator high 32 bits. */
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341 /* R1 to R15 - R0 is not included as it is the SP. */
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344 /* This pops the remaining registers. */
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350 /*-----------------------------------------------------------*/
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352 void vPortSoftwareInterruptISR( void )
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356 /* Re-enable interrupts. */
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359 /* Move the data that was automatically pushed onto the interrupt stack when
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360 the interrupt occurred from the interrupt stack to the user stack.
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362 R15 is saved before it is clobbered. */
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365 /* Read the user stack pointer. */
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366 "MVFC USP, R15 \n" \
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368 /* Move the address down to the data being moved. */
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369 "SUB #12, R15 \n" \
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370 "MVTC R15, USP \n" \
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372 /* Copy the data across, R15, then PC, then PSW. */
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373 "MOV.L [ R0 ], [ R15 ] \n" \
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374 "MOV.L 4[ R0 ], 4[ R15 ] \n" \
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375 "MOV.L 8[ R0 ], 8[ R15 ] \n" \
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377 /* Move the interrupt stack pointer to its new correct position. */
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380 /* All the rest of the registers are saved directly to the user stack. */
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383 /* Save the rest of the general registers (R15 has been saved already). */
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384 "PUSHM R1-R14 \n" \
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386 /* Save the accumulator. */
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393 /* Shifted left as it is restored to the low order word. */
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394 "SHLL #16, R15 \n" \
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397 /* Save the stack pointer to the TCB. */
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398 "MOV.L #_pxCurrentTCB, R15 \n" \
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399 "MOV.L [ R15 ], R15 \n" \
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400 "MOV.L R0, [ R15 ] \n" \
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402 /* Ensure the interrupt mask is set to the syscall priority while the kernel
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403 structures are being accessed. */
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406 /* Select the next task to run. */
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407 "BSR.A _vTaskSwitchContext \n" \
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409 /* Reset the interrupt mask as no more data structure access is required. */
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412 /* Load the stack pointer of the task that is now selected as the Running
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413 state task from its TCB. */
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414 "MOV.L #_pxCurrentTCB,R15 \n" \
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415 "MOV.L [ R15 ], R15 \n" \
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416 "MOV.L [ R15 ], R0 \n" \
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418 /* Restore the context of the new task. The PSW (Program Status Word) and
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419 PC will be popped by the RTE instruction. */
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428 :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
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431 /*-----------------------------------------------------------*/
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433 void vPortTickISR( void )
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435 /* Re-enabled interrupts. */
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436 __asm volatile( "SETPSW I" );
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438 /* Increment the tick, and perform any processing the new tick value
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439 necessitates. Ensure IPL is at the max syscall value first. */
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440 portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
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442 vTaskIncrementTick();
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444 portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
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446 /* Only select a new task if the preemptive scheduler is being used. */
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447 #if( configUSE_PREEMPTION == 1 )
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451 #if configUSE_TICKLESS_IDLE == 1
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453 /* The CPU woke because of a tick. */
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454 ulTickFlag = pdTRUE;
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456 /* If this is the first tick since exiting tickless mode then the CMT
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457 compare match value needs resetting. */
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458 CMT0.CMCOR = ( unsigned short ) ulMatchValueForOneTick;
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462 /*-----------------------------------------------------------*/
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464 unsigned long ulPortGetIPL( void )
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468 "MVFC PSW, R1 \n" \
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469 "SHLR #24, R1 \n" \
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473 /* This will never get executed, but keeps the compiler from complaining. */
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476 /*-----------------------------------------------------------*/
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478 void vPortSetIPL( unsigned long ulNewIPL )
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483 "MVFC PSW, R5 \n" \
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484 "SHLL #24, R1 \n" \
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485 "AND #-0F000001H, R5 \n" \
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487 "MVTC R5, PSW \n" \
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492 /*-----------------------------------------------------------*/
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494 static void prvSetupTimerInterrupt( void )
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497 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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503 SYSTEM.PRCR.WORD = portLOCK_KEY;
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505 /* Interrupt on compare match. */
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506 CMT0.CMCR.BIT.CMIE = 1;
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508 /* Set the compare match value. */
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509 CMT0.CMCOR = ( unsigned short ) ulMatchValueForOneTick;
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511 /* Divide the PCLK. */
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512 #if portCLOCK_DIVISOR == 512
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514 CMT0.CMCR.BIT.CKS = 3;
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516 #elif portCLOCK_DIVISOR == 128
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518 CMT0.CMCR.BIT.CKS = 2;
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520 #elif portCLOCK_DIVISOR == 32
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522 CMT0.CMCR.BIT.CKS = 1;
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524 #elif portCLOCK_DIVISOR == 8
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526 CMT0.CMCR.BIT.CKS = 0;
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530 #error Invalid portCLOCK_DIVISOR setting
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534 /* Enable the interrupt... */
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535 _IEN( _CMT0_CMI0 ) = 1;
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537 /* ...and set its priority to the application defined kernel priority. */
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538 _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
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540 /* Start the timer. */
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541 CMT.CMSTR0.BIT.STR0 = 1;
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543 /*-----------------------------------------------------------*/
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545 #if configUSE_TICKLESS_IDLE == 1
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547 static void prvSleep( portTickType xExpectedIdleTime )
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549 /* Allow the application to define some pre-sleep processing. */
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550 configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
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552 /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
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553 means the application defined code has already executed the WAIT
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555 if( xExpectedIdleTime > 0 )
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557 __asm volatile( "WAIT" );
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560 /* Allow the application to define some post sleep processing. */
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561 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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564 #endif /* configUSE_TICKLESS_IDLE */
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565 /*-----------------------------------------------------------*/
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567 #if configUSE_TICKLESS_IDLE == 1
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569 void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )
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571 unsigned long ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
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572 eSleepModeStatus eSleepAction;
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574 /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
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576 /* Make sure the CMT reload value does not overflow the counter. */
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577 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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579 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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582 /* Calculate the reload value required to wait xExpectedIdleTime tick
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583 periods. -1 is used because this code will execute part way through
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584 one of the tick periods, and the fraction of a tick period is accounted
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586 ulMatchValue = ( ulMatchValueForOneTick * ( xExpectedIdleTime - 1UL ) );
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587 if( ulMatchValue > ulStoppedTimerCompensation )
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589 /* Compensate for the fact that the CMT is going to be stopped
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591 ulMatchValue -= ulStoppedTimerCompensation;
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594 /* Stop the CMT momentarily. The time the CMT is stopped for is
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595 accounted for as best it can be, but using the tickless mode will
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596 inevitably result in some tiny drift of the time maintained by the
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597 kernel with respect to calendar time. */
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598 CMT.CMSTR0.BIT.STR0 = 0;
\r
599 while( CMT.CMSTR0.BIT.STR0 == 1 )
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601 /* Nothing to do here. */
\r
604 /* Critical section using the global interrupt bit as the i bit is
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605 automatically reset by the WAIT instruction. */
\r
606 __asm volatile( "CLRPSW i" );
\r
608 /* The tick flag is set to false before sleeping. If it is true when
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609 sleep mode is exited then sleep mode was probably exited because the
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610 tick was suppressed for the entire xExpectedIdleTime period. */
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611 ulTickFlag = pdFALSE;
\r
613 /* If a context switch is pending then abandon the low power entry as
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614 the context switch might have been pended by an external interrupt that
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615 requires processing. */
\r
616 eSleepAction = eTaskConfirmSleepModeStatus();
\r
617 if( eSleepAction == eAbortSleep )
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619 /* Restart tick. */
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620 CMT.CMSTR0.BIT.STR0 = 1;
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621 __asm volatile( "SETPSW i" );
\r
623 else if( eSleepAction == eNoTasksWaitingTimeout )
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625 /* Protection off. */
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626 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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628 /* Ready for software standby with all clocks stopped. */
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629 SYSTEM.SBYCR.BIT.SSBY = 1;
\r
631 /* Protection on. */
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632 SYSTEM.PRCR.WORD = portLOCK_KEY;
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634 /* Sleep until something happens. Calling prvSleep() will
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635 automatically reset the i bit in the PSW. */
\r
636 prvSleep( xExpectedIdleTime );
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638 /* Restart the CMT. */
\r
639 CMT.CMSTR0.BIT.STR0 = 1;
\r
643 /* Protection off. */
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644 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
\r
646 /* Ready for deep sleep mode. */
\r
647 SYSTEM.MSTPCRC.BIT.DSLPE = 1;
\r
648 SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
\r
649 SYSTEM.SBYCR.BIT.SSBY = 0;
\r
651 /* Protection on. */
\r
652 SYSTEM.PRCR.WORD = portLOCK_KEY;
\r
654 /* Adjust the match value to take into account that the current
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655 time slice is already partially complete. */
\r
656 ulMatchValue -= ( unsigned long ) CMT0.CMCNT;
\r
657 CMT0.CMCOR = ( unsigned short ) ulMatchValue;
\r
659 /* Restart the CMT to count up to the new match value. */
\r
661 CMT.CMSTR0.BIT.STR0 = 1;
\r
663 /* Sleep until something happens. Calling prvSleep() will
\r
664 automatically reset the i bit in the PSW. */
\r
665 prvSleep( xExpectedIdleTime );
\r
667 /* Stop CMT. Again, the time the SysTick is stopped for is
\r
668 accounted for as best it can be, but using the tickless mode will
\r
669 inevitably result in some tiny drift of the time maintained by the
\r
670 kernel with respect to calendar time. */
\r
671 CMT.CMSTR0.BIT.STR0 = 0;
\r
672 while( CMT.CMSTR0.BIT.STR0 == 1 )
\r
674 /* Nothing to do here. */
\r
677 ulCurrentCount = ( unsigned long ) CMT0.CMCNT;
\r
679 if( ulTickFlag != pdFALSE )
\r
681 /* The tick interrupt has already executed, although because
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682 this function is called with the scheduler suspended the actual
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683 tick processing will not occur until after this function has
\r
684 exited. Reset the match value with whatever remains of this
\r
686 ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
\r
687 CMT0.CMCOR = ( unsigned short ) ulMatchValue;
\r
689 /* The tick interrupt handler will already have pended the tick
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690 processing in the kernel. As the pending tick will be
\r
691 processed as soon as this function exits, the tick value
\r
692 maintained by the tick is stepped forward by one less than the
\r
693 time spent sleeping. The actual stepping of the tick appears
\r
694 later in this function. */
\r
695 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
699 /* Something other than the tick interrupt ended the sleep.
\r
700 How many complete tick periods passed while the processor was
\r
702 ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
\r
704 /* The match value is set to whatever fraction of a single tick
\r
706 ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
\r
707 CMT0.CMCOR = ( unsigned short ) ulMatchValue;
\r
710 /* Restart the CMT so it runs up to the match value. The match value
\r
711 will get set to the value required to generate exactly one tick period
\r
712 the next time the CMT interrupt executes. */
\r
714 CMT.CMSTR0.BIT.STR0 = 1;
\r
716 /* Wind the tick forward by the number of tick periods that the CPU
\r
717 remained in a low power state. */
\r
718 vTaskStepTick( ulCompleteTickPeriods );
\r
722 #endif /* configUSE_TICKLESS_IDLE */
\r