2 FreeRTOS V7.5.3 - Copyright (C) 2013 Real Time Engineers Ltd.
\r
5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
7 ***************************************************************************
\r
9 * FreeRTOS provides completely free yet professionally developed, *
\r
10 * robust, strictly quality controlled, supported, and cross *
\r
11 * platform software that has become a de facto standard. *
\r
13 * Help yourself get started quickly and support the FreeRTOS *
\r
14 * project by purchasing a FreeRTOS tutorial book, reference *
\r
15 * manual, or both from: http://www.FreeRTOS.org/Documentation *
\r
19 ***************************************************************************
\r
21 This file is part of the FreeRTOS distribution.
\r
23 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
24 the terms of the GNU General Public License (version 2) as published by the
\r
25 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
\r
27 >>! NOTE: The modification to the GPL is included to allow you to distribute
\r
28 >>! a combined work that includes FreeRTOS without being obliged to provide
\r
29 >>! the source code for proprietary components outside of the FreeRTOS
\r
32 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
33 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
34 FOR A PARTICULAR PURPOSE. Full license text is available from the following
\r
35 link: http://www.freertos.org/a00114.html
\r
39 ***************************************************************************
\r
41 * Having a problem? Start by reading the FAQ "My application does *
\r
42 * not run, what could be wrong?" *
\r
44 * http://www.FreeRTOS.org/FAQHelp.html *
\r
46 ***************************************************************************
\r
48 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
\r
49 license and Real Time Engineers Ltd. contact details.
\r
51 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
52 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
53 compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
55 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
\r
56 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
57 licenses offer ticketed support, indemnification and middleware.
\r
59 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
60 engineered and independently SIL3 certified version for use in safety and
\r
61 mission critical applications that require provable dependability.
\r
66 /*-----------------------------------------------------------
\r
67 * Implementation of functions defined in portable.h for the SH2A port.
\r
68 *----------------------------------------------------------*/
\r
70 /* Standard C includes. */
\r
73 /* Scheduler includes. */
\r
74 #include "FreeRTOS.h"
\r
77 /* Library includes. */
\r
80 /* Hardware specifics. */
\r
81 #include "iodefine.h"
\r
83 /*-----------------------------------------------------------*/
\r
85 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
\r
86 PSW is set with U and I set, and PM and IPL clear. */
\r
87 #define portINITIAL_PSW ( ( portSTACK_TYPE ) 0x00030000 )
\r
89 /* The peripheral clock is divided by this value before being supplying the
\r
91 #if ( configUSE_TICKLESS_IDLE == 0 )
\r
92 /* If tickless idle is not used then the divisor can be fixed. */
\r
93 #define portCLOCK_DIVISOR 8UL
\r
94 #elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
\r
95 #define portCLOCK_DIVISOR 512UL
\r
96 #elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
\r
97 #define portCLOCK_DIVISOR 128UL
\r
98 #elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
\r
99 #define portCLOCK_DIVISOR 32UL
\r
101 #define portCLOCK_DIVISOR 8UL
\r
104 /* These macros allow a critical section to be added around the call to
\r
105 xTaskIncrementTick(), which is only ever called from interrupts at the kernel
\r
106 priority - ie a known priority. Therefore these local macros are a slight
\r
107 optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
\r
108 which would require the old IPL to be read first and stored in a local variable. */
\r
109 #define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
\r
110 #define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
\r
112 /* Keys required to lock and unlock access to certain system registers
\r
114 #define portUNLOCK_KEY 0xA50B
\r
115 #define portLOCK_KEY 0xA500
\r
117 /*-----------------------------------------------------------*/
\r
120 * Function to start the first task executing - written in asm code as direct
\r
121 * access to registers is required.
\r
123 static void prvStartFirstTask( void ) __attribute__((naked));
\r
126 * Software interrupt handler. Performs the actual context switch (saving and
\r
127 * restoring of registers). Written in asm code as direct register access is
\r
130 void vPortSoftwareInterruptISR( void ) __attribute__((naked));
\r
133 * The tick interrupt handler.
\r
135 void vPortTickISR( void ) __attribute__((interrupt));
\r
138 * Sets up the periodic ISR used for the RTOS tick using the CMT.
\r
139 * The application writer can define configSETUP_TICK_INTERRUPT() (in
\r
140 * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
\r
141 * in place of prvSetupTimerInterrupt().
\r
143 static void prvSetupTimerInterrupt( void );
\r
144 #ifndef configSETUP_TICK_INTERRUPT
\r
145 /* The user has not provided their own tick interrupt configuration so use
\r
146 the definition in this file (which uses the interval timer). */
\r
147 #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
\r
148 #endif /* configSETUP_TICK_INTERRUPT */
\r
151 * Called after the sleep mode registers have been configured, prvSleep()
\r
152 * executes the pre and post sleep macros, and actually calls the wait
\r
155 #if configUSE_TICKLESS_IDLE == 1
\r
156 static void prvSleep( portTickType xExpectedIdleTime );
\r
157 #endif /* configUSE_TICKLESS_IDLE */
\r
159 /*-----------------------------------------------------------*/
\r
161 /* Used in the context save and restore code. */
\r
162 extern void *pxCurrentTCB;
\r
164 /* Calculate how many clock increments make up a single tick period. */
\r
165 static const unsigned long ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
\r
167 #if configUSE_TICKLESS_IDLE == 1
\r
169 /* Holds the maximum number of ticks that can be suppressed - which is
\r
170 basically how far into the future an interrupt can be generated. Set
\r
171 during initialisation. This is the maximum possible value that the
\r
172 compare match register can hold divided by ulMatchValueForOneTick. */
\r
173 static const portTickType xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
\r
175 /* Flag set from the tick interrupt to allow the sleep processing to know if
\r
176 sleep mode was exited because of a tick interrupt, or an interrupt
\r
177 generated by something else. */
\r
178 static volatile uint32_t ulTickFlag = pdFALSE;
\r
180 /* The CMT counter is stopped temporarily each time it is re-programmed.
\r
181 The following constant offsets the CMT counter match value by the number of
\r
182 CMT counts that would typically be missed while the counter was stopped to
\r
183 compensate for the lost time. The large difference between the divided CMT
\r
184 clock and the CPU clock means it is likely ulStoppedTimerCompensation will
\r
185 equal zero - and be optimised away. */
\r
186 static const unsigned long ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
\r
190 /*-----------------------------------------------------------*/
\r
193 * See header file for description.
\r
195 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
\r
197 /* Offset to end up on 8 byte boundary. */
\r
200 /* R0 is not included as it is the stack pointer. */
\r
201 *pxTopOfStack = 0x00;
\r
203 *pxTopOfStack = 0x00;
\r
205 *pxTopOfStack = portINITIAL_PSW;
\r
207 *pxTopOfStack = ( portSTACK_TYPE ) pxCode;
\r
209 /* When debugging it can be useful if every register is set to a known
\r
210 value. Otherwise code space can be saved by just setting the registers
\r
211 that need to be set. */
\r
212 #ifdef USE_FULL_REGISTER_INITIALISATION
\r
215 *pxTopOfStack = 0x12345678; /* r15. */
\r
217 *pxTopOfStack = 0xaaaabbbb;
\r
219 *pxTopOfStack = 0xdddddddd;
\r
221 *pxTopOfStack = 0xcccccccc;
\r
223 *pxTopOfStack = 0xbbbbbbbb;
\r
225 *pxTopOfStack = 0xaaaaaaaa;
\r
227 *pxTopOfStack = 0x99999999;
\r
229 *pxTopOfStack = 0x88888888;
\r
231 *pxTopOfStack = 0x77777777;
\r
233 *pxTopOfStack = 0x66666666;
\r
235 *pxTopOfStack = 0x55555555;
\r
237 *pxTopOfStack = 0x44444444;
\r
239 *pxTopOfStack = 0x33333333;
\r
241 *pxTopOfStack = 0x22222222;
\r
246 /* Leave space for the registers that will get popped from the stack
\r
247 when the task first starts executing. */
\r
248 pxTopOfStack -= 15;
\r
252 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R1 */
\r
254 *pxTopOfStack = 0x12345678; /* Accumulator. */
\r
256 *pxTopOfStack = 0x87654321; /* Accumulator. */
\r
258 return pxTopOfStack;
\r
260 /*-----------------------------------------------------------*/
\r
262 portBASE_TYPE xPortStartScheduler( void )
\r
264 /* Use pxCurrentTCB just so it does not get optimised away. */
\r
265 if( pxCurrentTCB != NULL )
\r
267 /* Call an application function to set up the timer that will generate
\r
268 the tick interrupt. This way the application can decide which
\r
269 peripheral to use. If tickless mode is used then the default
\r
270 implementation defined in this file (which uses CMT0) should not be
\r
272 configSETUP_TICK_INTERRUPT();
\r
274 /* Enable the software interrupt. */
\r
275 _IEN( _ICU_SWINT ) = 1;
\r
277 /* Ensure the software interrupt is clear. */
\r
278 _IR( _ICU_SWINT ) = 0;
\r
280 /* Ensure the software interrupt is set to the kernel priority. */
\r
281 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
\r
283 /* Start the first task. */
\r
284 prvStartFirstTask();
\r
287 /* Execution should not reach here as the tasks are now running!
\r
288 prvSetupTimerInterrupt() is called here to prevent the compiler outputting
\r
289 a warning about a statically declared function not being referenced in the
\r
290 case that the application writer has provided their own tick interrupt
\r
291 configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
\r
292 their own routine will be called in place of prvSetupTimerInterrupt()). */
\r
293 prvSetupTimerInterrupt();
\r
295 /* Should not get here. */
\r
298 /*-----------------------------------------------------------*/
\r
300 void vPortEndScheduler( void )
\r
302 /* Not implemented as there is nothing to return to. */
\r
304 /*-----------------------------------------------------------*/
\r
306 static void prvStartFirstTask( void )
\r
310 /* When starting the scheduler there is nothing that needs moving to the
\r
311 interrupt stack because the function is not called from an interrupt.
\r
312 Just ensure the current stack is the user stack. */
\r
315 /* Obtain the location of the stack associated with which ever task
\r
316 pxCurrentTCB is currently pointing to. */
\r
317 "MOV.L #_pxCurrentTCB, R15 \n" \
\r
318 "MOV.L [R15], R15 \n" \
\r
319 "MOV.L [R15], R0 \n" \
\r
321 /* Restore the registers from the stack of the task pointed to by
\r
325 /* Accumulator low 32 bits. */
\r
329 /* Accumulator high 32 bits. */
\r
332 /* R1 to R15 - R0 is not included as it is the SP. */
\r
335 /* This pops the remaining registers. */
\r
341 /*-----------------------------------------------------------*/
\r
343 void vPortSoftwareInterruptISR( void )
\r
347 /* Re-enable interrupts. */
\r
350 /* Move the data that was automatically pushed onto the interrupt stack when
\r
351 the interrupt occurred from the interrupt stack to the user stack.
\r
353 R15 is saved before it is clobbered. */
\r
356 /* Read the user stack pointer. */
\r
357 "MVFC USP, R15 \n" \
\r
359 /* Move the address down to the data being moved. */
\r
360 "SUB #12, R15 \n" \
\r
361 "MVTC R15, USP \n" \
\r
363 /* Copy the data across, R15, then PC, then PSW. */
\r
364 "MOV.L [ R0 ], [ R15 ] \n" \
\r
365 "MOV.L 4[ R0 ], 4[ R15 ] \n" \
\r
366 "MOV.L 8[ R0 ], 8[ R15 ] \n" \
\r
368 /* Move the interrupt stack pointer to its new correct position. */
\r
371 /* All the rest of the registers are saved directly to the user stack. */
\r
374 /* Save the rest of the general registers (R15 has been saved already). */
\r
375 "PUSHM R1-R14 \n" \
\r
377 /* Save the accumulator. */
\r
384 /* Shifted left as it is restored to the low order word. */
\r
385 "SHLL #16, R15 \n" \
\r
388 /* Save the stack pointer to the TCB. */
\r
389 "MOV.L #_pxCurrentTCB, R15 \n" \
\r
390 "MOV.L [ R15 ], R15 \n" \
\r
391 "MOV.L R0, [ R15 ] \n" \
\r
393 /* Ensure the interrupt mask is set to the syscall priority while the kernel
\r
394 structures are being accessed. */
\r
397 /* Select the next task to run. */
\r
398 "BSR.A _vTaskSwitchContext \n" \
\r
400 /* Reset the interrupt mask as no more data structure access is required. */
\r
403 /* Load the stack pointer of the task that is now selected as the Running
\r
404 state task from its TCB. */
\r
405 "MOV.L #_pxCurrentTCB,R15 \n" \
\r
406 "MOV.L [ R15 ], R15 \n" \
\r
407 "MOV.L [ R15 ], R0 \n" \
\r
409 /* Restore the context of the new task. The PSW (Program Status Word) and
\r
410 PC will be popped by the RTE instruction. */
\r
419 :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
\r
422 /*-----------------------------------------------------------*/
\r
424 void vPortTickISR( void )
\r
426 /* Re-enabled interrupts. */
\r
427 __asm volatile( "SETPSW I" );
\r
429 /* Increment the tick, and perform any processing the new tick value
\r
430 necessitates. Ensure IPL is at the max syscall value first. */
\r
431 portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
\r
433 if( xTaskIncrementTick() != pdFALSE )
\r
438 portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
\r
440 #if configUSE_TICKLESS_IDLE == 1
\r
442 /* The CPU woke because of a tick. */
\r
443 ulTickFlag = pdTRUE;
\r
445 /* If this is the first tick since exiting tickless mode then the CMT
\r
446 compare match value needs resetting. */
\r
447 CMT0.CMCOR = ( unsigned short ) ulMatchValueForOneTick;
\r
451 /*-----------------------------------------------------------*/
\r
453 unsigned long ulPortGetIPL( void )
\r
457 "MVFC PSW, R1 \n" \
\r
458 "SHLR #24, R1 \n" \
\r
462 /* This will never get executed, but keeps the compiler from complaining. */
\r
465 /*-----------------------------------------------------------*/
\r
467 void vPortSetIPL( unsigned long ulNewIPL )
\r
472 "MVFC PSW, R5 \n" \
\r
473 "SHLL #24, R1 \n" \
\r
474 "AND #-0F000001H, R5 \n" \
\r
476 "MVTC R5, PSW \n" \
\r
481 /*-----------------------------------------------------------*/
\r
483 static void prvSetupTimerInterrupt( void )
\r
486 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
\r
492 SYSTEM.PRCR.WORD = portLOCK_KEY;
\r
494 /* Interrupt on compare match. */
\r
495 CMT0.CMCR.BIT.CMIE = 1;
\r
497 /* Set the compare match value. */
\r
498 CMT0.CMCOR = ( unsigned short ) ulMatchValueForOneTick;
\r
500 /* Divide the PCLK. */
\r
501 #if portCLOCK_DIVISOR == 512
\r
503 CMT0.CMCR.BIT.CKS = 3;
\r
505 #elif portCLOCK_DIVISOR == 128
\r
507 CMT0.CMCR.BIT.CKS = 2;
\r
509 #elif portCLOCK_DIVISOR == 32
\r
511 CMT0.CMCR.BIT.CKS = 1;
\r
513 #elif portCLOCK_DIVISOR == 8
\r
515 CMT0.CMCR.BIT.CKS = 0;
\r
519 #error Invalid portCLOCK_DIVISOR setting
\r
523 /* Enable the interrupt... */
\r
524 _IEN( _CMT0_CMI0 ) = 1;
\r
526 /* ...and set its priority to the application defined kernel priority. */
\r
527 _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
\r
529 /* Start the timer. */
\r
530 CMT.CMSTR0.BIT.STR0 = 1;
\r
532 /*-----------------------------------------------------------*/
\r
534 #if configUSE_TICKLESS_IDLE == 1
\r
536 static void prvSleep( portTickType xExpectedIdleTime )
\r
538 /* Allow the application to define some pre-sleep processing. */
\r
539 configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
\r
541 /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
\r
542 means the application defined code has already executed the WAIT
\r
544 if( xExpectedIdleTime > 0 )
\r
546 __asm volatile( "WAIT" );
\r
549 /* Allow the application to define some post sleep processing. */
\r
550 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
\r
553 #endif /* configUSE_TICKLESS_IDLE */
\r
554 /*-----------------------------------------------------------*/
\r
556 #if configUSE_TICKLESS_IDLE == 1
\r
558 void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )
\r
560 unsigned long ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
\r
561 eSleepModeStatus eSleepAction;
\r
563 /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
\r
565 /* Make sure the CMT reload value does not overflow the counter. */
\r
566 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
\r
568 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
\r
571 /* Calculate the reload value required to wait xExpectedIdleTime tick
\r
573 ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
\r
574 if( ulMatchValue > ulStoppedTimerCompensation )
\r
576 /* Compensate for the fact that the CMT is going to be stopped
\r
578 ulMatchValue -= ulStoppedTimerCompensation;
\r
581 /* Stop the CMT momentarily. The time the CMT is stopped for is
\r
582 accounted for as best it can be, but using the tickless mode will
\r
583 inevitably result in some tiny drift of the time maintained by the
\r
584 kernel with respect to calendar time. */
\r
585 CMT.CMSTR0.BIT.STR0 = 0;
\r
586 while( CMT.CMSTR0.BIT.STR0 == 1 )
\r
588 /* Nothing to do here. */
\r
591 /* Critical section using the global interrupt bit as the i bit is
\r
592 automatically reset by the WAIT instruction. */
\r
593 __asm volatile( "CLRPSW i" );
\r
595 /* The tick flag is set to false before sleeping. If it is true when
\r
596 sleep mode is exited then sleep mode was probably exited because the
\r
597 tick was suppressed for the entire xExpectedIdleTime period. */
\r
598 ulTickFlag = pdFALSE;
\r
600 /* If a context switch is pending then abandon the low power entry as
\r
601 the context switch might have been pended by an external interrupt that
\r
602 requires processing. */
\r
603 eSleepAction = eTaskConfirmSleepModeStatus();
\r
604 if( eSleepAction == eAbortSleep )
\r
606 /* Restart tick. */
\r
607 CMT.CMSTR0.BIT.STR0 = 1;
\r
608 __asm volatile( "SETPSW i" );
\r
610 else if( eSleepAction == eNoTasksWaitingTimeout )
\r
612 /* Protection off. */
\r
613 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
\r
615 /* Ready for software standby with all clocks stopped. */
\r
616 SYSTEM.SBYCR.BIT.SSBY = 1;
\r
618 /* Protection on. */
\r
619 SYSTEM.PRCR.WORD = portLOCK_KEY;
\r
621 /* Sleep until something happens. Calling prvSleep() will
\r
622 automatically reset the i bit in the PSW. */
\r
623 prvSleep( xExpectedIdleTime );
\r
625 /* Restart the CMT. */
\r
626 CMT.CMSTR0.BIT.STR0 = 1;
\r
630 /* Protection off. */
\r
631 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
\r
633 /* Ready for deep sleep mode. */
\r
634 SYSTEM.MSTPCRC.BIT.DSLPE = 1;
\r
635 SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
\r
636 SYSTEM.SBYCR.BIT.SSBY = 0;
\r
638 /* Protection on. */
\r
639 SYSTEM.PRCR.WORD = portLOCK_KEY;
\r
641 /* Adjust the match value to take into account that the current
\r
642 time slice is already partially complete. */
\r
643 ulMatchValue -= ( unsigned long ) CMT0.CMCNT;
\r
644 CMT0.CMCOR = ( unsigned short ) ulMatchValue;
\r
646 /* Restart the CMT to count up to the new match value. */
\r
648 CMT.CMSTR0.BIT.STR0 = 1;
\r
650 /* Sleep until something happens. Calling prvSleep() will
\r
651 automatically reset the i bit in the PSW. */
\r
652 prvSleep( xExpectedIdleTime );
\r
654 /* Stop CMT. Again, the time the SysTick is stopped for is
\r
655 accounted for as best it can be, but using the tickless mode will
\r
656 inevitably result in some tiny drift of the time maintained by the
\r
657 kernel with respect to calendar time. */
\r
658 CMT.CMSTR0.BIT.STR0 = 0;
\r
659 while( CMT.CMSTR0.BIT.STR0 == 1 )
\r
661 /* Nothing to do here. */
\r
664 ulCurrentCount = ( unsigned long ) CMT0.CMCNT;
\r
666 if( ulTickFlag != pdFALSE )
\r
668 /* The tick interrupt has already executed, although because
\r
669 this function is called with the scheduler suspended the actual
\r
670 tick processing will not occur until after this function has
\r
671 exited. Reset the match value with whatever remains of this
\r
673 ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
\r
674 CMT0.CMCOR = ( unsigned short ) ulMatchValue;
\r
676 /* The tick interrupt handler will already have pended the tick
\r
677 processing in the kernel. As the pending tick will be
\r
678 processed as soon as this function exits, the tick value
\r
679 maintained by the tick is stepped forward by one less than the
\r
680 time spent sleeping. The actual stepping of the tick appears
\r
681 later in this function. */
\r
682 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
686 /* Something other than the tick interrupt ended the sleep.
\r
687 How many complete tick periods passed while the processor was
\r
689 ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
\r
691 /* The match value is set to whatever fraction of a single tick
\r
693 ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
\r
694 CMT0.CMCOR = ( unsigned short ) ulMatchValue;
\r
697 /* Restart the CMT so it runs up to the match value. The match value
\r
698 will get set to the value required to generate exactly one tick period
\r
699 the next time the CMT interrupt executes. */
\r
701 CMT.CMSTR0.BIT.STR0 = 1;
\r
703 /* Wind the tick forward by the number of tick periods that the CPU
\r
704 remained in a low power state. */
\r
705 vTaskStepTick( ulCompleteTickPeriods );
\r
709 #endif /* configUSE_TICKLESS_IDLE */
\r