git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/RX600v2/port.c

   1 /*\r
   2  * FreeRTOS Kernel V10.0.0\r
   3  * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software. If you wish to use our Amazon\r
  14  * FreeRTOS name, please do so in a fair use way that does not cause confusion.\r
  15  *\r
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  18  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  19  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  20  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  22  *\r
  23  * http://www.FreeRTOS.org\r
  24  * http://aws.amazon.com/freertos\r
  25  *\r
  26  * 1 tab == 4 spaces!\r
  27  */\r
  28 \r
  29 /*-----------------------------------------------------------\r
  30  * Implementation of functions defined in portable.h for the SH2A port.\r
  31  *----------------------------------------------------------*/\r
  32 \r
  33 /* Scheduler includes. */\r
  34 #include "FreeRTOS.h"\r
  35 #include "task.h"\r
  36 \r
  37 /* Library includes. */\r
  38 #include "string.h"\r
  39 \r
  40 /* Hardware specifics. */\r
  41 #include "iodefine.h"\r
  42 \r
  43 /*-----------------------------------------------------------*/\r
  44 \r
  45 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore\r
  46 PSW is set with U and I set, and PM and IPL clear. */\r
  47 #define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )\r
  48 #define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )\r
  49 \r
  50 /* These macros allow a critical section to be added around the call to\r
  51 xTaskIncrementTick(), which is only ever called from interrupts at the kernel\r
  52 priority - ie a known priority.  Therefore these local macros are a slight\r
  53 optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,\r
  54 which would require the old IPL to be read first and stored in a local variable. */\r
  55 #define portMASK_INTERRUPTS_FROM_KERNEL_ISR()   __asm volatile ( "MVTIPL        %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )\r
  56 #define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR()         __asm volatile ( "MVTIPL        %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )\r
  57 \r
  58 /*-----------------------------------------------------------*/\r
  59 \r
  60 /*\r
  61  * Function to start the first task executing - written in asm code as direct\r
  62  * access to registers is required.\r
  63  */\r
  64 static void prvStartFirstTask( void ) __attribute__((naked));\r
  65 \r
  66 /*\r
  67  * Software interrupt handler.  Performs the actual context switch (saving and\r
  68  * restoring of registers).  Written in asm code as direct register access is\r
  69  * required.\r
  70  */\r
  71 void vSoftwareInterruptISR( void ) __attribute__((naked));\r
  72 \r
  73 /*\r
  74  * The tick interrupt handler.\r
  75  */\r
  76 void vTickISR( void ) __attribute__((interrupt));\r
  77 \r
  78 /*-----------------------------------------------------------*/\r
  79 \r
  80 extern void *pxCurrentTCB;\r
  81 \r
  82 /*-----------------------------------------------------------*/\r
  83 \r
  84 /*\r
  85  * See header file for description.\r
  86  */\r
  87 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
  88 {\r
  89         /* R0 is not included as it is the stack pointer. */\r
  90 \r
  91         *pxTopOfStack = 0x00;\r
  92         pxTopOfStack--;\r
  93         *pxTopOfStack = portINITIAL_PSW;\r
  94         pxTopOfStack--;\r
  95         *pxTopOfStack = ( StackType_t ) pxCode;\r
  96 \r
  97         /* When debugging it can be useful if every register is set to a known\r
  98         value.  Otherwise code space can be saved by just setting the registers\r
  99         that need to be set. */\r
 100         #ifdef USE_FULL_REGISTER_INITIALISATION\r
 101         {\r
 102                 pxTopOfStack--;\r
 103                 *pxTopOfStack = 0xffffffff;     /* r15. */\r
 104                 pxTopOfStack--;\r
 105                 *pxTopOfStack = 0xeeeeeeee;\r
 106                 pxTopOfStack--;\r
 107                 *pxTopOfStack = 0xdddddddd;\r
 108                 pxTopOfStack--;\r
 109                 *pxTopOfStack = 0xcccccccc;\r
 110                 pxTopOfStack--;\r
 111                 *pxTopOfStack = 0xbbbbbbbb;\r
 112                 pxTopOfStack--;\r
 113                 *pxTopOfStack = 0xaaaaaaaa;\r
 114                 pxTopOfStack--;\r
 115                 *pxTopOfStack = 0x99999999;\r
 116                 pxTopOfStack--;\r
 117                 *pxTopOfStack = 0x88888888;\r
 118                 pxTopOfStack--;\r
 119                 *pxTopOfStack = 0x77777777;\r
 120                 pxTopOfStack--;\r
 121                 *pxTopOfStack = 0x66666666;\r
 122                 pxTopOfStack--;\r
 123                 *pxTopOfStack = 0x55555555;\r
 124                 pxTopOfStack--;\r
 125                 *pxTopOfStack = 0x44444444;\r
 126                 pxTopOfStack--;\r
 127                 *pxTopOfStack = 0x33333333;\r
 128                 pxTopOfStack--;\r
 129                 *pxTopOfStack = 0x22222222;\r
 130                 pxTopOfStack--;\r
 131         }\r
 132         #else\r
 133         {\r
 134                 pxTopOfStack -= 15;\r
 135         }\r
 136         #endif\r
 137 \r
 138         *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */\r
 139         pxTopOfStack--;\r
 140         *pxTopOfStack = portINITIAL_FPSW;\r
 141         pxTopOfStack--;\r
 142         *pxTopOfStack = 0x11111111; /* Accumulator 0. */\r
 143         pxTopOfStack--;\r
 144         *pxTopOfStack = 0x22222222; /* Accumulator 0. */\r
 145         pxTopOfStack--;\r
 146         *pxTopOfStack = 0x33333333; /* Accumulator 0. */\r
 147         pxTopOfStack--;\r
 148         *pxTopOfStack = 0x44444444; /* Accumulator 1. */\r
 149         pxTopOfStack--;\r
 150         *pxTopOfStack = 0x55555555; /* Accumulator 1. */\r
 151         pxTopOfStack--;\r
 152         *pxTopOfStack = 0x66666666; /* Accumulator 1. */\r
 153 \r
 154         return pxTopOfStack;\r
 155 }\r
 156 /*-----------------------------------------------------------*/\r
 157 \r
 158 BaseType_t xPortStartScheduler( void )\r
 159 {\r
 160 extern void vApplicationSetupTimerInterrupt( void );\r
 161 \r
 162         /* Use pxCurrentTCB just so it does not get optimised away. */\r
 163         if( pxCurrentTCB != NULL )\r
 164         {\r
 165                 /* Call an application function to set up the timer that will generate the\r
 166                 tick interrupt.  This way the application can decide which peripheral to\r
 167                 use.  A demo application is provided to show a suitable example. */\r
 168                 vApplicationSetupTimerInterrupt();\r
 169 \r
 170                 /* Enable the software interrupt. */\r
 171                 _IEN( _ICU_SWINT ) = 1;\r
 172 \r
 173                 /* Ensure the software interrupt is clear. */\r
 174                 _IR( _ICU_SWINT ) = 0;\r
 175 \r
 176                 /* Ensure the software interrupt is set to the kernel priority. */\r
 177                 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;\r
 178 \r
 179                 /* Start the first task. */\r
 180                 prvStartFirstTask();\r
 181         }\r
 182 \r
 183         /* Should not get here. */\r
 184         return pdFAIL;\r
 185 }\r
 186 /*-----------------------------------------------------------*/\r
 187 \r
 188 void vPortEndScheduler( void )\r
 189 {\r
 190         /* Not implemented in ports where there is nothing to return to.\r
 191         Artificially force an assert. */\r
 192         configASSERT( pxCurrentTCB == NULL );\r
 193 }\r
 194 /*-----------------------------------------------------------*/\r
 195 \r
 196 static void prvStartFirstTask( void )\r
 197 {\r
 198         __asm volatile\r
 199         (\r
 200                 /* When starting the scheduler there is nothing that needs moving to the\r
 201                 interrupt stack because the function is not called from an interrupt.\r
 202                 Just ensure the current stack is the user stack. */\r
 203                 "SETPSW         U                                               \n" \\r
 204 \r
 205                 /* Obtain the location of the stack associated with which ever task\r
 206                 pxCurrentTCB is currently pointing to. */\r
 207                 "MOV.L          #_pxCurrentTCB, R15             \n" \\r
 208                 "MOV.L          [R15], R15                              \n" \\r
 209                 "MOV.L          [R15], R0                               \n" \\r
 210 \r
 211                 /* Restore the registers from the stack of the task pointed to by\r
 212                 pxCurrentTCB. */\r
 213             "POP                R15                                             \n" \\r
 214 \r
 215                 /* Accumulator low 32 bits. */\r
 216             "MVTACLO    R15, A0                                 \n" \\r
 217             "POP                R15                                             \n" \\r
 218 \r
 219             /* Accumulator high 32 bits. */\r
 220             "MVTACHI    R15, A0                                 \n" \\r
 221             "POP                R15                                             \n" \\r
 222 \r
 223             /* Accumulator guard. */\r
 224             "MVTACGU    R15, A0                                 \n" \\r
 225             "POP                R15                                             \n" \\r
 226 \r
 227             /* Accumulator low 32 bits. */\r
 228             "MVTACLO    R15, A1                                 \n" \\r
 229             "POP                R15                                             \n" \\r
 230 \r
 231             /* Accumulator high 32 bits. */\r
 232             "MVTACHI    R15, A1                                 \n" \\r
 233             "POP                R15                                             \n" \\r
 234 \r
 235             /* Accumulator guard. */\r
 236             "MVTACGU    R15, A1                                 \n" \\r
 237             "POP                R15                                             \n" \\r
 238 \r
 239                 /* Floating point status word. */\r
 240             "MVTC               R15, FPSW                               \n" \\r
 241 \r
 242                 /* R1 to R15 - R0 is not included as it is the SP. */\r
 243             "POPM               R1-R15                                  \n" \\r
 244 \r
 245                 /* This pops the remaining registers. */\r
 246             "RTE                                                                \n" \\r
 247             "NOP                                                                \n" \\r
 248             "NOP                                                                \n"\r
 249         );\r
 250 }\r
 251 /*-----------------------------------------------------------*/\r
 252 \r
 253 void vSoftwareInterruptISR( void )\r
 254 {\r
 255         __asm volatile\r
 256         (\r
 257                 /* Re-enable interrupts. */\r
 258                 "SETPSW         I                                                       \n" \\r
 259 \r
 260                 /* Move the data that was automatically pushed onto the interrupt stack when\r
 261                 the interrupt occurred from the interrupt stack to the user stack.\r
 262 \r
 263                 R15 is saved before it is clobbered. */\r
 264                 "PUSH.L         R15                                                     \n" \\r
 265 \r
 266                 /* Read the user stack pointer. */\r
 267                 "MVFC           USP, R15                                        \n" \\r
 268 \r
 269                 /* Move the address down to the data being moved. */\r
 270                 "SUB            #12, R15                                        \n" \\r
 271                 "MVTC           R15, USP                                        \n" \\r
 272 \r
 273                 /* Copy the data across, R15, then PC, then PSW. */\r
 274                 "MOV.L          [ R0 ], [ R15 ]                         \n" \\r
 275                 "MOV.L          4[ R0 ], 4[ R15 ]                       \n" \\r
 276                 "MOV.L          8[ R0 ], 8[ R15 ]                       \n" \\r
 277 \r
 278                 /* Move the interrupt stack pointer to its new correct position. */\r
 279                 "ADD            #12, R0                                         \n" \\r
 280 \r
 281                 /* All the rest of the registers are saved directly to the user stack. */\r
 282                 "SETPSW         U                                                       \n" \\r
 283 \r
 284                 /* Save the rest of the general registers (R15 has been saved already). */\r
 285                 "PUSHM          R1-R14                                          \n" \\r
 286 \r
 287                 /* Save the FPSW and accumulator. */\r
 288                 "MVFC           FPSW, R15                                       \n" \\r
 289                 "PUSH.L         R15                                                     \n" \\r
 290                 "MVFACGU        #0, A1, R15                                     \n" \\r
 291                 "PUSH.L         R15                                                     \n" \\r
 292                 "MVFACHI        #0, A1, R15                                     \n" \\r
 293                 "PUSH.L         R15                                                     \n" \\r
 294                 /* Low order word. */\r
 295                 "MVFACLO        #0, A1, R15                                     \n" \\r
 296                 "PUSH.L         R15                                                     \n" \\r
 297                 "MVFACGU        #0, A0, R15                                     \n" \\r
 298                 "PUSH.L         R15                                                     \n" \\r
 299                 "MVFACHI        #0, A0, R15                                     \n" \\r
 300                 "PUSH.L         R15                                                     \n" \\r
 301                 /* Low order word. */\r
 302                 "MVFACLO        #0, A0, R15                                     \n" \\r
 303                 "PUSH.L         R15                                                     \n" \\r
 304 \r
 305                 /* Save the stack pointer to the TCB. */\r
 306                 "MOV.L          #_pxCurrentTCB, R15                     \n" \\r
 307                 "MOV.L          [ R15 ], R15                            \n" \\r
 308                 "MOV.L          R0, [ R15 ]                                     \n" \\r
 309 \r
 310                 /* Ensure the interrupt mask is set to the syscall priority while the kernel\r
 311                 structures are being accessed. */\r
 312                 "MVTIPL         %0                                                      \n" \\r
 313 \r
 314                 /* Select the next task to run. */\r
 315                 "BSR.A          _vTaskSwitchContext                     \n" \\r
 316 \r
 317                 /* Reset the interrupt mask as no more data structure access is required. */\r
 318                 "MVTIPL         %1                                                      \n" \\r
 319 \r
 320                 /* Load the stack pointer of the task that is now selected as the Running\r
 321                 state task from its TCB. */\r
 322                 "MOV.L          #_pxCurrentTCB,R15                      \n" \\r
 323                 "MOV.L          [ R15 ], R15                            \n" \\r
 324                 "MOV.L          [ R15 ], R0                                     \n" \\r
 325 \r
 326                 /* Restore the context of the new task.  The PSW (Program Status Word) and\r
 327                 PC will be popped by the RTE instruction. */\r
 328             "POP                R15                                                     \n" \\r
 329 \r
 330             /* Accumulator low 32 bits. */\r
 331             "MVTACLO    R15, A0                                         \n" \\r
 332             "POP                R15                                                     \n" \\r
 333 \r
 334             /* Accumulator high 32 bits. */\r
 335             "MVTACHI    R15, A0                                         \n" \\r
 336             "POP                R15                                                     \n" \\r
 337 \r
 338             /* Accumulator guard. */\r
 339             "MVTACGU    R15, A0                                         \n" \\r
 340             "POP                R15                                                     \n" \\r
 341 \r
 342             /* Accumulator low 32 bits. */\r
 343             "MVTACLO    R15, A1                                         \n" \\r
 344             "POP                R15                                                     \n" \\r
 345 \r
 346             /* Accumulator high 32 bits. */\r
 347             "MVTACHI    R15, A1                                         \n" \\r
 348             "POP                R15                                                     \n" \\r
 349 \r
 350             /* Accumulator guard. */\r
 351             "MVTACGU    R15, A1                                         \n" \\r
 352                 "POP            R15                                                     \n" \\r
 353                 "MVTC           R15, FPSW                                       \n" \\r
 354                 "POPM           R1-R15                                          \n" \\r
 355                 "RTE                                                                    \n" \\r
 356                 "NOP                                                                    \n" \\r
 357                 "NOP                                                                      "\r
 358                 :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)\r
 359         );\r
 360 }\r
 361 /*-----------------------------------------------------------*/\r
 362 \r
 363 void vTickISR( void )\r
 364 {\r
 365         /* Re-enabled interrupts. */\r
 366         __asm volatile( "SETPSW I" );\r
 367 \r
 368         /* Increment the tick, and perform any processing the new tick value\r
 369         necessitates.  Ensure IPL is at the max syscall value first. */\r
 370         portMASK_INTERRUPTS_FROM_KERNEL_ISR();\r
 371         {\r
 372                 if( xTaskIncrementTick() != pdFALSE )\r
 373                 {\r
 374                         taskYIELD();\r
 375                 }\r
 376         }\r
 377         portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();\r
 378 }\r
 379 /*-----------------------------------------------------------*/\r
 380 \r
 381 uint32_t ulPortGetIPL( void )\r
 382 {\r
 383         __asm volatile\r
 384         (\r
 385                 "MVFC   PSW, R1                 \n"     \\r
 386                 "SHLR   #24, R1                 \n"     \\r
 387                 "RTS                                      "\r
 388         );\r
 389 \r
 390         /* This will never get executed, but keeps the compiler from complaining. */\r
 391         return 0;\r
 392 }\r
 393 /*-----------------------------------------------------------*/\r
 394 \r
 395 void vPortSetIPL( uint32_t ulNewIPL )\r
 396 {\r
 397         __asm volatile\r
 398         (\r
 399                 "PUSH   R5                              \n" \\r
 400                 "MVFC   PSW, R5                 \n"     \\r
 401                 "SHLL   #24, R1                 \n" \\r
 402                 "AND    #-0F000001H, R5 \n" \\r
 403                 "OR             R1, R5                  \n" \\r
 404                 "MVTC   R5, PSW                 \n" \\r
 405                 "POP    R5                              \n" \\r
 406                 "RTS                                      "\r
 407          );\r
 408 }\r