git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/RX600v2/port.c

   1 /*\r
   2     FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     This file is part of the FreeRTOS distribution.\r
   8 \r
   9     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  10     the terms of the GNU General Public License (version 2) as published by the\r
  11     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  12 \r
  13     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  14     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  15     >>!   obliged to provide the source code for proprietary components     !<<\r
  16     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  17 \r
  18     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  19     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  20     FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
  21     link: http://www.freertos.org/a00114.html\r
  22 \r
  23     1 tab == 4 spaces!\r
  24 \r
  25     ***************************************************************************\r
  26      *                                                                       *\r
  27      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  28      *    not run, what could be wrong?".  Have you defined configASSERT()?  *\r
  29      *                                                                       *\r
  30      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  31      *                                                                       *\r
  32     ***************************************************************************\r
  33 \r
  34     ***************************************************************************\r
  35      *                                                                       *\r
  36      *    FreeRTOS provides completely free yet professionally developed,    *\r
  37      *    robust, strictly quality controlled, supported, and cross          *\r
  38      *    platform software that is more than just the market leader, it     *\r
  39      *    is the industry's de facto standard.                               *\r
  40      *                                                                       *\r
  41      *    Help yourself get started quickly while simultaneously helping     *\r
  42      *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r
  43      *    tutorial book, reference manual, or both:                          *\r
  44      *    http://www.FreeRTOS.org/Documentation                              *\r
  45      *                                                                       *\r
  46     ***************************************************************************\r
  47 \r
  48     ***************************************************************************\r
  49      *                                                                       *\r
  50      *   Investing in training allows your team to be as productive as       *\r
  51      *   possible as early as possible, lowering your overall development    *\r
  52      *   cost, and enabling you to bring a more robust product to market     *\r
  53      *   earlier than would otherwise be possible.  Richard Barry is both    *\r
  54      *   the architect and key author of FreeRTOS, and so also the world's   *\r
  55      *   leading authority on what is the world's most popular real time     *\r
  56      *   kernel for deeply embedded MCU designs.  Obtaining your training    *\r
  57      *   from Richard ensures your team will gain directly from his in-depth *\r
  58      *   product knowledge and years of usage experience.  Contact Real Time *\r
  59      *   Engineers Ltd to enquire about the FreeRTOS Masterclass, presented  *\r
  60      *   by Richard Barry:  http://www.FreeRTOS.org/contact\r
  61      *                                                                       *\r
  62     ***************************************************************************\r
  63 \r
  64     ***************************************************************************\r
  65      *                                                                       *\r
  66      *    You are receiving this top quality software for free.  Please play *\r
  67      *    fair and reciprocate by reporting any suspected issues and         *\r
  68      *    participating in the community forum:                              *\r
  69      *    http://www.FreeRTOS.org/support                                    *\r
  70      *                                                                       *\r
  71      *    Thank you!                                                         *\r
  72      *                                                                       *\r
  73     ***************************************************************************\r
  74 \r
  75     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  76     license and Real Time Engineers Ltd. contact details.\r
  77 \r
  78     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  79     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  80     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  81 \r
  82     http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
  83     Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
  84 \r
  85     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  86     Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  87     licenses offer ticketed support, indemnification and commercial middleware.\r
  88 \r
  89     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  90     engineered and independently SIL3 certified version for use in safety and\r
  91     mission critical applications that require provable dependability.\r
  92 \r
  93     1 tab == 4 spaces!\r
  94 */\r
  95 \r
  96 /*-----------------------------------------------------------\r
  97  * Implementation of functions defined in portable.h for the SH2A port.\r
  98  *----------------------------------------------------------*/\r
  99 \r
 100 /* Scheduler includes. */\r
 101 #include "FreeRTOS.h"\r
 102 #include "task.h"\r
 103 \r
 104 /* Library includes. */\r
 105 #include "string.h"\r
 106 \r
 107 /* Hardware specifics. */\r
 108 #include "iodefine.h"\r
 109 \r
 110 /*-----------------------------------------------------------*/\r
 111 \r
 112 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore\r
 113 PSW is set with U and I set, and PM and IPL clear. */\r
 114 #define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )\r
 115 #define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )\r
 116 \r
 117 /* These macros allow a critical section to be added around the call to\r
 118 xTaskIncrementTick(), which is only ever called from interrupts at the kernel\r
 119 priority - ie a known priority.  Therefore these local macros are a slight\r
 120 optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,\r
 121 which would require the old IPL to be read first and stored in a local variable. */\r
 122 #define portMASK_INTERRUPTS_FROM_KERNEL_ISR()   __asm volatile ( "MVTIPL        %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )\r
 123 #define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR()         __asm volatile ( "MVTIPL        %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )\r
 124 \r
 125 /*-----------------------------------------------------------*/\r
 126 \r
 127 /*\r
 128  * Function to start the first task executing - written in asm code as direct\r
 129  * access to registers is required.\r
 130  */\r
 131 static void prvStartFirstTask( void ) __attribute__((naked));\r
 132 \r
 133 /*\r
 134  * Software interrupt handler.  Performs the actual context switch (saving and\r
 135  * restoring of registers).  Written in asm code as direct register access is\r
 136  * required.\r
 137  */\r
 138 void vSoftwareInterruptISR( void ) __attribute__((naked));\r
 139 \r
 140 /*\r
 141  * The tick interrupt handler.\r
 142  */\r
 143 void vTickISR( void ) __attribute__((interrupt));\r
 144 \r
 145 /*-----------------------------------------------------------*/\r
 146 \r
 147 extern void *pxCurrentTCB;\r
 148 \r
 149 /*-----------------------------------------------------------*/\r
 150 \r
 151 /*\r
 152  * See header file for description.\r
 153  */\r
 154 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
 155 {\r
 156         /* R0 is not included as it is the stack pointer. */\r
 157 \r
 158         *pxTopOfStack = 0x00;\r
 159         pxTopOfStack--;\r
 160         *pxTopOfStack = portINITIAL_PSW;\r
 161         pxTopOfStack--;\r
 162         *pxTopOfStack = ( StackType_t ) pxCode;\r
 163 \r
 164         /* When debugging it can be useful if every register is set to a known\r
 165         value.  Otherwise code space can be saved by just setting the registers\r
 166         that need to be set. */\r
 167         #ifdef USE_FULL_REGISTER_INITIALISATION\r
 168         {\r
 169                 pxTopOfStack--;\r
 170                 *pxTopOfStack = 0xffffffff;     /* r15. */\r
 171                 pxTopOfStack--;\r
 172                 *pxTopOfStack = 0xeeeeeeee;\r
 173                 pxTopOfStack--;\r
 174                 *pxTopOfStack = 0xdddddddd;\r
 175                 pxTopOfStack--;\r
 176                 *pxTopOfStack = 0xcccccccc;\r
 177                 pxTopOfStack--;\r
 178                 *pxTopOfStack = 0xbbbbbbbb;\r
 179                 pxTopOfStack--;\r
 180                 *pxTopOfStack = 0xaaaaaaaa;\r
 181                 pxTopOfStack--;\r
 182                 *pxTopOfStack = 0x99999999;\r
 183                 pxTopOfStack--;\r
 184                 *pxTopOfStack = 0x88888888;\r
 185                 pxTopOfStack--;\r
 186                 *pxTopOfStack = 0x77777777;\r
 187                 pxTopOfStack--;\r
 188                 *pxTopOfStack = 0x66666666;\r
 189                 pxTopOfStack--;\r
 190                 *pxTopOfStack = 0x55555555;\r
 191                 pxTopOfStack--;\r
 192                 *pxTopOfStack = 0x44444444;\r
 193                 pxTopOfStack--;\r
 194                 *pxTopOfStack = 0x33333333;\r
 195                 pxTopOfStack--;\r
 196                 *pxTopOfStack = 0x22222222;\r
 197                 pxTopOfStack--;\r
 198         }\r
 199         #else\r
 200         {\r
 201                 pxTopOfStack -= 15;\r
 202         }\r
 203         #endif\r
 204 \r
 205         *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */\r
 206         pxTopOfStack--;\r
 207         *pxTopOfStack = portINITIAL_FPSW;\r
 208         pxTopOfStack--;\r
 209         *pxTopOfStack = 0x11111111; /* Accumulator 0. */\r
 210         pxTopOfStack--;\r
 211         *pxTopOfStack = 0x22222222; /* Accumulator 0. */\r
 212         pxTopOfStack--;\r
 213         *pxTopOfStack = 0x33333333; /* Accumulator 0. */\r
 214         pxTopOfStack--;\r
 215         *pxTopOfStack = 0x44444444; /* Accumulator 1. */\r
 216         pxTopOfStack--;\r
 217         *pxTopOfStack = 0x55555555; /* Accumulator 1. */\r
 218         pxTopOfStack--;\r
 219         *pxTopOfStack = 0x66666666; /* Accumulator 1. */\r
 220 \r
 221         return pxTopOfStack;\r
 222 }\r
 223 /*-----------------------------------------------------------*/\r
 224 \r
 225 BaseType_t xPortStartScheduler( void )\r
 226 {\r
 227 extern void vApplicationSetupTimerInterrupt( void );\r
 228 \r
 229         /* Use pxCurrentTCB just so it does not get optimised away. */\r
 230         if( pxCurrentTCB != NULL )\r
 231         {\r
 232                 /* Call an application function to set up the timer that will generate the\r
 233                 tick interrupt.  This way the application can decide which peripheral to\r
 234                 use.  A demo application is provided to show a suitable example. */\r
 235                 vApplicationSetupTimerInterrupt();\r
 236 \r
 237                 /* Enable the software interrupt. */\r
 238                 _IEN( _ICU_SWINT ) = 1;\r
 239 \r
 240                 /* Ensure the software interrupt is clear. */\r
 241                 _IR( _ICU_SWINT ) = 0;\r
 242 \r
 243                 /* Ensure the software interrupt is set to the kernel priority. */\r
 244                 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;\r
 245 \r
 246                 /* Start the first task. */\r
 247                 prvStartFirstTask();\r
 248         }\r
 249 \r
 250         /* Should not get here. */\r
 251         return pdFAIL;\r
 252 }\r
 253 /*-----------------------------------------------------------*/\r
 254 \r
 255 void vPortEndScheduler( void )\r
 256 {\r
 257         /* Not implemented in ports where there is nothing to return to.\r
 258         Artificially force an assert. */\r
 259         configASSERT( pxCurrentTCB == NULL );\r
 260 }\r
 261 /*-----------------------------------------------------------*/\r
 262 \r
 263 static void prvStartFirstTask( void )\r
 264 {\r
 265         __asm volatile\r
 266         (\r
 267                 /* When starting the scheduler there is nothing that needs moving to the\r
 268                 interrupt stack because the function is not called from an interrupt.\r
 269                 Just ensure the current stack is the user stack. */\r
 270                 "SETPSW         U                                               \n" \\r
 271 \r
 272                 /* Obtain the location of the stack associated with which ever task\r
 273                 pxCurrentTCB is currently pointing to. */\r
 274                 "MOV.L          #_pxCurrentTCB, R15             \n" \\r
 275                 "MOV.L          [R15], R15                              \n" \\r
 276                 "MOV.L          [R15], R0                               \n" \\r
 277 \r
 278                 /* Restore the registers from the stack of the task pointed to by\r
 279                 pxCurrentTCB. */\r
 280             "POP                R15                                             \n" \\r
 281 \r
 282                 /* Accumulator low 32 bits. */\r
 283             "MVTACLO    R15, A0                                 \n" \\r
 284             "POP                R15                                             \n" \\r
 285 \r
 286             /* Accumulator high 32 bits. */\r
 287             "MVTACHI    R15, A0                                 \n" \\r
 288             "POP                R15                                             \n" \\r
 289 \r
 290             /* Accumulator guard. */\r
 291             "MVTACGU    R15, A0                                 \n" \\r
 292             "POP                R15                                             \n" \\r
 293 \r
 294             /* Accumulator low 32 bits. */\r
 295             "MVTACLO    R15, A1                                 \n" \\r
 296             "POP                R15                                             \n" \\r
 297 \r
 298             /* Accumulator high 32 bits. */\r
 299             "MVTACHI    R15, A1                                 \n" \\r
 300             "POP                R15                                             \n" \\r
 301 \r
 302             /* Accumulator guard. */\r
 303             "MVTACGU    R15, A1                                 \n" \\r
 304             "POP                R15                                             \n" \\r
 305 \r
 306                 /* Floating point status word. */\r
 307             "MVTC               R15, FPSW                               \n" \\r
 308 \r
 309                 /* R1 to R15 - R0 is not included as it is the SP. */\r
 310             "POPM               R1-R15                                  \n" \\r
 311 \r
 312                 /* This pops the remaining registers. */\r
 313             "RTE                                                                \n" \\r
 314             "NOP                                                                \n" \\r
 315             "NOP                                                                \n"\r
 316         );\r
 317 }\r
 318 /*-----------------------------------------------------------*/\r
 319 \r
 320 void vSoftwareInterruptISR( void )\r
 321 {\r
 322         __asm volatile\r
 323         (\r
 324                 /* Re-enable interrupts. */\r
 325                 "SETPSW         I                                                       \n" \\r
 326 \r
 327                 /* Move the data that was automatically pushed onto the interrupt stack when\r
 328                 the interrupt occurred from the interrupt stack to the user stack.\r
 329 \r
 330                 R15 is saved before it is clobbered. */\r
 331                 "PUSH.L         R15                                                     \n" \\r
 332 \r
 333                 /* Read the user stack pointer. */\r
 334                 "MVFC           USP, R15                                        \n" \\r
 335 \r
 336                 /* Move the address down to the data being moved. */\r
 337                 "SUB            #12, R15                                        \n" \\r
 338                 "MVTC           R15, USP                                        \n" \\r
 339 \r
 340                 /* Copy the data across, R15, then PC, then PSW. */\r
 341                 "MOV.L          [ R0 ], [ R15 ]                         \n" \\r
 342                 "MOV.L          4[ R0 ], 4[ R15 ]                       \n" \\r
 343                 "MOV.L          8[ R0 ], 8[ R15 ]                       \n" \\r
 344 \r
 345                 /* Move the interrupt stack pointer to its new correct position. */\r
 346                 "ADD            #12, R0                                         \n" \\r
 347 \r
 348                 /* All the rest of the registers are saved directly to the user stack. */\r
 349                 "SETPSW         U                                                       \n" \\r
 350 \r
 351                 /* Save the rest of the general registers (R15 has been saved already). */\r
 352                 "PUSHM          R1-R14                                          \n" \\r
 353 \r
 354                 /* Save the FPSW and accumulator. */\r
 355                 "MVFC           FPSW, R15                                       \n" \\r
 356                 "PUSH.L         R15                                                     \n" \\r
 357                 "MVFACGU        #0, A1, R15                                     \n" \\r
 358                 "PUSH.L         R15                                                     \n" \\r
 359                 "MVFACHI        #0, A1, R15                                     \n" \\r
 360                 "PUSH.L         R15                                                     \n" \\r
 361                 /* Low order word. */\r
 362                 "MVFACLO        #0, A1, R15                                     \n" \\r
 363                 "PUSH.L         R15                                                     \n" \\r
 364                 "MVFACGU        #0, A0, R15                                     \n" \\r
 365                 "PUSH.L         R15                                                     \n" \\r
 366                 "MVFACHI        #0, A0, R15                                     \n" \\r
 367                 "PUSH.L         R15                                                     \n" \\r
 368                 /* Low order word. */\r
 369                 "MVFACLO        #0, A0, R15                                     \n" \\r
 370                 "PUSH.L         R15                                                     \n" \\r
 371 \r
 372                 /* Save the stack pointer to the TCB. */\r
 373                 "MOV.L          #_pxCurrentTCB, R15                     \n" \\r
 374                 "MOV.L          [ R15 ], R15                            \n" \\r
 375                 "MOV.L          R0, [ R15 ]                                     \n" \\r
 376 \r
 377                 /* Ensure the interrupt mask is set to the syscall priority while the kernel\r
 378                 structures are being accessed. */\r
 379                 "MVTIPL         %0                                                      \n" \\r
 380 \r
 381                 /* Select the next task to run. */\r
 382                 "BSR.A          _vTaskSwitchContext                     \n" \\r
 383 \r
 384                 /* Reset the interrupt mask as no more data structure access is required. */\r
 385                 "MVTIPL         %1                                                      \n" \\r
 386 \r
 387                 /* Load the stack pointer of the task that is now selected as the Running\r
 388                 state task from its TCB. */\r
 389                 "MOV.L          #_pxCurrentTCB,R15                      \n" \\r
 390                 "MOV.L          [ R15 ], R15                            \n" \\r
 391                 "MOV.L          [ R15 ], R0                                     \n" \\r
 392 \r
 393                 /* Restore the context of the new task.  The PSW (Program Status Word) and\r
 394                 PC will be popped by the RTE instruction. */\r
 395             "POP                R15                                                     \n" \\r
 396 \r
 397             /* Accumulator low 32 bits. */\r
 398             "MVTACLO    R15, A0                                         \n" \\r
 399             "POP                R15                                                     \n" \\r
 400 \r
 401             /* Accumulator high 32 bits. */\r
 402             "MVTACHI    R15, A0                                         \n" \\r
 403             "POP                R15                                                     \n" \\r
 404 \r
 405             /* Accumulator guard. */\r
 406             "MVTACGU    R15, A0                                         \n" \\r
 407             "POP                R15                                                     \n" \\r
 408 \r
 409             /* Accumulator low 32 bits. */\r
 410             "MVTACLO    R15, A1                                         \n" \\r
 411             "POP                R15                                                     \n" \\r
 412 \r
 413             /* Accumulator high 32 bits. */\r
 414             "MVTACHI    R15, A1                                         \n" \\r
 415             "POP                R15                                                     \n" \\r
 416 \r
 417             /* Accumulator guard. */\r
 418             "MVTACGU    R15, A1                                         \n" \\r
 419                 "POP            R15                                                     \n" \\r
 420                 "MVTC           R15, FPSW                                       \n" \\r
 421                 "POPM           R1-R15                                          \n" \\r
 422                 "RTE                                                                    \n" \\r
 423                 "NOP                                                                    \n" \\r
 424                 "NOP                                                                      "\r
 425                 :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)\r
 426         );\r
 427 }\r
 428 /*-----------------------------------------------------------*/\r
 429 \r
 430 void vTickISR( void )\r
 431 {\r
 432         /* Re-enabled interrupts. */\r
 433         __asm volatile( "SETPSW I" );\r
 434 \r
 435         /* Increment the tick, and perform any processing the new tick value\r
 436         necessitates.  Ensure IPL is at the max syscall value first. */\r
 437         portMASK_INTERRUPTS_FROM_KERNEL_ISR();\r
 438         {\r
 439                 if( xTaskIncrementTick() != pdFALSE )\r
 440                 {\r
 441                         taskYIELD();\r
 442                 }\r
 443         }\r
 444         portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();\r
 445 }\r
 446 /*-----------------------------------------------------------*/\r
 447 \r
 448 uint32_t ulPortGetIPL( void )\r
 449 {\r
 450         __asm volatile\r
 451         (\r
 452                 "MVFC   PSW, R1                 \n"     \\r
 453                 "SHLR   #24, R1                 \n"     \\r
 454                 "RTS                                      "\r
 455         );\r
 456 \r
 457         /* This will never get executed, but keeps the compiler from complaining. */\r
 458         return 0;\r
 459 }\r
 460 /*-----------------------------------------------------------*/\r
 461 \r
 462 void vPortSetIPL( uint32_t ulNewIPL )\r
 463 {\r
 464         __asm volatile\r
 465         (\r
 466                 "PUSH   R5                              \n" \\r
 467                 "MVFC   PSW, R5                 \n"     \\r
 468                 "SHLL   #24, R1                 \n" \\r
 469                 "AND    #-0F000001H, R5 \n" \\r
 470                 "OR             R1, R5                  \n" \\r
 471                 "MVTC   R5, PSW                 \n" \\r
 472                 "POP    R5                              \n" \\r
 473                 "RTS                                      "\r
 474          );\r
 475 }\r