2 * FreeRTOS Kernel V10.3.0
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3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /* Standard includes. */
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32 /* TriCore specific includes. */
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34 #include <machine/intrinsics.h>
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35 #include <machine/cint.h>
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36 #include <machine/wdtcon.h>
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38 /* Kernel includes. */
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39 #include "FreeRTOS.h"
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43 #if configCHECK_FOR_STACK_OVERFLOW > 0
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44 #error "Stack checking cannot be used with this port, as, unlike most ports, the pxTopOfStack member of the TCB is consumed CSA. CSA starvation, loosely equivalent to stack overflow, will result in a trap exception."
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45 /* The stack pointer is accessible using portCSA_TO_ADDRESS( portCSA_TO_ADDRESS( pxCurrentTCB->pxTopOfStack )[ 0 ] )[ 2 ]; */
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46 #endif /* configCHECK_FOR_STACK_OVERFLOW */
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49 /*-----------------------------------------------------------*/
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51 /* System register Definitions. */
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52 #define portSYSTEM_PROGRAM_STATUS_WORD ( 0x000008FFUL ) /* Supervisor Mode, MPU Register Set 0 and Call Depth Counting disabled. */
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53 #define portINITIAL_PRIVILEGED_PROGRAM_STATUS_WORD ( 0x000014FFUL ) /* IO Level 1, MPU Register Set 1 and Call Depth Counting disabled. */
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54 #define portINITIAL_UNPRIVILEGED_PROGRAM_STATUS_WORD ( 0x000010FFUL ) /* IO Level 0, MPU Register Set 1 and Call Depth Counting disabled. */
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55 #define portINITIAL_PCXI_UPPER_CONTEXT_WORD ( 0x00C00000UL ) /* The lower 20 bits identify the CSA address. */
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56 #define portINITIAL_SYSCON ( 0x00000000UL ) /* MPU Disable. */
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58 /* CSA manipulation macros. */
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59 #define portCSA_FCX_MASK ( 0x000FFFFFUL )
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61 /* OS Interrupt and Trap mechanisms. */
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62 #define portRESTORE_PSW_MASK ( ~( 0x000000FFUL ) )
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63 #define portSYSCALL_TRAP ( 6 )
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65 /* Each CSA contains 16 words of data. */
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66 #define portNUM_WORDS_IN_CSA ( 16 )
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68 /* The interrupt enable bit in the PCP_SRC register. */
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69 #define portENABLE_CPU_INTERRUPT ( 1U << 12U )
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70 /*-----------------------------------------------------------*/
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73 * Perform any hardware configuration necessary to generate the tick interrupt.
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75 static void prvSystemTickHandler( int ) __attribute__((longcall));
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76 static void prvSetupTimerInterrupt( void );
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79 * Trap handler for yields.
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81 static void prvTrapYield( int iTrapIdentification );
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84 * Priority 1 interrupt handler for yields pended from an interrupt.
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86 static void prvInterruptYield( int iTrapIdentification );
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88 /*-----------------------------------------------------------*/
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90 /* This reference is required by the save/restore context macros. */
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91 extern volatile uint32_t *pxCurrentTCB;
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93 /* Precalculate the compare match value at compile time. */
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94 static const uint32_t ulCompareMatchValue = ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ );
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96 /*-----------------------------------------------------------*/
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98 StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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100 uint32_t *pulUpperCSA = NULL;
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101 uint32_t *pulLowerCSA = NULL;
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103 /* 16 Address Registers (4 Address registers are global), 16 Data
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104 Registers, and 3 System Registers.
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106 There are 3 registers that track the CSAs.
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107 FCX points to the head of globally free set of CSAs.
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108 PCX for the task needs to point to Lower->Upper->NULL arrangement.
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109 LCX points to the last free CSA so that corrective action can be taken.
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111 Need two CSAs to store the context of a task.
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112 The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL.
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113 The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext.
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114 The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR.
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115 The Lower Context points to the Upper Context ready for the return from the interrupt handler.
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117 The Real stack pointer for the task is stored in the A10 which is restored
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118 with the upper context. */
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120 /* Have to disable interrupts here because the CSAs are going to be
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122 portENTER_CRITICAL();
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124 /* DSync to ensure that buffering is not a problem. */
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127 /* Consume two free CSAs. */
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128 pulLowerCSA = portCSA_TO_ADDRESS( __MFCR( $FCX ) );
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129 if( NULL != pulLowerCSA )
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131 /* The Lower Links to the Upper. */
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132 pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] );
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135 /* Check that we have successfully reserved two CSAs. */
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136 if( ( NULL != pulLowerCSA ) && ( NULL != pulUpperCSA ) )
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138 /* Remove the two consumed CSAs from the free CSA list. */
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141 _mtcr( $FCX, pulUpperCSA[ 0 ] );
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147 /* Simply trigger a context list depletion trap. */
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151 portEXIT_CRITICAL();
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153 /* Clear the upper CSA. */
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154 memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
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156 /* Upper Context. */
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157 pulUpperCSA[ 2 ] = ( uint32_t )pxTopOfStack; /* A10; Stack Return aka Stack Pointer */
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158 pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD; /* PSW */
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160 /* Clear the lower CSA. */
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161 memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
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163 /* Lower Context. */
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164 pulLowerCSA[ 8 ] = ( uint32_t ) pvParameters; /* A4; Address Type Parameter Register */
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165 pulLowerCSA[ 1 ] = ( uint32_t ) pxCode; /* A11; Return Address aka RA */
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167 /* PCXI pointing to the Upper context. */
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168 pulLowerCSA[ 0 ] = ( portINITIAL_PCXI_UPPER_CONTEXT_WORD | ( uint32_t ) portADDRESS_TO_CSA( pulUpperCSA ) );
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170 /* Save the link to the CSA in the top of stack. */
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171 pxTopOfStack = (uint32_t * ) portADDRESS_TO_CSA( pulLowerCSA );
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173 /* DSync to ensure that buffering is not a problem. */
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176 return pxTopOfStack;
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178 /*-----------------------------------------------------------*/
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180 int32_t xPortStartScheduler( void )
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182 extern void vTrapInstallHandlers( void );
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183 uint32_t ulMFCR = 0UL;
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184 uint32_t *pulUpperCSA = NULL;
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185 uint32_t *pulLowerCSA = NULL;
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187 /* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable
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188 when this function is called. */
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190 /* Set-up the timer interrupt. */
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191 prvSetupTimerInterrupt();
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193 /* Install the Trap Handlers. */
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194 vTrapInstallHandlers();
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196 /* Install the Syscall Handler for yield calls. */
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197 if( 0 == _install_trap_handler( portSYSCALL_TRAP, prvTrapYield ) )
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199 /* Failed to install the yield handler, force an assert. */
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200 configASSERT( ( ( volatile void * ) NULL ) );
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203 /* Enable then install the priority 1 interrupt for pending context
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204 switches from an ISR. See mod_SRC in the TriCore manual. */
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205 CPU_SRC0.reg = ( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY );
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206 if( 0 == _install_int_handler( configKERNEL_YIELD_PRIORITY, prvInterruptYield, 0 ) )
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208 /* Failed to install the yield handler, force an assert. */
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209 configASSERT( ( ( volatile void * ) NULL ) );
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214 /* Load the initial SYSCON. */
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215 _mtcr( $SYSCON, portINITIAL_SYSCON );
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218 /* ENDINIT has already been applied in the 'cstart.c' code. */
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220 /* Clear the PSW.CDC to enable the use of an RFE without it generating an
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221 exception because this code is not genuinely in an exception. */
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222 ulMFCR = __MFCR( $PSW );
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223 ulMFCR &= portRESTORE_PSW_MASK;
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225 _mtcr( $PSW, ulMFCR );
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228 /* Finally, perform the equivalent of a portRESTORE_CONTEXT() */
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229 pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) );
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230 pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[0] );
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232 _mtcr( $PCXI, *pxCurrentTCB );
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238 /* Return to the first task selected to execute. */
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239 __asm volatile( "rfe" );
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241 /* Will not get here. */
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244 /*-----------------------------------------------------------*/
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246 static void prvSetupTimerInterrupt( void )
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248 /* Set-up the clock divider. */
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251 /* Wait until access to Endint protected register is enabled. */
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252 while( 0 != ( WDT_CON0.reg & 0x1UL ) );
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254 /* RMC == 1 so STM Clock == FPI */
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255 STM_CLC.reg = ( 1UL << 8 );
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259 /* Determine how many bits are used without changing other bits in the CMCON register. */
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260 STM_CMCON.reg &= ~( 0x1fUL );
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261 STM_CMCON.reg |= ( 0x1fUL - __CLZ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) );
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263 /* Take into account the current time so a tick doesn't happen immediately. */
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264 STM_CMP0.reg = ulCompareMatchValue + STM_TIM0.reg;
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266 if( 0 != _install_int_handler( configKERNEL_INTERRUPT_PRIORITY, prvSystemTickHandler, 0 ) )
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268 /* Set-up the interrupt. */
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269 STM_SRC0.reg = ( configKERNEL_INTERRUPT_PRIORITY | 0x00005000UL );
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271 /* Enable the Interrupt. */
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272 STM_ISRR.reg &= ~( 0x03UL );
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273 STM_ISRR.reg |= 0x1UL;
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274 STM_ISRR.reg &= ~( 0x07UL );
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275 STM_ICR.reg |= 0x1UL;
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279 /* Failed to install the Tick Interrupt. */
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280 configASSERT( ( ( volatile void * ) NULL ) );
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283 /*-----------------------------------------------------------*/
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285 static void prvSystemTickHandler( int iArg )
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287 uint32_t ulSavedInterruptMask;
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288 uint32_t *pxUpperCSA = NULL;
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289 uint32_t xUpperCSA = 0UL;
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290 extern volatile uint32_t *pxCurrentTCB;
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291 int32_t lYieldRequired;
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293 /* Just to avoid compiler warnings about unused parameters. */
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296 /* Clear the interrupt source. */
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297 STM_ISRR.reg = 1UL;
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299 /* Reload the Compare Match register for X ticks into the future.
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301 If critical section or interrupt nesting budgets are exceeded, then
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302 it is possible that the calculated next compare match value is in the
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303 past. If this occurs (unlikely), it is possible that the resulting
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304 time slippage will exceed a single tick period. Any adverse effect of
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305 this is time bounded by the fact that only the first n bits of the 56 bit
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306 STM timer are being used for a compare match, so another compare match
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307 will occur after an overflow in just those n bits (not the entire 56 bits).
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308 As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz,
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309 a missed tick could result in the next tick interrupt occurring within a
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310 time that is 1.7 times the desired period. The fact that this is greater
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311 than a single tick period is an effect of using a timer that cannot be
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312 automatically reset, in hardware, by the occurrence of a tick interrupt.
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313 Changing the tick source to a timer that has an automatic reset on compare
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314 match (such as a GPTA timer) will reduce the maximum possible additional
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315 period to exactly 1 times the desired period. */
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316 STM_CMP0.reg += ulCompareMatchValue;
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318 /* Kernel API calls require Critical Sections. */
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319 ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
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321 /* Increment the Tick. */
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322 lYieldRequired = xTaskIncrementTick();
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324 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
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326 if( lYieldRequired != pdFALSE )
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328 /* Save the context of a task.
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329 The upper context is automatically saved when entering a trap or interrupt.
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330 Need to save the lower context as well and copy the PCXI CSA ID into
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331 pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
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334 Call vTaskSwitchContext to select the next task, note that this changes the
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335 value of pxCurrentTCB so that it needs to be reloaded.
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337 Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
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338 that has just been switched in.
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340 Load the context of the task.
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341 Need to restore the lower context by loading the CSA from
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342 pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
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343 In the Interrupt handler post-amble, RSLCX will restore the lower context
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344 of the task. RFE will restore the upper context of the task, jump to the
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345 return address and restore the previous state of interrupts being
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346 enabled/disabled. */
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349 xUpperCSA = __MFCR( $PCXI );
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350 pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
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351 *pxCurrentTCB = pxUpperCSA[ 0 ];
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352 vTaskSwitchContext();
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353 pxUpperCSA[ 0 ] = *pxCurrentTCB;
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354 CPU_SRC0.bits.SETR = 0;
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358 /*-----------------------------------------------------------*/
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361 * When a task is deleted, it is yielded permanently until the IDLE task
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362 * has an opportunity to reclaim the memory that that task was using.
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363 * Typically, the memory used by a task is the TCB and Stack but in the
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364 * TriCore this includes the CSAs that were consumed as part of the Call
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365 * Stack. These CSAs can only be returned to the Globally Free Pool when
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366 * they are not part of the current Call Stack, hence, delaying the
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367 * reclamation until the IDLE task is freeing the task's other resources.
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368 * This function uses the head of the linked list of CSAs (from when the
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369 * task yielded for the last time) and finds the tail (the very bottom of
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370 * the call stack) and inserts this list at the head of the Free list,
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371 * attaching the existing Free List to the tail of the reclaimed call stack.
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373 * NOTE: the IDLE task needs processing time to complete this function
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374 * and in heavily loaded systems, the Free CSAs may be consumed faster
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375 * than they can be freed assuming that tasks are being spawned and
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376 * deleted frequently.
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378 void vPortReclaimCSA( uint32_t *pxTCB )
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380 uint32_t pxHeadCSA, pxTailCSA, pxFreeCSA;
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381 uint32_t *pulNextCSA;
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383 /* A pointer to the first CSA in the list of CSAs consumed by the task is
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384 stored in the first element of the tasks TCB structure (where the stack
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385 pointer would be on a traditional stack based architecture). */
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386 pxHeadCSA = ( *pxTCB ) & portCSA_FCX_MASK;
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388 /* Mask off everything in the CSA link field other than the address. If
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389 the address is NULL, then the CSA is not linking anywhere and there is
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391 pxTailCSA = pxHeadCSA;
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393 /* Convert the link value to contain just a raw address and store this
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394 in a local variable. */
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395 pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
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397 /* Iterate over the CSAs that were consumed as part of the task. The
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398 first field in the CSA is the pointer to then next CSA. Mask off
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399 everything in the pointer to the next CSA, other than the link address.
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400 If this is NULL, then the CSA currently being pointed to is the last in
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402 while( 0UL != ( pulNextCSA[ 0 ] & portCSA_FCX_MASK ) )
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404 /* Clear all bits of the pointer to the next in the chain, other
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405 than the address bits themselves. */
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406 pulNextCSA[ 0 ] = pulNextCSA[ 0 ] & portCSA_FCX_MASK;
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408 /* Move the pointer to point to the next CSA in the list. */
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409 pxTailCSA = pulNextCSA[ 0 ];
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411 /* Update the local pointer to the CSA. */
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412 pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
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417 /* Look up the current free CSA head. */
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419 pxFreeCSA = __MFCR( $FCX );
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421 /* Join the current Free onto the Tail of what is being reclaimed. */
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422 portCSA_TO_ADDRESS( pxTailCSA )[ 0 ] = pxFreeCSA;
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424 /* Move the head of the reclaimed into the Free. */
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426 _mtcr( $FCX, pxHeadCSA );
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431 /*-----------------------------------------------------------*/
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433 void vPortEndScheduler( void )
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435 /* Nothing to do. Unlikely to want to end. */
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437 /*-----------------------------------------------------------*/
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439 static void prvTrapYield( int iTrapIdentification )
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441 uint32_t *pxUpperCSA = NULL;
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442 uint32_t xUpperCSA = 0UL;
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443 extern volatile uint32_t *pxCurrentTCB;
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445 switch( iTrapIdentification )
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447 case portSYSCALL_TASK_YIELD:
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448 /* Save the context of a task.
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449 The upper context is automatically saved when entering a trap or interrupt.
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450 Need to save the lower context as well and copy the PCXI CSA ID into
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451 pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
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454 Call vTaskSwitchContext to select the next task, note that this changes the
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455 value of pxCurrentTCB so that it needs to be reloaded.
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457 Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
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458 that has just been switched in.
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460 Load the context of the task.
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461 Need to restore the lower context by loading the CSA from
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462 pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
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463 In the Interrupt handler post-amble, RSLCX will restore the lower context
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464 of the task. RFE will restore the upper context of the task, jump to the
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465 return address and restore the previous state of interrupts being
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466 enabled/disabled. */
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469 xUpperCSA = __MFCR( $PCXI );
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470 pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
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471 *pxCurrentTCB = pxUpperCSA[ 0 ];
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472 vTaskSwitchContext();
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473 pxUpperCSA[ 0 ] = *pxCurrentTCB;
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474 CPU_SRC0.bits.SETR = 0;
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479 /* Unimplemented trap called. */
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480 configASSERT( ( ( volatile void * ) NULL ) );
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484 /*-----------------------------------------------------------*/
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486 static void prvInterruptYield( int iId )
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488 uint32_t *pxUpperCSA = NULL;
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489 uint32_t xUpperCSA = 0UL;
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490 extern volatile uint32_t *pxCurrentTCB;
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492 /* Just to remove compiler warnings. */
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495 /* Save the context of a task.
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496 The upper context is automatically saved when entering a trap or interrupt.
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497 Need to save the lower context as well and copy the PCXI CSA ID into
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498 pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
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501 Call vTaskSwitchContext to select the next task, note that this changes the
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502 value of pxCurrentTCB so that it needs to be reloaded.
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504 Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
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505 that has just been switched in.
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507 Load the context of the task.
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508 Need to restore the lower context by loading the CSA from
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509 pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
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510 In the Interrupt handler post-amble, RSLCX will restore the lower context
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511 of the task. RFE will restore the upper context of the task, jump to the
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512 return address and restore the previous state of interrupts being
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513 enabled/disabled. */
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516 xUpperCSA = __MFCR( $PCXI );
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517 pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
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518 *pxCurrentTCB = pxUpperCSA[ 0 ];
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519 vTaskSwitchContext();
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520 pxUpperCSA[ 0 ] = *pxCurrentTCB;
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521 CPU_SRC0.bits.SETR = 0;
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524 /*-----------------------------------------------------------*/
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526 uint32_t uxPortSetInterruptMaskFromISR( void )
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528 uint32_t uxReturn = 0UL;
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531 uxReturn = __MFCR( $ICR );
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532 _mtcr( $ICR, ( ( uxReturn & ~portCCPN_MASK ) | configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
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536 /* Return just the interrupt mask bits. */
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537 return ( uxReturn & portCCPN_MASK );
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539 /*-----------------------------------------------------------*/
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