2 FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS provides completely free yet professionally developed, *
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10 * robust, strictly quality controlled, supported, and cross *
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11 * platform software that has become a de facto standard. *
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13 * Help yourself get started quickly and support the FreeRTOS *
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14 * project by purchasing a FreeRTOS tutorial book, reference *
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15 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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19 ***************************************************************************
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21 This file is part of the FreeRTOS distribution.
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23 FreeRTOS is free software; you can redistribute it and/or modify it under
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24 the terms of the GNU General Public License (version 2) as published by the
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25 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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27 >>! NOTE: The modification to the GPL is included to allow you to distribute
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28 >>! a combined work that includes FreeRTOS without being obliged to provide
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29 >>! the source code for proprietary components outside of the FreeRTOS
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32 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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33 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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34 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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35 link: http://www.freertos.org/a00114.html
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39 ***************************************************************************
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41 * Having a problem? Start by reading the FAQ "My application does *
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42 * not run, what could be wrong?" *
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44 * http://www.FreeRTOS.org/FAQHelp.html *
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46 ***************************************************************************
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48 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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49 license and Real Time Engineers Ltd. contact details.
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51 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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52 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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53 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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55 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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56 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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57 licenses offer ticketed support, indemnification and middleware.
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59 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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60 engineered and independently SIL3 certified version for use in safety and
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61 mission critical applications that require provable dependability.
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66 /* Standard includes. */
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70 /* TriCore specific includes. */
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72 #include <machine/intrinsics.h>
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73 #include <machine/cint.h>
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74 #include <machine/wdtcon.h>
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76 /* Kernel includes. */
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77 #include "FreeRTOS.h"
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81 #if configCHECK_FOR_STACK_OVERFLOW > 0
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82 #error "Stack checking cannot be used with this port, as, unlike most ports, the pxTopOfStack member of the TCB is consumed CSA. CSA starvation, loosely equivalent to stack overflow, will result in a trap exception."
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83 /* The stack pointer is accessible using portCSA_TO_ADDRESS( portCSA_TO_ADDRESS( pxCurrentTCB->pxTopOfStack )[ 0 ] )[ 2 ]; */
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84 #endif /* configCHECK_FOR_STACK_OVERFLOW */
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87 /*-----------------------------------------------------------*/
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89 /* System register Definitions. */
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90 #define portSYSTEM_PROGRAM_STATUS_WORD ( 0x000008FFUL ) /* Supervisor Mode, MPU Register Set 0 and Call Depth Counting disabled. */
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91 #define portINITIAL_PRIVILEGED_PROGRAM_STATUS_WORD ( 0x000014FFUL ) /* IO Level 1, MPU Register Set 1 and Call Depth Counting disabled. */
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92 #define portINITIAL_UNPRIVILEGED_PROGRAM_STATUS_WORD ( 0x000010FFUL ) /* IO Level 0, MPU Register Set 1 and Call Depth Counting disabled. */
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93 #define portINITIAL_PCXI_UPPER_CONTEXT_WORD ( 0x00C00000UL ) /* The lower 20 bits identify the CSA address. */
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94 #define portINITIAL_SYSCON ( 0x00000000UL ) /* MPU Disable. */
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96 /* CSA manipulation macros. */
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97 #define portCSA_FCX_MASK ( 0x000FFFFFUL )
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99 /* OS Interrupt and Trap mechanisms. */
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100 #define portRESTORE_PSW_MASK ( ~( 0x000000FFUL ) )
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101 #define portSYSCALL_TRAP ( 6 )
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103 /* Each CSA contains 16 words of data. */
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104 #define portNUM_WORDS_IN_CSA ( 16 )
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106 /* The interrupt enable bit in the PCP_SRC register. */
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107 #define portENABLE_CPU_INTERRUPT ( 1U << 12U )
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108 /*-----------------------------------------------------------*/
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111 * Perform any hardware configuration necessary to generate the tick interrupt.
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113 static void prvSystemTickHandler( int ) __attribute__((longcall));
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114 static void prvSetupTimerInterrupt( void );
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117 * Trap handler for yields.
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119 static void prvTrapYield( int iTrapIdentification );
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122 * Priority 1 interrupt handler for yields pended from an interrupt.
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124 static void prvInterruptYield( int iTrapIdentification );
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126 /*-----------------------------------------------------------*/
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128 /* This reference is required by the save/restore context macros. */
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129 extern volatile unsigned long *pxCurrentTCB;
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131 /* Precalculate the compare match value at compile time. */
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132 static const unsigned long ulCompareMatchValue = ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ );
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134 /*-----------------------------------------------------------*/
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136 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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138 unsigned long *pulUpperCSA = NULL;
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139 unsigned long *pulLowerCSA = NULL;
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141 /* 16 Address Registers (4 Address registers are global), 16 Data
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142 Registers, and 3 System Registers.
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144 There are 3 registers that track the CSAs.
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145 FCX points to the head of globally free set of CSAs.
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146 PCX for the task needs to point to Lower->Upper->NULL arrangement.
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147 LCX points to the last free CSA so that corrective action can be taken.
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149 Need two CSAs to store the context of a task.
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150 The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL.
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151 The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext.
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152 The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR.
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153 The Lower Context points to the Upper Context ready for the return from the interrupt handler.
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155 The Real stack pointer for the task is stored in the A10 which is restored
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156 with the upper context. */
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158 /* Have to disable interrupts here because the CSAs are going to be
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160 portENTER_CRITICAL();
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162 /* DSync to ensure that buffering is not a problem. */
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165 /* Consume two free CSAs. */
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166 pulLowerCSA = portCSA_TO_ADDRESS( _mfcr( $FCX ) );
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167 if( NULL != pulLowerCSA )
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169 /* The Lower Links to the Upper. */
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170 pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] );
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173 /* Check that we have successfully reserved two CSAs. */
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174 if( ( NULL != pulLowerCSA ) && ( NULL != pulUpperCSA ) )
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176 /* Remove the two consumed CSAs from the free CSA list. */
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179 _mtcr( $FCX, pulUpperCSA[ 0 ] );
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185 /* Simply trigger a context list depletion trap. */
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189 portEXIT_CRITICAL();
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191 /* Clear the upper CSA. */
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192 memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( unsigned long ) );
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194 /* Upper Context. */
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195 pulUpperCSA[ 2 ] = ( unsigned long )pxTopOfStack; /* A10; Stack Return aka Stack Pointer */
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196 pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD; /* PSW */
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198 /* Clear the lower CSA. */
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199 memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( unsigned long ) );
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201 /* Lower Context. */
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202 pulLowerCSA[ 8 ] = ( unsigned long ) pvParameters; /* A4; Address Type Parameter Register */
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203 pulLowerCSA[ 1 ] = ( unsigned long ) pxCode; /* A11; Return Address aka RA */
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205 /* PCXI pointing to the Upper context. */
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206 pulLowerCSA[ 0 ] = ( portINITIAL_PCXI_UPPER_CONTEXT_WORD | ( unsigned long ) portADDRESS_TO_CSA( pulUpperCSA ) );
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208 /* Save the link to the CSA in the top of stack. */
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209 pxTopOfStack = (unsigned long * ) portADDRESS_TO_CSA( pulLowerCSA );
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211 /* DSync to ensure that buffering is not a problem. */
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214 return pxTopOfStack;
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216 /*-----------------------------------------------------------*/
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218 long xPortStartScheduler( void )
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220 extern void vTrapInstallHandlers( void );
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221 unsigned long ulMFCR = 0UL;
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222 unsigned long *pulUpperCSA = NULL;
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223 unsigned long *pulLowerCSA = NULL;
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225 /* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable
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226 when this function is called. */
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228 /* Set-up the timer interrupt. */
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229 prvSetupTimerInterrupt();
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231 /* Install the Trap Handlers. */
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232 vTrapInstallHandlers();
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234 /* Install the Syscall Handler for yield calls. */
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235 if( 0 == _install_trap_handler( portSYSCALL_TRAP, prvTrapYield ) )
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237 /* Failed to install the yield handler, force an assert. */
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238 configASSERT( ( ( volatile void * ) NULL ) );
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241 /* Enable then install the priority 1 interrupt for pending context
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242 switches from an ISR. See mod_SRC in the TriCore manual. */
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243 CPU_SRC0.reg = ( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY );
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244 if( 0 == _install_int_handler( configKERNEL_YIELD_PRIORITY, prvInterruptYield, 0 ) )
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246 /* Failed to install the yield handler, force an assert. */
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247 configASSERT( ( ( volatile void * ) NULL ) );
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252 /* Load the initial SYSCON. */
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253 _mtcr( $SYSCON, portINITIAL_SYSCON );
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256 /* ENDINIT has already been applied in the 'cstart.c' code. */
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258 /* Clear the PSW.CDC to enable the use of an RFE without it generating an
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259 exception because this code is not genuinely in an exception. */
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260 ulMFCR = _mfcr( $PSW );
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261 ulMFCR &= portRESTORE_PSW_MASK;
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263 _mtcr( $PSW, ulMFCR );
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266 /* Finally, perform the equivalent of a portRESTORE_CONTEXT() */
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267 pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) );
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268 pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[0] );
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270 _mtcr( $PCXI, *pxCurrentTCB );
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276 /* Return to the first task selected to execute. */
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277 __asm volatile( "rfe" );
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279 /* Will not get here. */
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282 /*-----------------------------------------------------------*/
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284 static void prvSetupTimerInterrupt( void )
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286 /* Set-up the clock divider. */
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289 /* Wait until access to Endint protected register is enabled. */
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290 while( 0 != ( WDT_CON0.reg & 0x1UL ) );
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292 /* RMC == 1 so STM Clock == FPI */
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293 STM_CLC.reg = ( 1UL << 8 );
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297 /* Determine how many bits are used without changing other bits in the CMCON register. */
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298 STM_CMCON.reg &= ~( 0x1fUL );
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299 STM_CMCON.reg |= ( 0x1fUL - __CLZ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) );
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301 /* Take into account the current time so a tick doesn't happen immediately. */
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302 STM_CMP0.reg = ulCompareMatchValue + STM_TIM0.reg;
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304 if( 0 != _install_int_handler( configKERNEL_INTERRUPT_PRIORITY, prvSystemTickHandler, 0 ) )
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306 /* Set-up the interrupt. */
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307 STM_SRC0.reg = ( configKERNEL_INTERRUPT_PRIORITY | 0x00005000UL );
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309 /* Enable the Interrupt. */
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310 STM_ISRR.reg &= ~( 0x03UL );
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311 STM_ISRR.reg |= 0x1UL;
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312 STM_ISRR.reg &= ~( 0x07UL );
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313 STM_ICR.reg |= 0x1UL;
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317 /* Failed to install the Tick Interrupt. */
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318 configASSERT( ( ( volatile void * ) NULL ) );
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321 /*-----------------------------------------------------------*/
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323 static void prvSystemTickHandler( int iArg )
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325 unsigned long ulSavedInterruptMask;
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326 unsigned long *pxUpperCSA = NULL;
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327 unsigned long xUpperCSA = 0UL;
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328 extern volatile unsigned long *pxCurrentTCB;
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329 long lYieldRequired;
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331 /* Just to avoid compiler warnings about unused parameters. */
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334 /* Clear the interrupt source. */
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335 STM_ISRR.reg = 1UL;
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337 /* Reload the Compare Match register for X ticks into the future.
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339 If critical section or interrupt nesting budgets are exceeded, then
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340 it is possible that the calculated next compare match value is in the
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341 past. If this occurs (unlikely), it is possible that the resulting
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342 time slippage will exceed a single tick period. Any adverse effect of
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343 this is time bounded by the fact that only the first n bits of the 56 bit
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344 STM timer are being used for a compare match, so another compare match
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345 will occur after an overflow in just those n bits (not the entire 56 bits).
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346 As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz,
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347 a missed tick could result in the next tick interrupt occurring within a
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348 time that is 1.7 times the desired period. The fact that this is greater
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349 than a single tick period is an effect of using a timer that cannot be
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350 automatically reset, in hardware, by the occurrence of a tick interrupt.
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351 Changing the tick source to a timer that has an automatic reset on compare
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352 match (such as a GPTA timer) will reduce the maximum possible additional
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353 period to exactly 1 times the desired period. */
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354 STM_CMP0.reg += ulCompareMatchValue;
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356 /* Kernel API calls require Critical Sections. */
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357 ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
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359 /* Increment the Tick. */
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360 lYieldRequired = xTaskIncrementTick();
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362 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
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364 if( lYieldRequired != pdFALSE )
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366 /* Save the context of a task.
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367 The upper context is automatically saved when entering a trap or interrupt.
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368 Need to save the lower context as well and copy the PCXI CSA ID into
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369 pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
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372 Call vTaskSwitchContext to select the next task, note that this changes the
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373 value of pxCurrentTCB so that it needs to be reloaded.
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375 Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
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376 that has just been switched in.
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378 Load the context of the task.
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379 Need to restore the lower context by loading the CSA from
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380 pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
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381 In the Interrupt handler post-amble, RSLCX will restore the lower context
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382 of the task. RFE will restore the upper context of the task, jump to the
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383 return address and restore the previous state of interrupts being
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384 enabled/disabled. */
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387 xUpperCSA = _mfcr( $PCXI );
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388 pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
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389 *pxCurrentTCB = pxUpperCSA[ 0 ];
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390 vTaskSwitchContext();
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391 pxUpperCSA[ 0 ] = *pxCurrentTCB;
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392 CPU_SRC0.bits.SETR = 0;
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396 /*-----------------------------------------------------------*/
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399 * When a task is deleted, it is yielded permanently until the IDLE task
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400 * has an opportunity to reclaim the memory that that task was using.
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401 * Typically, the memory used by a task is the TCB and Stack but in the
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402 * TriCore this includes the CSAs that were consumed as part of the Call
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403 * Stack. These CSAs can only be returned to the Globally Free Pool when
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404 * they are not part of the current Call Stack, hence, delaying the
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405 * reclamation until the IDLE task is freeing the task's other resources.
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406 * This function uses the head of the linked list of CSAs (from when the
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407 * task yielded for the last time) and finds the tail (the very bottom of
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408 * the call stack) and inserts this list at the head of the Free list,
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409 * attaching the existing Free List to the tail of the reclaimed call stack.
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411 * NOTE: the IDLE task needs processing time to complete this function
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412 * and in heavily loaded systems, the Free CSAs may be consumed faster
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413 * than they can be freed assuming that tasks are being spawned and
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414 * deleted frequently.
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416 void vPortReclaimCSA( unsigned long *pxTCB )
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418 unsigned long pxHeadCSA, pxTailCSA, pxFreeCSA;
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419 unsigned long *pulNextCSA;
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421 /* A pointer to the first CSA in the list of CSAs consumed by the task is
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422 stored in the first element of the tasks TCB structure (where the stack
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423 pointer would be on a traditional stack based architecture). */
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424 pxHeadCSA = ( *pxTCB ) & portCSA_FCX_MASK;
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426 /* Mask off everything in the CSA link field other than the address. If
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427 the address is NULL, then the CSA is not linking anywhere and there is
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429 pxTailCSA = pxHeadCSA;
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431 /* Convert the link value to contain just a raw address and store this
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432 in a local variable. */
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433 pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
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435 /* Iterate over the CSAs that were consumed as part of the task. The
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436 first field in the CSA is the pointer to then next CSA. Mask off
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437 everything in the pointer to the next CSA, other than the link address.
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438 If this is NULL, then the CSA currently being pointed to is the last in
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440 while( 0UL != ( pulNextCSA[ 0 ] & portCSA_FCX_MASK ) )
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442 /* Clear all bits of the pointer to the next in the chain, other
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443 than the address bits themselves. */
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444 pulNextCSA[ 0 ] = pulNextCSA[ 0 ] & portCSA_FCX_MASK;
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446 /* Move the pointer to point to the next CSA in the list. */
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447 pxTailCSA = pulNextCSA[ 0 ];
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449 /* Update the local pointer to the CSA. */
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450 pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
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455 /* Look up the current free CSA head. */
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457 pxFreeCSA = _mfcr( $FCX );
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459 /* Join the current Free onto the Tail of what is being reclaimed. */
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460 portCSA_TO_ADDRESS( pxTailCSA )[ 0 ] = pxFreeCSA;
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462 /* Move the head of the reclaimed into the Free. */
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464 _mtcr( $FCX, pxHeadCSA );
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469 /*-----------------------------------------------------------*/
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471 void vPortEndScheduler( void )
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473 /* Nothing to do. Unlikely to want to end. */
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475 /*-----------------------------------------------------------*/
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477 static void prvTrapYield( int iTrapIdentification )
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479 unsigned long *pxUpperCSA = NULL;
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480 unsigned long xUpperCSA = 0UL;
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481 extern volatile unsigned long *pxCurrentTCB;
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483 switch( iTrapIdentification )
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485 case portSYSCALL_TASK_YIELD:
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486 /* Save the context of a task.
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487 The upper context is automatically saved when entering a trap or interrupt.
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488 Need to save the lower context as well and copy the PCXI CSA ID into
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489 pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
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492 Call vTaskSwitchContext to select the next task, note that this changes the
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493 value of pxCurrentTCB so that it needs to be reloaded.
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495 Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
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496 that has just been switched in.
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498 Load the context of the task.
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499 Need to restore the lower context by loading the CSA from
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500 pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
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501 In the Interrupt handler post-amble, RSLCX will restore the lower context
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502 of the task. RFE will restore the upper context of the task, jump to the
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503 return address and restore the previous state of interrupts being
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504 enabled/disabled. */
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507 xUpperCSA = _mfcr( $PCXI );
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508 pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
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509 *pxCurrentTCB = pxUpperCSA[ 0 ];
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510 vTaskSwitchContext();
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511 pxUpperCSA[ 0 ] = *pxCurrentTCB;
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512 CPU_SRC0.bits.SETR = 0;
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517 /* Unimplemented trap called. */
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518 configASSERT( ( ( volatile void * ) NULL ) );
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522 /*-----------------------------------------------------------*/
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524 static void prvInterruptYield( int iId )
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526 unsigned long *pxUpperCSA = NULL;
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527 unsigned long xUpperCSA = 0UL;
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528 extern volatile unsigned long *pxCurrentTCB;
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530 /* Just to remove compiler warnings. */
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533 /* Save the context of a task.
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534 The upper context is automatically saved when entering a trap or interrupt.
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535 Need to save the lower context as well and copy the PCXI CSA ID into
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536 pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
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539 Call vTaskSwitchContext to select the next task, note that this changes the
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540 value of pxCurrentTCB so that it needs to be reloaded.
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542 Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
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543 that has just been switched in.
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545 Load the context of the task.
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546 Need to restore the lower context by loading the CSA from
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547 pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
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548 In the Interrupt handler post-amble, RSLCX will restore the lower context
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549 of the task. RFE will restore the upper context of the task, jump to the
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550 return address and restore the previous state of interrupts being
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551 enabled/disabled. */
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554 xUpperCSA = _mfcr( $PCXI );
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555 pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
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556 *pxCurrentTCB = pxUpperCSA[ 0 ];
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557 vTaskSwitchContext();
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558 pxUpperCSA[ 0 ] = *pxCurrentTCB;
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559 CPU_SRC0.bits.SETR = 0;
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562 /*-----------------------------------------------------------*/
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564 unsigned long uxPortSetInterruptMaskFromISR( void )
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566 unsigned long uxReturn = 0UL;
\r
569 uxReturn = _mfcr( $ICR );
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570 _mtcr( $ICR, ( ( uxReturn & ~portCCPN_MASK ) | configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
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574 /* Return just the interrupt mask bits. */
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575 return ( uxReturn & portCCPN_MASK );
\r
577 /*-----------------------------------------------------------*/
\r