git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/TriCore_1782/porttrap.c

   1 /*\r
   2     FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.\r
   3 \r
   4     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   5 \r
   6     ***************************************************************************\r
   7      *                                                                       *\r
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  14      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
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  16      *    Thank you!                                                         *\r
  17      *                                                                       *\r
  18     ***************************************************************************\r
  19 \r
  20     This file is part of the FreeRTOS distribution.\r
  21 \r
  22     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  23     the terms of the GNU General Public License (version 2) as published by the\r
  24     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  25 \r
  26     >>! NOTE: The modification to the GPL is included to allow you to distribute\r
  27     >>! a combined work that includes FreeRTOS without being obliged to provide\r
  28     >>! the source code for proprietary components outside of the FreeRTOS\r
  29     >>! kernel.\r
  30 \r
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  32     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  33     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  34     link: http://www.freertos.org/a00114.html\r
  35 \r
  36     1 tab == 4 spaces!\r
  37 \r
  38     ***************************************************************************\r
  39      *                                                                       *\r
  40      *    Having a problem?  Start by reading the FAQ "My application does   *\r
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  46 \r
  47     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
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  49 \r
  50     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  51     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
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  53 \r
  54     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
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  57 \r
  58     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  59     engineered and independently SIL3 certified version for use in safety and\r
  60     mission critical applications that require provable dependability.\r
  61 \r
  62     1 tab == 4 spaces!\r
  63 */\r
  64 \r
  65 /* Kernel includes. */\r
  66 #include "FreeRTOS.h"\r
  67 \r
  68 /* Machine includes */\r
  69 #include <tc1782.h>\r
  70 #include <machine/intrinsics.h>\r
  71 #include <machine/cint.h>\r
  72 /*---------------------------------------------------------------------------*/\r
  73 \r
  74 /*\r
  75  * This reference is required by the Save/Restore Context Macros.\r
  76  */\r
  77 extern volatile unsigned long *pxCurrentTCB;\r
  78 /*-----------------------------------------------------------*/\r
  79 \r
  80 /*\r
  81  * This file contains base definitions for all of the possible traps in the system.\r
  82  * It is suggested to provide implementations for all of the traps but for\r
  83  * the time being they simply trigger a DEBUG instruction so that it is easy\r
  84  * to see what caused a particular trap.\r
  85  *\r
  86  * Trap Class 6, the SYSCALL, is used exclusively by the operating system.\r
  87  */\r
  88 \r
  89 /* The Trap Classes. */\r
  90 #define portMMU_TRAP                                                                            0\r
  91 #define portIPT_TRAP                                                                            1\r
  92 #define portIE_TRAP                                                                                     2\r
  93 #define portCM_TRAP                                                                                     3\r
  94 #define portSBP_TRAP                                                                            4\r
  95 #define portASSERT_TRAP                                                                         5\r
  96 #define portNMI_TRAP                                                                            7\r
  97 \r
  98 /* MMU Trap Identifications. */\r
  99 #define portTIN_MMU_VIRTUAL_ADDRESS_FILL                                        0\r
 100 #define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION                          1\r
 101 \r
 102 /* Internal Protection Trap Identifications. */\r
 103 #define portTIN_IPT_PRIVILIGED_INSTRUCTION                                      1\r
 104 #define portTIN_IPT_MEMORY_PROTECTION_READ                                      2\r
 105 #define portTIN_IPT_MEMORY_PROTECTION_WRITE                                     3\r
 106 #define portTIN_IPT_MEMORY_PROTECTION_EXECUTION                         4\r
 107 #define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS         5\r
 108 #define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS                      6\r
 109 #define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION  7\r
 110 \r
 111 /* Instruction Error Trap Identifications. */\r
 112 #define portTIN_IE_ILLEGAL_OPCODE                                                       1\r
 113 #define portTIN_IE_UNIMPLEMENTED_OPCODE                                         2\r
 114 #define portTIN_IE_INVALID_OPERAND                                                      3\r
 115 #define portTIN_IE_DATA_ADDRESS_ALIGNMENT                                       4\r
 116 #define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS                         5\r
 117 \r
 118 /* Context Management Trap Identifications. */\r
 119 #define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION                          1\r
 120 #define portTIN_CM_CALL_DEPTH_OVERFLOW                                          2\r
 121 #define portTIN_CM_CALL_DEPTH_UNDEFLOW                                          3\r
 122 #define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW                          4\r
 123 #define portTIN_CM_CALL_STACK_UNDERFLOW                                         5\r
 124 #define portTIN_CM_CONTEXT_TYPE                                                         6\r
 125 #define portTIN_CM_NESTING_ERROR                                                        7\r
 126 \r
 127 /* System Bus and Peripherals Trap Identifications. */\r
 128 #define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR                     1\r
 129 #define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR                       2\r
 130 #define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR                      3\r
 131 #define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR         4\r
 132 #define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR                      5\r
 133 #define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR                         6\r
 134 \r
 135 /* Assertion Trap Identifications. */\r
 136 #define portTIN_ASSERT_ARITHMETIC_OVERFLOW                                      1\r
 137 #define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW                       2\r
 138 \r
 139 /* Non-maskable Interrupt Trap Identifications. */\r
 140 #define portTIN_NMI_NON_MASKABLE_INTERRUPT                                      0\r
 141 /*---------------------------------------------------------------------------*/\r
 142 \r
 143 void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 144 void vInternalProtectionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 145 void vInstructionErrorTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 146 void vContextManagementTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 147 void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 148 void vAssertionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 149 void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 150 /*---------------------------------------------------------------------------*/\r
 151 \r
 152 void vTrapInstallHandlers( void )\r
 153 {\r
 154         if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )\r
 155         {\r
 156                 _debug();\r
 157         }\r
 158 \r
 159         if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )\r
 160         {\r
 161                 _debug();\r
 162         }\r
 163 \r
 164         if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )\r
 165         {\r
 166                 _debug();\r
 167         }\r
 168 \r
 169         if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )\r
 170         {\r
 171                 _debug();\r
 172         }\r
 173 \r
 174         if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )\r
 175         {\r
 176                 _debug();\r
 177         }\r
 178 \r
 179         if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )\r
 180         {\r
 181                 _debug();\r
 182         }\r
 183 \r
 184         if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )\r
 185         {\r
 186                 _debug();\r
 187         }\r
 188 }\r
 189 /*-----------------------------------------------------------*/\r
 190 \r
 191 void vMMUTrap( int iTrapIdentification )\r
 192 {\r
 193         switch( iTrapIdentification )\r
 194         {\r
 195         case portTIN_MMU_VIRTUAL_ADDRESS_FILL:\r
 196         case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:\r
 197         default:\r
 198                 _debug();\r
 199                 break;\r
 200         }\r
 201 }\r
 202 /*---------------------------------------------------------------------------*/\r
 203 \r
 204 void vInternalProtectionTrap( int iTrapIdentification )\r
 205 {\r
 206         /* Deliberate fall through to default. */\r
 207         switch( iTrapIdentification )\r
 208         {\r
 209                 case portTIN_IPT_PRIVILIGED_INSTRUCTION:\r
 210                         /* Instruction is not allowed at current execution level, eg DISABLE at User-0. */\r
 211 \r
 212                 case portTIN_IPT_MEMORY_PROTECTION_READ:\r
 213                         /* Load word using invalid address. */\r
 214                         \r
 215                 case portTIN_IPT_MEMORY_PROTECTION_WRITE:\r
 216                         /* Store Word using invalid address. */\r
 217                         \r
 218                 case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:\r
 219                         /* PC jumped to an address outside of the valid range. */\r
 220                         \r
 221                 case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:\r
 222                         /* Access to a peripheral denied at current execution level. */\r
 223                         \r
 224                 case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:\r
 225                         /* NULL Pointer. */\r
 226                         \r
 227                 case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:\r
 228                         /* Tried to modify a global address pointer register. */\r
 229                         \r
 230                 default:\r
 231                 \r
 232                         pxCurrentTCB[ 0 ] = _mfcr( $PCXI );\r
 233                         _debug();\r
 234                         break;\r
 235         }\r
 236 }\r
 237 /*---------------------------------------------------------------------------*/\r
 238 \r
 239 void vInstructionErrorTrap( int iTrapIdentification )\r
 240 {\r
 241         /* Deliberate fall through to default. */\r
 242         switch( iTrapIdentification )\r
 243         {\r
 244                 case portTIN_IE_ILLEGAL_OPCODE:\r
 245                 case portTIN_IE_UNIMPLEMENTED_OPCODE:\r
 246                 case portTIN_IE_INVALID_OPERAND:\r
 247                 case portTIN_IE_DATA_ADDRESS_ALIGNMENT:\r
 248                 case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:\r
 249                 default:\r
 250                         _debug();\r
 251                         break;\r
 252         }\r
 253 }\r
 254 /*---------------------------------------------------------------------------*/\r
 255 \r
 256 void vContextManagementTrap( int iTrapIdentification )\r
 257 {\r
 258         /* Deliberate fall through to default. */\r
 259         switch( iTrapIdentification )\r
 260         {\r
 261                 case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:\r
 262                 case portTIN_CM_CALL_DEPTH_OVERFLOW:\r
 263                 case portTIN_CM_CALL_DEPTH_UNDEFLOW:\r
 264                 case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:\r
 265                 case portTIN_CM_CALL_STACK_UNDERFLOW:\r
 266                 case portTIN_CM_CONTEXT_TYPE:\r
 267                 case portTIN_CM_NESTING_ERROR:\r
 268                 default:\r
 269                         _debug();\r
 270                         break;\r
 271         }\r
 272 }\r
 273 /*---------------------------------------------------------------------------*/\r
 274 \r
 275 void vSystemBusAndPeripheralsTrap( int iTrapIdentification )\r
 276 {\r
 277         /* Deliberate fall through to default. */\r
 278         switch( iTrapIdentification )\r
 279         {\r
 280                 case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:\r
 281                 case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:\r
 282                 case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:\r
 283                 case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:\r
 284                 case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:\r
 285                 case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:\r
 286                 default:\r
 287                         _debug();\r
 288                         break;\r
 289         }\r
 290 }\r
 291 /*---------------------------------------------------------------------------*/\r
 292 \r
 293 void vAssertionTrap( int iTrapIdentification )\r
 294 {\r
 295         /* Deliberate fall through to default. */\r
 296         switch( iTrapIdentification )\r
 297         {\r
 298                 case portTIN_ASSERT_ARITHMETIC_OVERFLOW:\r
 299                 case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:\r
 300                 default:\r
 301                         _debug();\r
 302                         break;\r
 303         }\r
 304 }\r
 305 /*---------------------------------------------------------------------------*/\r
 306 \r
 307 void vNonMaskableInterruptTrap( int iTrapIdentification )\r
 308 {\r
 309         /* Deliberate fall through to default. */\r
 310         switch( iTrapIdentification )\r
 311         {\r
 312                 case portTIN_NMI_NON_MASKABLE_INTERRUPT:\r
 313                 default:\r
 314                         _debug();\r
 315                         break;\r
 316         }\r
 317 }\r
 318 /*---------------------------------------------------------------------------*/\r