2 FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 /* Standard includes. */
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74 #include <intrinsics.h>
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76 /* Scheduler includes. */
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77 #include "FreeRTOS.h"
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80 #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
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81 #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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84 #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
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85 #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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88 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
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89 #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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92 #ifndef configSETUP_TICK_INTERRUPT
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93 #error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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94 #endif /* configSETUP_TICK_INTERRUPT */
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96 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
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97 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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100 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
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101 #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
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104 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
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105 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
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108 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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109 /* Check the configuration. */
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110 #if( configMAX_PRIORITIES > 32 )
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111 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
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113 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
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115 /* In case security extensions are implemented. */
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116 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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117 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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120 #ifndef configCLEAR_TICK_INTERRUPT
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121 #define configCLEAR_TICK_INTERRUPT()
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124 /* A critical section is exited when the critical section nesting count reaches
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126 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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128 /* In all GICs 255 can be written to the priority mask register to unmask all
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129 (but the lowest) interrupt priority. */
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130 #define portUNMASK_VALUE ( 0xFFUL )
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132 /* Tasks are not created with a floating point context, but can be given a
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133 floating point context after they have been created. A variable is stored as
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134 part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
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135 does not have an FPU context, or any other value if the task does have an FPU
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137 #define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
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139 /* Constants required to setup the initial task context. */
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140 #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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141 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
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142 #define portTHUMB_MODE_ADDRESS ( 0x01UL )
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144 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
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146 #define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
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148 /* Masks all bits in the APSR other than the mode bits. */
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149 #define portAPSR_MODE_BITS_MASK ( 0x1F )
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151 /* The value of the mode bits in the APSR when the CPU is executing in user
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153 #define portAPSR_USER_MODE ( 0x10 )
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155 /* Macro to unmask all interrupt priorities. */
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156 #define portCLEAR_INTERRUPT_MASK() \
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159 portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
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165 /*-----------------------------------------------------------*/
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168 * Starts the first task executing. This function is necessarily written in
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169 * assembly code so is implemented in portASM.s.
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171 extern void vPortRestoreTaskContext( void );
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174 * Used to catch tasks that attempt to return from their implementing function.
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176 static void prvTaskExitError( void );
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178 /*-----------------------------------------------------------*/
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180 /* A variable is used to keep track of the critical section nesting. This
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181 variable has to be stored as part of the task context and must be initialised to
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182 a non zero value to ensure interrupts don't inadvertently become unmasked before
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183 the scheduler starts. As it is stored as part of the task context it will
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184 automatically be set to 0 when the first task is started. */
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185 volatile uint32_t ulCriticalNesting = 9999UL;
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187 /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero
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188 then a floating point context must be saved and restored for the task. */
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189 uint32_t ulPortTaskHasFPUContext = pdFALSE;
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191 /* Set to 1 to pend a context switch from an ISR. */
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192 uint32_t ulPortYieldRequired = pdFALSE;
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194 /* Counts the interrupt nesting depth. A context switch is only performed if
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195 if the nesting depth is 0. */
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196 uint32_t ulPortInterruptNesting = 0UL;
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199 /*-----------------------------------------------------------*/
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202 * See header file for description.
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204 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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206 /* Setup the initial stack of the task. The stack is set exactly as
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207 expected by the portRESTORE_CONTEXT() macro.
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209 The fist real value on the stack is the status register, which is set for
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210 system mode, with interrupts enabled. A few NULLs are added first to ensure
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211 GDB does not try decoding a non-existent return address. */
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212 *pxTopOfStack = NULL;
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214 *pxTopOfStack = NULL;
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216 *pxTopOfStack = NULL;
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218 *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
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220 if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
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222 /* The task will start in THUMB mode. */
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223 *pxTopOfStack |= portTHUMB_MODE_BIT;
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228 /* Next the return address, which in this case is the start of the task. */
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229 *pxTopOfStack = ( StackType_t ) pxCode;
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232 /* Next all the registers other than the stack pointer. */
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233 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */
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235 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
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237 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
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239 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
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241 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
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243 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
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245 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
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247 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
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249 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
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251 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
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253 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
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255 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
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257 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
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259 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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262 /* The task will start with a critical nesting count of 0 as interrupts are
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264 *pxTopOfStack = portNO_CRITICAL_NESTING;
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267 /* The task will start without a floating point context. A task that uses
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268 the floating point hardware must call vPortTaskUsesFPU() before executing
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269 any floating point instructions. */
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270 *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
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272 return pxTopOfStack;
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274 /*-----------------------------------------------------------*/
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276 static void prvTaskExitError( void )
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278 /* A function that implements a task must not exit or attempt to return to
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279 its caller as there is nothing to return to. If a task wants to exit it
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280 should instead call vTaskDelete( NULL ).
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282 Artificially force an assert() to be triggered if configASSERT() is
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283 defined, then stop here so application writers can catch the error. */
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284 configASSERT( ulPortInterruptNesting == ~0UL );
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285 portDISABLE_INTERRUPTS();
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288 /*-----------------------------------------------------------*/
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290 BaseType_t xPortStartScheduler( void )
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294 /* Only continue if the CPU is not in User mode. The CPU must be in a
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295 Privileged mode for the scheduler to start. */
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296 __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
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297 ulAPSR &= portAPSR_MODE_BITS_MASK;
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298 configASSERT( ulAPSR != portAPSR_USER_MODE );
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300 if( ulAPSR != portAPSR_USER_MODE )
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302 /* Only continue if the binary point value is set to its lowest possible
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303 setting. See the comments in vPortValidateInterruptPriority() below for
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304 more information. */
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305 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
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307 if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
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309 /* Start the timer that generates the tick ISR. */
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310 configSETUP_TICK_INTERRUPT();
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313 vPortRestoreTaskContext();
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317 /* Will only get here if vTaskStartScheduler() was called with the CPU in
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318 a non-privileged mode or the binary point register was not set to its lowest
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322 /*-----------------------------------------------------------*/
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324 void vPortEndScheduler( void )
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326 /* Not implemented in ports where there is nothing to return to.
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327 Artificially force an assert. */
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328 configASSERT( ulCriticalNesting == 1000UL );
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330 /*-----------------------------------------------------------*/
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332 void vPortEnterCritical( void )
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334 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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335 ulPortSetInterruptMask();
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337 /* Now interrupts are disabled ulCriticalNesting can be accessed
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338 directly. Increment ulCriticalNesting to keep a count of how many times
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339 portENTER_CRITICAL() has been called. */
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340 ulCriticalNesting++;
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342 /* This is not the interrupt safe version of the enter critical function so
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343 assert() if it is being called from an interrupt context. Only API
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344 functions that end in "FromISR" can be used in an interrupt. Only assert if
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345 the critical nesting count is 1 to protect against recursive calls if the
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346 assert function also uses a critical section. */
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347 if( ulCriticalNesting == 1 )
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349 configASSERT( ulPortInterruptNesting == 0 );
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352 /*-----------------------------------------------------------*/
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354 void vPortExitCritical( void )
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356 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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358 /* Decrement the nesting count as the critical section is being
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360 ulCriticalNesting--;
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362 /* If the nesting level has reached zero then all interrupt
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363 priorities must be re-enabled. */
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364 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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366 /* Critical nesting has reached zero so all interrupt priorities
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367 should be unmasked. */
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368 portCLEAR_INTERRUPT_MASK();
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372 /*-----------------------------------------------------------*/
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374 void FreeRTOS_Tick_Handler( void )
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376 /* Set interrupt mask before altering scheduler structures. The tick
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377 handler runs at the lowest priority, so interrupts cannot already be masked,
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378 so there is no need to save and restore the current mask value. */
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380 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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385 /* Increment the RTOS tick. */
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386 if( xTaskIncrementTick() != pdFALSE )
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388 ulPortYieldRequired = pdTRUE;
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391 /* Ensure all interrupt priorities are active again. */
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392 portCLEAR_INTERRUPT_MASK();
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393 configCLEAR_TICK_INTERRUPT();
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395 /*-----------------------------------------------------------*/
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397 void vPortTaskUsesFPU( void )
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399 uint32_t ulInitialFPSCR = 0;
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401 /* A task is registering the fact that it needs an FPU context. Set the
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402 FPU flag (which is saved as part of the task context). */
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403 ulPortTaskHasFPUContext = pdTRUE;
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405 /* Initialise the floating point status register. */
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406 __asm( "FMXR FPSCR, %0" :: "r" (ulInitialFPSCR) );
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408 /*-----------------------------------------------------------*/
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410 void vPortClearInterruptMask( uint32_t ulNewMaskValue )
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412 if( ulNewMaskValue == pdFALSE )
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414 portCLEAR_INTERRUPT_MASK();
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417 /*-----------------------------------------------------------*/
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419 uint32_t ulPortSetInterruptMask( void )
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424 if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
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426 /* Interrupts were already masked. */
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431 ulReturn = pdFALSE;
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432 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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440 /*-----------------------------------------------------------*/
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442 #if( configASSERT_DEFINED == 1 )
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444 void vPortValidateInterruptPriority( void )
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446 /* The following assertion will fail if a service routine (ISR) for
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447 an interrupt that has been assigned a priority above
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448 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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449 function. ISR safe FreeRTOS API functions must *only* be called
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450 from interrupts that have been assigned a priority at or below
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451 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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453 Numerically low interrupt priority numbers represent logically high
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454 interrupt priorities, therefore the priority of the interrupt must
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455 be set to a value equal to or numerically *higher* than
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456 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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458 FreeRTOS maintains separate thread and ISR API functions to ensure
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459 interrupt entry is as fast and simple as possible.
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461 The following links provide detailed information:
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462 http://www.freertos.org/RTOS-Cortex-M3-M4.html
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463 http://www.freertos.org/FAQHelp.html */
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464 configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
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466 /* Priority grouping: The interrupt controller (GIC) allows the bits
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467 that define each interrupt's priority to be split between bits that
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468 define the interrupt's pre-emption priority bits and bits that define
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469 the interrupt's sub-priority. For simplicity all bits must be defined
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470 to be pre-emption priority bits. The following assertion will fail if
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471 this is not the case (if some bits represent a sub-priority).
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473 The priority grouping is configured by the GIC's binary point register
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474 (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
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475 possible value (which may be above 0). */
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476 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
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479 #endif /* configASSERT_DEFINED */
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