2 * FreeRTOS Kernel V10.2.1
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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29 EXTERN vTaskSwitchContext
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30 EXTERN vPortSVCHandler_C
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32 PUBLIC xIsPrivileged
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33 PUBLIC vResetPrivilege
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34 PUBLIC vRestoreContextOfFirstTask
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35 PUBLIC vRaisePrivilege
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36 PUBLIC vStartFirstTask
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37 PUBLIC ulSetInterruptMaskFromISR
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38 PUBLIC vClearInterruptMaskFromISR
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39 PUBLIC PendSV_Handler
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42 #if ( configENABLE_FPU == 1 )
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43 #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
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45 /*-----------------------------------------------------------*/
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47 /*---------------- Unprivileged Functions -------------------*/
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49 /*-----------------------------------------------------------*/
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51 SECTION .text:CODE:NOROOT(2)
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53 /*-----------------------------------------------------------*/
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56 mrs r0, control /* r0 = CONTROL. */
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57 movs r1, #1 /* r1 = 1. */
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58 tst r0, r1 /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
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59 beq running_privileged /* If the result of previous AND operation was 0, branch. */
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60 movs r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
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63 movs r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
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66 /*-----------------------------------------------------------*/
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69 mrs r0, control /* r0 = CONTROL. */
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70 movs r1, #1 /* r1 = 1. */
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71 orrs r0, r1 /* r0 = r0 | r1. */
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72 msr control, r0 /* CONTROL = r0. */
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73 bx lr /* Return to the caller. */
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74 /*-----------------------------------------------------------*/
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76 /*----------------- Privileged Functions --------------------*/
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78 /*-----------------------------------------------------------*/
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80 SECTION privileged_functions:CODE:NOROOT(2)
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82 /*-----------------------------------------------------------*/
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84 vRestoreContextOfFirstTask:
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85 ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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86 ldr r1, [r2] /* Read pxCurrentTCB. */
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87 ldr r0, [r1] /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
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89 #if ( configENABLE_MPU == 1 )
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90 dmb /* Complete outstanding transfers before disabling MPU. */
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91 ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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92 ldr r3, [r2] /* Read the value of MPU_CTRL. */
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93 movs r4, #1 /* r4 = 1. */
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94 bics r3, r4 /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
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95 str r3, [r2] /* Disable MPU. */
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97 adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
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98 ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */
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99 ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
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100 str r4, [r2] /* Program MAIR0. */
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101 ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
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102 adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
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103 movs r4, #4 /* r4 = 4. */
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104 str r4, [r2] /* Program RNR = 4. */
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105 ldmia r1!, {r5,r6} /* Read first set of RBAR/RLAR from TCB. */
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106 ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */
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107 stmia r3!, {r5,r6} /* Write first set of RBAR/RLAR registers. */
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108 movs r4, #5 /* r4 = 5. */
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109 str r4, [r2] /* Program RNR = 5. */
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110 ldmia r1!, {r5,r6} /* Read second set of RBAR/RLAR from TCB. */
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111 ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */
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112 stmia r3!, {r5,r6} /* Write second set of RBAR/RLAR registers. */
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113 movs r4, #6 /* r4 = 6. */
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114 str r4, [r2] /* Program RNR = 6. */
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115 ldmia r1!, {r5,r6} /* Read third set of RBAR/RLAR from TCB. */
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116 ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */
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117 stmia r3!, {r5,r6} /* Write third set of RBAR/RLAR registers. */
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118 movs r4, #7 /* r4 = 7. */
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119 str r4, [r2] /* Program RNR = 7. */
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120 ldmia r1!, {r5,r6} /* Read fourth set of RBAR/RLAR from TCB. */
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121 ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */
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122 stmia r3!, {r5,r6} /* Write fourth set of RBAR/RLAR registers. */
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124 ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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125 ldr r3, [r2] /* Read the value of MPU_CTRL. */
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126 movs r4, #1 /* r4 = 1. */
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127 orrs r3, r4 /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
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128 str r3, [r2] /* Enable MPU. */
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129 dsb /* Force memory writes before continuing. */
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130 #endif /* configENABLE_MPU */
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132 #if ( configENABLE_MPU == 1 )
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133 ldm r0!, {r1-r3} /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
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134 msr psplim, r1 /* Set this task's PSPLIM value. */
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135 msr control, r2 /* Set this task's CONTROL value. */
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136 adds r0, #32 /* Discard everything up to r0. */
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137 msr psp, r0 /* This is now the new top of stack to use in the task. */
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139 bx r3 /* Finally, branch to EXC_RETURN. */
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140 #else /* configENABLE_MPU */
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141 ldm r0!, {r1-r2} /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
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142 msr psplim, r1 /* Set this task's PSPLIM value. */
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143 movs r1, #2 /* r1 = 2. */
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144 msr CONTROL, r1 /* Switch to use PSP in the thread mode. */
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145 adds r0, #32 /* Discard everything up to r0. */
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146 msr psp, r0 /* This is now the new top of stack to use in the task. */
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148 bx r2 /* Finally, branch to EXC_RETURN. */
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149 #endif /* configENABLE_MPU */
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150 /*-----------------------------------------------------------*/
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153 mrs r0, control /* Read the CONTROL register. */
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154 movs r1, #1 /* r1 = 1. */
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155 bics r0, r1 /* Clear the bit 0. */
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156 msr control, r0 /* Write back the new CONTROL value. */
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157 bx lr /* Return to the caller. */
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158 /*-----------------------------------------------------------*/
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161 ldr r0, =0xe000ed08 /* Use the NVIC offset register to locate the stack. */
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162 ldr r0, [r0] /* Read the VTOR register which gives the address of vector table. */
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163 ldr r0, [r0] /* The first entry in vector table is stack pointer. */
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164 msr msp, r0 /* Set the MSP back to the start of the stack. */
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165 cpsie i /* Globally enable interrupts. */
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168 svc 2 /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
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170 /*-----------------------------------------------------------*/
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172 ulSetInterruptMaskFromISR:
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176 /*-----------------------------------------------------------*/
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178 vClearInterruptMaskFromISR:
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181 /*-----------------------------------------------------------*/
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184 mrs r0, psp /* Read PSP in r0. */
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185 ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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186 ldr r1, [r2] /* Read pxCurrentTCB. */
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187 #if ( configENABLE_MPU == 1 )
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188 subs r0, r0, #44 /* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
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189 str r0, [r1] /* Save the new top of stack in TCB. */
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190 mrs r1, psplim /* r1 = PSPLIM. */
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191 mrs r2, control /* r2 = CONTROL. */
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192 mov r3, lr /* r3 = LR/EXC_RETURN. */
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193 stmia r0!, {r1-r7} /* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
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194 mov r4, r8 /* r4 = r8. */
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195 mov r5, r9 /* r5 = r9. */
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196 mov r6, r10 /* r6 = r10. */
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197 mov r7, r11 /* r7 = r11. */
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198 stmia r0!, {r4-r7} /* Store the high registers that are not saved automatically. */
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199 #else /* configENABLE_MPU */
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200 subs r0, r0, #40 /* Make space for PSPLIM, LR and the remaining registers on the stack. */
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201 str r0, [r1] /* Save the new top of stack in TCB. */
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202 mrs r2, psplim /* r2 = PSPLIM. */
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203 mov r3, lr /* r3 = LR/EXC_RETURN. */
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204 stmia r0!, {r2-r7} /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
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205 mov r4, r8 /* r4 = r8. */
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206 mov r5, r9 /* r5 = r9. */
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207 mov r6, r10 /* r6 = r10. */
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208 mov r7, r11 /* r7 = r11. */
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209 stmia r0!, {r4-r7} /* Store the high registers that are not saved automatically. */
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210 #endif /* configENABLE_MPU */
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213 bl vTaskSwitchContext
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216 ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
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217 ldr r1, [r2] /* Read pxCurrentTCB. */
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218 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
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220 #if ( configENABLE_MPU == 1 )
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221 dmb /* Complete outstanding transfers before disabling MPU. */
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222 ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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223 ldr r3, [r2] /* Read the value of MPU_CTRL. */
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224 movs r4, #1 /* r4 = 1. */
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225 bics r3, r4 /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
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226 str r3, [r2] /* Disable MPU. */
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228 adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
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229 ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */
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230 ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
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231 str r4, [r2] /* Program MAIR0. */
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232 ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
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233 adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
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234 movs r4, #4 /* r4 = 4. */
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235 str r4, [r2] /* Program RNR = 4. */
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236 ldmia r1!, {r5,r6} /* Read first set of RBAR/RLAR from TCB. */
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237 ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */
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238 stmia r3!, {r5,r6} /* Write first set of RBAR/RLAR registers. */
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239 movs r4, #5 /* r4 = 5. */
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240 str r4, [r2] /* Program RNR = 5. */
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241 ldmia r1!, {r5,r6} /* Read second set of RBAR/RLAR from TCB. */
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242 ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */
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243 stmia r3!, {r5,r6} /* Write second set of RBAR/RLAR registers. */
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244 movs r4, #6 /* r4 = 6. */
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245 str r4, [r2] /* Program RNR = 6. */
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246 ldmia r1!, {r5,r6} /* Read third set of RBAR/RLAR from TCB. */
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247 ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */
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248 stmia r3!, {r5,r6} /* Write third set of RBAR/RLAR registers. */
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249 movs r4, #7 /* r4 = 7. */
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250 str r4, [r2] /* Program RNR = 7. */
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251 ldmia r1!, {r5,r6} /* Read fourth set of RBAR/RLAR from TCB. */
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252 ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */
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253 stmia r3!, {r5,r6} /* Write fourth set of RBAR/RLAR registers. */
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255 ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
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256 ldr r3, [r2] /* Read the value of MPU_CTRL. */
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257 movs r4, #1 /* r4 = 1. */
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258 orrs r3, r4 /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
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259 str r3, [r2] /* Enable MPU. */
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260 dsb /* Force memory writes before continuing. */
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261 #endif /* configENABLE_MPU */
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263 #if ( configENABLE_MPU == 1 )
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264 adds r0, r0, #28 /* Move to the high registers. */
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265 ldmia r0!, {r4-r7} /* Restore the high registers that are not automatically restored. */
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266 mov r8, r4 /* r8 = r4. */
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267 mov r9, r5 /* r9 = r5. */
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268 mov r10, r6 /* r10 = r6. */
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269 mov r11, r7 /* r11 = r7. */
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270 msr psp, r0 /* Remember the new top of stack for the task. */
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271 subs r0, r0, #44 /* Move to the starting of the saved context. */
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272 ldmia r0!, {r1-r7} /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
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273 msr psplim, r1 /* Restore the PSPLIM register value for the task. */
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274 msr control, r2 /* Restore the CONTROL register value for the task. */
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276 #else /* configENABLE_MPU */
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277 adds r0, r0, #24 /* Move to the high registers. */
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278 ldmia r0!, {r4-r7} /* Restore the high registers that are not automatically restored. */
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279 mov r8, r4 /* r8 = r4. */
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280 mov r9, r5 /* r9 = r5. */
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281 mov r10, r6 /* r10 = r6. */
\r
282 mov r11, r7 /* r11 = r7. */
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283 msr psp, r0 /* Remember the new top of stack for the task. */
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284 subs r0, r0, #40 /* Move to the starting of the saved context. */
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285 ldmia r0!, {r2-r7} /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
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286 msr psplim, r2 /* Restore the PSPLIM register value for the task. */
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288 #endif /* configENABLE_MPU */
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289 /*-----------------------------------------------------------*/
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295 beq stacking_used_msp
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297 b vPortSVCHandler_C
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300 b vPortSVCHandler_C
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301 /*-----------------------------------------------------------*/
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