2 * FreeRTOS Kernel V10.2.0
\r
3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
\r
5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
\r
6 * this software and associated documentation files (the "Software"), to deal in
\r
7 * the Software without restriction, including without limitation the rights to
\r
8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
\r
9 * the Software, and to permit persons to whom the Software is furnished to do so,
\r
10 * subject to the following conditions:
\r
12 * The above copyright notice and this permission notice shall be included in all
\r
13 * copies or substantial portions of the Software.
\r
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
\r
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
\r
17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
\r
18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
\r
19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
\r
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
\r
22 * http://www.FreeRTOS.org
\r
23 * http://aws.amazon.com/freertos
\r
25 * 1 tab == 4 spaces!
\r
28 /* Standard includes. */
\r
31 /* Secure init includes. */
\r
32 #include "secure_init.h"
\r
34 /* Secure port macros. */
\r
35 #include "secure_port_macros.h"
\r
38 * @brief Constants required to manipulate the SCB.
\r
40 #define secureinitSCB_AIRCR ( ( volatile uint32_t * ) 0xe000ed0c ) /* Application Interrupt and Reset Control Register. */
\r
41 #define secureinitSCB_AIRCR_VECTKEY_POS ( 16UL )
\r
42 #define secureinitSCB_AIRCR_VECTKEY_MASK ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
\r
43 #define secureinitSCB_AIRCR_PRIS_POS ( 14UL )
\r
44 #define secureinitSCB_AIRCR_PRIS_MASK ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
\r
47 * @brief Constants required to manipulate the FPU.
\r
49 #define secureinitFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
\r
50 #define secureinitFPCCR_LSPENS_POS ( 29UL )
\r
51 #define secureinitFPCCR_LSPENS_MASK ( 1UL << secureinitFPCCR_LSPENS_POS )
\r
52 #define secureinitFPCCR_TS_POS ( 26UL )
\r
53 #define secureinitFPCCR_TS_MASK ( 1UL << secureinitFPCCR_TS_POS )
\r
55 #define secureinitNSACR ( ( volatile uint32_t * ) 0xe000ed8c ) /* Non-secure Access Control Register. */
\r
56 #define secureinitNSACR_CP10_POS ( 10UL )
\r
57 #define secureinitNSACR_CP10_MASK ( 1UL << secureinitNSACR_CP10_POS )
\r
58 #define secureinitNSACR_CP11_POS ( 11UL )
\r
59 #define secureinitNSACR_CP11_MASK ( 1UL << secureinitNSACR_CP11_POS )
\r
60 /*-----------------------------------------------------------*/
\r
62 secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
\r
66 /* Read the Interrupt Program Status Register (IPSR) value. */
\r
67 secureportREAD_IPSR( ulIPSR );
\r
69 /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
\r
70 * when the processor is running in the Thread Mode. */
\r
73 *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
\r
74 ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
\r
75 ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
\r
78 /*-----------------------------------------------------------*/
\r
80 secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
\r
84 /* Read the Interrupt Program Status Register (IPSR) value. */
\r
85 secureportREAD_IPSR( ulIPSR );
\r
87 /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
\r
88 * when the processor is running in the Thread Mode. */
\r
91 /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
\r
92 * permitted. CP11 should be programmed to the same value as CP10. */
\r
93 *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
\r
95 /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
\r
96 * that we can enable/disable lazy stacking in port.c file. */
\r
97 *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
\r
99 /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
\r
100 * registers (S16-S31) are also pushed to stack on exception entry and
\r
101 * restored on exception return. */
\r
102 *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
\r
105 /*-----------------------------------------------------------*/
\r