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[freertos] / FreeRTOS / Source / portable / IAR / ARM_CM33_NTZ / non_secure / port.c
1 /*\r
2  * FreeRTOS Kernel V10.2.0\r
3  * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
4  *\r
5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
6  * this software and associated documentation files (the "Software"), to deal in\r
7  * the Software without restriction, including without limitation the rights to\r
8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
10  * subject to the following conditions:\r
11  *\r
12  * The above copyright notice and this permission notice shall be included in all\r
13  * copies or substantial portions of the Software.\r
14  *\r
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
21  *\r
22  * http://www.FreeRTOS.org\r
23  * http://aws.amazon.com/freertos\r
24  *\r
25  * 1 tab == 4 spaces!\r
26  */\r
27 \r
28 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
29  * all the API functions to use the MPU wrappers. That should only be done when\r
30  * task.h is included from an application file. */\r
31 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
32 \r
33 /* Scheduler includes. */\r
34 #include "FreeRTOS.h"\r
35 #include "task.h"\r
36 \r
37 /* MPU wrappers includes. */\r
38 #include "mpu_wrappers.h"\r
39 \r
40 /* Portasm includes. */\r
41 #include "portasm.h"\r
42 \r
43 #if( configENABLE_TRUSTZONE == 1 )\r
44         /* Secure components includes. */\r
45         #include "secure_context.h"\r
46         #include "secure_init.h"\r
47 #endif /* configENABLE_TRUSTZONE */\r
48 \r
49 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
50 \r
51 /**\r
52  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\r
53  * i.e. the processor boots as secure and never jumps to the non-secure side.\r
54  * The Trust Zone support in the port must be disabled in order to run FreeRTOS\r
55  * on the secure side. The following are the valid configuration seetings:\r
56  *\r
57  * 1. Run FreeRTOS on the Secure Side:\r
58  *              configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\r
59  *\r
60  * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\r
61  *              configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\r
62  *\r
63  * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\r
64  *              configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\r
65  */\r
66 #if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\r
67         #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\r
68 #endif\r
69 /*-----------------------------------------------------------*/\r
70 \r
71 /**\r
72  * @brief Constants required to manipulate the NVIC.\r
73  */\r
74 #define portNVIC_SYSTICK_CTRL                           ( ( volatile uint32_t * ) 0xe000e010 )\r
75 #define portNVIC_SYSTICK_LOAD                           ( ( volatile uint32_t * ) 0xe000e014 )\r
76 #define portNVIC_SYSTICK_CURRENT_VALUE          ( ( volatile uint32_t * ) 0xe000e018 )\r
77 #define portNVIC_INT_CTRL                                       ( ( volatile uint32_t * ) 0xe000ed04 )\r
78 #define portNVIC_SYSPRI2                                        ( ( volatile uint32_t * ) 0xe000ed20 )\r
79 #define portNVIC_SYSTICK_CLK                            ( 0x00000004 )\r
80 #define portNVIC_SYSTICK_INT                            ( 0x00000002 )\r
81 #define portNVIC_SYSTICK_ENABLE                         ( 0x00000001 )\r
82 #define portNVIC_PENDSVSET                                      ( 0x10000000 )\r
83 #define portMIN_INTERRUPT_PRIORITY                      ( 255UL )\r
84 #define portNVIC_PENDSV_PRI                                     ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
85 #define portNVIC_SYSTICK_PRI                            ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
86 /*-----------------------------------------------------------*/\r
87 \r
88 /**\r
89  * @brief Constants required to manipulate the SCB.\r
90  */\r
91 #define portSCB_SYS_HANDLER_CTRL_STATE_REG      ( * ( volatile uint32_t * ) 0xe000ed24 )\r
92 #define portSCB_MEM_FAULT_ENABLE                        ( 1UL << 16UL )\r
93 /*-----------------------------------------------------------*/\r
94 \r
95 /**\r
96  * @brief Constants required to manipulate the FPU.\r
97  */\r
98 #define portCPACR                                                       ( ( volatile uint32_t * ) 0xe000ed88 )  /* Coprocessor Access Control Register. */\r
99 #define portCPACR_CP10_VALUE                            ( 3UL )\r
100 #define portCPACR_CP11_VALUE                            portCPACR_CP10_VALUE\r
101 #define portCPACR_CP10_POS                                      ( 20UL )\r
102 #define portCPACR_CP11_POS                                      ( 22UL )\r
103 \r
104 #define portFPCCR                                                       ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */\r
105 #define portFPCCR_ASPEN_POS                                     ( 31UL )\r
106 #define portFPCCR_ASPEN_MASK                            ( 1UL << portFPCCR_ASPEN_POS )\r
107 #define portFPCCR_LSPEN_POS                                     ( 30UL )\r
108 #define portFPCCR_LSPEN_MASK                            ( 1UL << portFPCCR_LSPEN_POS )\r
109 /*-----------------------------------------------------------*/\r
110 \r
111 /**\r
112  * @brief Constants required to manipulate the MPU.\r
113  */\r
114 #define portMPU_TYPE_REG                                        ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
115 #define portMPU_CTRL_REG                                        ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
116 #define portMPU_RNR_REG                                         ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
117 \r
118 #define portMPU_RBAR_REG                                        ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
119 #define portMPU_RLAR_REG                                        ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
120 \r
121 #define portMPU_RBAR_A1_REG                                     ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
122 #define portMPU_RLAR_A1_REG                                     ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
123 \r
124 #define portMPU_RBAR_A2_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
125 #define portMPU_RLAR_A2_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
126 \r
127 #define portMPU_RBAR_A3_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
128 #define portMPU_RLAR_A3_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
129 \r
130 #define portMPU_MAIR0_REG                                       ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
131 #define portMPU_MAIR1_REG                                       ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
132 \r
133 #define portMPU_RBAR_ADDRESS_MASK                       ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
134 #define portMPU_RLAR_ADDRESS_MASK                       ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
135 \r
136 #define portMPU_MAIR_ATTR0_POS                          ( 0UL )\r
137 #define portMPU_MAIR_ATTR0_MASK                         ( 0x000000ff )\r
138 \r
139 #define portMPU_MAIR_ATTR1_POS                          ( 8UL )\r
140 #define portMPU_MAIR_ATTR1_MASK                         ( 0x0000ff00 )\r
141 \r
142 #define portMPU_MAIR_ATTR2_POS                          ( 16UL )\r
143 #define portMPU_MAIR_ATTR2_MASK                         ( 0x00ff0000 )\r
144 \r
145 #define portMPU_MAIR_ATTR3_POS                          ( 24UL )\r
146 #define portMPU_MAIR_ATTR3_MASK                         ( 0xff000000 )\r
147 \r
148 #define portMPU_MAIR_ATTR4_POS                          ( 0UL )\r
149 #define portMPU_MAIR_ATTR4_MASK                         ( 0x000000ff )\r
150 \r
151 #define portMPU_MAIR_ATTR5_POS                          ( 8UL )\r
152 #define portMPU_MAIR_ATTR5_MASK                         ( 0x0000ff00 )\r
153 \r
154 #define portMPU_MAIR_ATTR6_POS                          ( 16UL )\r
155 #define portMPU_MAIR_ATTR6_MASK                         ( 0x00ff0000 )\r
156 \r
157 #define portMPU_MAIR_ATTR7_POS                          ( 24UL )\r
158 #define portMPU_MAIR_ATTR7_MASK                         ( 0xff000000 )\r
159 \r
160 #define portMPU_RLAR_ATTR_INDEX0                        ( 0UL << 1UL )\r
161 #define portMPU_RLAR_ATTR_INDEX1                        ( 1UL << 1UL )\r
162 #define portMPU_RLAR_ATTR_INDEX2                        ( 2UL << 1UL )\r
163 #define portMPU_RLAR_ATTR_INDEX3                        ( 3UL << 1UL )\r
164 #define portMPU_RLAR_ATTR_INDEX4                        ( 4UL << 1UL )\r
165 #define portMPU_RLAR_ATTR_INDEX5                        ( 5UL << 1UL )\r
166 #define portMPU_RLAR_ATTR_INDEX6                        ( 6UL << 1UL )\r
167 #define portMPU_RLAR_ATTR_INDEX7                        ( 7UL << 1UL )\r
168 \r
169 #define portMPU_RLAR_REGION_ENABLE                      ( 1UL )\r
170 \r
171 /* Enable privileged access to unmapped region. */\r
172 #define portMPU_PRIV_BACKGROUND_ENABLE          ( 1UL << 2UL )\r
173 \r
174 /* Enable MPU. */\r
175 #define portMPU_ENABLE                                          ( 1UL << 0UL )\r
176 \r
177 /* Expected value of the portMPU_TYPE register. */\r
178 #define portEXPECTED_MPU_TYPE_VALUE                     ( 8UL << 8UL ) /* 8 regions, unified. */\r
179 /*-----------------------------------------------------------*/\r
180 \r
181 /**\r
182  * @brief Constants required to set up the initial stack.\r
183  */\r
184 #define portINITIAL_XPSR                                        ( 0x01000000 )\r
185 \r
186 #if( configRUN_FREERTOS_SECURE_ONLY == 1 )\r
187         /**\r
188          * @brief Initial EXC_RETURN value.\r
189          *\r
190          *     FF         FF         FF         FD\r
191          * 1111 1111  1111 1111  1111 1111  1111 1101\r
192          *\r
193          * Bit[6] - 1 --> The exception was taken from the Secure state.\r
194          * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
195          * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
196          * Bit[3] - 1 --> Return to the Thread mode.\r
197          * Bit[2] - 1 --> Restore registers from the process stack.\r
198          * Bit[1] - 0 --> Reserved, 0.\r
199          * Bit[0] - 1 --> The exception was taken to the Secure state.\r
200          */\r
201         #define portINITIAL_EXC_RETURN                  ( 0xfffffffd )\r
202 #else\r
203         /**\r
204          * @brief Initial EXC_RETURN value.\r
205          *\r
206          *     FF         FF         FF         BC\r
207          * 1111 1111  1111 1111  1111 1111  1011 1100\r
208          *\r
209          * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
210          * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
211          * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
212          * Bit[3] - 1 --> Return to the Thread mode.\r
213          * Bit[2] - 1 --> Restore registers from the process stack.\r
214          * Bit[1] - 0 --> Reserved, 0.\r
215          * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
216          */\r
217         #define portINITIAL_EXC_RETURN                  ( 0xffffffbc )\r
218 #endif /* configRUN_FREERTOS_SECURE_ONLY */\r
219 \r
220 /**\r
221  * @brief CONTROL register privileged bit mask.\r
222  *\r
223  * Bit[0] in CONTROL register tells the privilege:\r
224  *  Bit[0] = 0 ==> The task is privileged.\r
225  *  Bit[0] = 1 ==> The task is not privileged.\r
226  */\r
227 #define portCONTROL_PRIVILEGED_MASK                     ( 1UL << 0UL )\r
228 \r
229 /**\r
230  * @brief Initial CONTROL register values.\r
231  */\r
232 #define portINITIAL_CONTROL_UNPRIVILEGED        ( 0x3 )\r
233 #define portINITIAL_CONTROL_PRIVILEGED          ( 0x2 )\r
234 \r
235 /**\r
236  * @brief Let the user override the pre-loading of the initial LR with the\r
237  * address of prvTaskExitError() in case it messes up unwinding of the stack\r
238  * in the debugger.\r
239  */\r
240 #ifdef configTASK_RETURN_ADDRESS\r
241         #define portTASK_RETURN_ADDRESS                 configTASK_RETURN_ADDRESS\r
242 #else\r
243         #define portTASK_RETURN_ADDRESS                 prvTaskExitError\r
244 #endif\r
245 \r
246 /**\r
247  * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\r
248  * when a task is created. This helps in debugging at the cost of code size.\r
249  */\r
250 #define portPRELOAD_REGISTERS                           1\r
251 \r
252 /**\r
253  * @brief A task is created without a secure context, and must call\r
254  * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\r
255  * any secure calls.\r
256  */\r
257 #define portNO_SECURE_CONTEXT                           0\r
258 /*-----------------------------------------------------------*/\r
259 \r
260 /**\r
261  * @brief Setup the timer to generate the tick interrupts.\r
262  */\r
263 static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
264 \r
265 /**\r
266  * @brief Used to catch tasks that attempt to return from their implementing\r
267  * function.\r
268  */\r
269 static void prvTaskExitError( void );\r
270 \r
271 #if( configENABLE_MPU == 1 )\r
272         /**\r
273          * @brief Setup the Memory Protection Unit (MPU).\r
274          */\r
275         static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
276 #endif /* configENABLE_MPU */\r
277 \r
278 #if( configENABLE_FPU == 1 )\r
279         /**\r
280          * @brief Setup the Floating Point Unit (FPU).\r
281          */\r
282         static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
283 #endif /* configENABLE_FPU */\r
284 \r
285 /**\r
286  * @brief Yield the processor.\r
287  */\r
288 void vPortYield( void ) PRIVILEGED_FUNCTION;\r
289 \r
290 /**\r
291  * @brief Enter critical section.\r
292  */\r
293 void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\r
294 \r
295 /**\r
296  * @brief Exit from critical section.\r
297  */\r
298 void vPortExitCritical( void ) PRIVILEGED_FUNCTION;\r
299 \r
300 /**\r
301  * @brief SysTick handler.\r
302  */\r
303 void SysTick_Handler( void ) PRIVILEGED_FUNCTION;\r
304 \r
305 /**\r
306  * @brief C part of SVC handler.\r
307  */\r
308 void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
309 /*-----------------------------------------------------------*/\r
310 \r
311 /**\r
312  * @brief Each task maintains its own interrupt status in the critical nesting\r
313  * variable.\r
314  */\r
315 static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\r
316 \r
317 #if( configENABLE_TRUSTZONE == 1 )\r
318         /**\r
319          * @brief Saved as part of the task context to indicate which context the\r
320          * task is using on the secure side.\r
321          */\r
322         volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
323 #endif /* configENABLE_TRUSTZONE */\r
324 /*-----------------------------------------------------------*/\r
325 \r
326 static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
327 {\r
328         /* Stop and reset the SysTick. */\r
329         *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
330         *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
331 \r
332         /* Configure SysTick to interrupt at the requested rate. */\r
333         *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
334         *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
335 }\r
336 /*-----------------------------------------------------------*/\r
337 \r
338 static void prvTaskExitError( void )\r
339 {\r
340 volatile uint32_t ulDummy = 0UL;\r
341 \r
342         /* A function that implements a task must not exit or attempt to return to\r
343          * its caller as there is nothing to return to. If a task wants to exit it\r
344          * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
345          * to be triggered if configASSERT() is defined, then stop here so\r
346          * application writers can catch the error. */\r
347         configASSERT( ulCriticalNesting == ~0UL );\r
348         portDISABLE_INTERRUPTS();\r
349 \r
350         while( ulDummy == 0 )\r
351         {\r
352                 /* This file calls prvTaskExitError() after the scheduler has been\r
353                  * started to remove a compiler warning about the function being\r
354                  * defined but never called.  ulDummy is used purely to quieten other\r
355                  * warnings about code appearing after this function is called - making\r
356                  * ulDummy volatile makes the compiler think the function could return\r
357                  * and therefore not output an 'unreachable code' warning for code that\r
358                  * appears after it. */\r
359         }\r
360 }\r
361 /*-----------------------------------------------------------*/\r
362 \r
363 #if( configENABLE_MPU == 1 )\r
364         static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
365         {\r
366         #if defined( __ARMCC_VERSION )\r
367                 /* Declaration when these variable are defined in code instead of being\r
368                  * exported from linker scripts. */\r
369                 extern uint32_t * __privileged_functions_start__;\r
370                 extern uint32_t * __privileged_functions_end__;\r
371                 extern uint32_t * __syscalls_flash_start__;\r
372                 extern uint32_t * __unprivileged_flash_end__;\r
373                 extern uint32_t * __privileged_sram_start__;\r
374                 extern uint32_t * __privileged_sram_end__;\r
375         #else\r
376                 /* Declaration when these variable are exported from linker scripts. */\r
377                 extern uint32_t __privileged_functions_start__[];\r
378                 extern uint32_t __privileged_functions_end__[];\r
379                 extern uint32_t __syscalls_flash_start__[];\r
380                 extern uint32_t __unprivileged_flash_end__[];\r
381                 extern uint32_t __privileged_sram_start__[];\r
382                 extern uint32_t __privileged_sram_end__[];\r
383         #endif /* defined( __ARMCC_VERSION ) */\r
384 \r
385                 /* Check that the MPU is present. */\r
386                 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
387                 {\r
388                         /* MAIR0 - Index 0. */\r
389                         portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
390                         /* MAIR0 - Index 1. */\r
391                         portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
392 \r
393                         /* Setup privileged flash as Read Only so that privileged tasks can\r
394                          * read it but not modify. */\r
395                         portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
396                         portMPU_RBAR_REG =      ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
397                                                                 ( portMPU_REGION_NON_SHAREABLE ) |\r
398                                                                 ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
399                         portMPU_RLAR_REG =      ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
400                                                                 ( portMPU_RLAR_ATTR_INDEX0 ) |\r
401                                                                 ( portMPU_RLAR_REGION_ENABLE );\r
402 \r
403                         /* Setup unprivileged flash and system calls flash as Read Only by\r
404                          * both privileged and unprivileged tasks. All tasks can read it but\r
405                          * no-one can modify. */\r
406                         portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
407                         portMPU_RBAR_REG =      ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
408                                                                 ( portMPU_REGION_NON_SHAREABLE ) |\r
409                                                                 ( portMPU_REGION_READ_ONLY );\r
410                         portMPU_RLAR_REG =      ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
411                                                                 ( portMPU_RLAR_ATTR_INDEX0 ) |\r
412                                                                 ( portMPU_RLAR_REGION_ENABLE );\r
413 \r
414                         /* Setup RAM containing kernel data for privileged access only. */\r
415                         portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
416                         portMPU_RBAR_REG =      ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
417                                                                 ( portMPU_REGION_NON_SHAREABLE ) |\r
418                                                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
419                                                                 ( portMPU_REGION_EXECUTE_NEVER );\r
420                         portMPU_RLAR_REG =      ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
421                                                                 ( portMPU_RLAR_ATTR_INDEX0 ) |\r
422                                                                 ( portMPU_RLAR_REGION_ENABLE );\r
423 \r
424                         /* By default allow everything to access the general peripherals.\r
425                          * The system peripherals and registers are protected. */\r
426                         portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;\r
427                         portMPU_RBAR_REG =      ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |\r
428                                                                 ( portMPU_REGION_NON_SHAREABLE ) |\r
429                                                                 ( portMPU_REGION_READ_WRITE ) |\r
430                                                                 ( portMPU_REGION_EXECUTE_NEVER );\r
431                         portMPU_RLAR_REG =      ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |\r
432                                                                 ( portMPU_RLAR_ATTR_INDEX1 ) |\r
433                                                                 ( portMPU_RLAR_REGION_ENABLE );\r
434 \r
435                         /* Enable mem fault. */\r
436                         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
437 \r
438                         /* Enable MPU with privileged background access i.e. unmapped\r
439                          * regions have privileged access. */\r
440                         portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
441                 }\r
442         }\r
443 #endif /* configENABLE_MPU */\r
444 /*-----------------------------------------------------------*/\r
445 \r
446 #if( configENABLE_FPU == 1 )\r
447         static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
448         {\r
449                 #if( configENABLE_TRUSTZONE == 1 )\r
450                 {\r
451                         /* Enable non-secure access to the FPU. */\r
452                         SecureInit_EnableNSFPUAccess();\r
453                 }\r
454                 #endif /* configENABLE_TRUSTZONE */\r
455 \r
456                 /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
457                  * unprivileged code should be able to access FPU. CP11 should be\r
458                  * programmed to the same value as CP10. */\r
459                 *( portCPACR ) |=       (       ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
460                                                                 ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
461                                                         );\r
462 \r
463                 /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
464                  * context on exception entry and restore on exception return.\r
465                  * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
466                 *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
467         }\r
468 #endif /* configENABLE_FPU */\r
469 /*-----------------------------------------------------------*/\r
470 \r
471 void vPortYield( void ) /* PRIVILEGED_FUNCTION */\r
472 {\r
473         /* Set a PendSV to request a context switch. */\r
474         *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
475 \r
476         /* Barriers are normally not required but do ensure the code is\r
477          * completely within the specified behaviour for the architecture. */\r
478         __asm volatile( "dsb" ::: "memory" );\r
479         __asm volatile( "isb" );\r
480 }\r
481 /*-----------------------------------------------------------*/\r
482 \r
483 void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\r
484 {\r
485         portDISABLE_INTERRUPTS();\r
486         ulCriticalNesting++;\r
487 \r
488         /* Barriers are normally not required but do ensure the code is\r
489          * completely within the specified behaviour for the architecture. */\r
490         __asm volatile( "dsb" ::: "memory" );\r
491         __asm volatile( "isb" );\r
492 }\r
493 /*-----------------------------------------------------------*/\r
494 \r
495 void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\r
496 {\r
497         configASSERT( ulCriticalNesting );\r
498         ulCriticalNesting--;\r
499 \r
500         if( ulCriticalNesting == 0 )\r
501         {\r
502                 portENABLE_INTERRUPTS();\r
503         }\r
504 }\r
505 /*-----------------------------------------------------------*/\r
506 \r
507 void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\r
508 {\r
509 uint32_t ulPreviousMask;\r
510 \r
511         ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
512         {\r
513                 /* Increment the RTOS tick. */\r
514                 if( xTaskIncrementTick() != pdFALSE )\r
515                 {\r
516                         /* Pend a context switch. */\r
517                         *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
518                 }\r
519         }\r
520         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
521 }\r
522 /*-----------------------------------------------------------*/\r
523 \r
524 void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */\r
525 {\r
526 #if( configENABLE_MPU == 1 )\r
527         #if defined( __ARMCC_VERSION )\r
528                 /* Declaration when these variable are defined in code instead of being\r
529                  * exported from linker scripts. */\r
530                 extern uint32_t * __syscalls_flash_start__;\r
531                 extern uint32_t * __syscalls_flash_end__;\r
532         #else\r
533                 /* Declaration when these variable are exported from linker scripts. */\r
534                 extern uint32_t __syscalls_flash_start__[];\r
535                 extern uint32_t __syscalls_flash_end__[];\r
536         #endif /* defined( __ARMCC_VERSION ) */\r
537 #endif /* configENABLE_MPU */\r
538 \r
539 uint32_t ulPC;\r
540 \r
541 #if( configENABLE_TRUSTZONE == 1 )\r
542         uint32_t ulR0;\r
543         #if( configENABLE_MPU == 1 )\r
544                 uint32_t ulControl, ulIsTaskPrivileged;\r
545         #endif /* configENABLE_MPU */\r
546 #endif /* configENABLE_TRUSTZONE */\r
547 uint8_t ucSVCNumber;\r
548 \r
549         /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
550          * R12, LR, PC, xPSR. */\r
551         ulPC = pulCallerStackAddress[ 6 ];\r
552         ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
553 \r
554         switch( ucSVCNumber )\r
555         {\r
556                 #if( configENABLE_TRUSTZONE == 1 )\r
557                         case portSVC_ALLOCATE_SECURE_CONTEXT:\r
558                         {\r
559                                 /* R0 contains the stack size passed as parameter to the\r
560                                  * vPortAllocateSecureContext function. */\r
561                                 ulR0 = pulCallerStackAddress[ 0 ];\r
562 \r
563                                 #if( configENABLE_MPU == 1 )\r
564                                 {\r
565                                         /* Read the CONTROL register value. */\r
566                                         __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );\r
567 \r
568                                         /* The task that raised the SVC is privileged if Bit[0]\r
569                                          * in the CONTROL register is 0. */\r
570                                         ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
571 \r
572                                         /* Allocate and load a context for the secure task. */\r
573                                         xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
574                                 }\r
575                                 #else\r
576                                 {\r
577                                         /* Allocate and load a context for the secure task. */\r
578                                         xSecureContext = SecureContext_AllocateContext( ulR0 );\r
579                                 }\r
580                                 #endif /* configENABLE_MPU */\r
581 \r
582                                 configASSERT( xSecureContext != NULL );\r
583                                 SecureContext_LoadContext( xSecureContext );\r
584                         }\r
585                         break;\r
586 \r
587                         case portSVC_FREE_SECURE_CONTEXT:\r
588                         {\r
589                                 /* R0 contains the secure context handle to be freed. */\r
590                                 ulR0 = pulCallerStackAddress[ 0 ];\r
591 \r
592                                 /* Free the secure context. */\r
593                                 SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
594                         }\r
595                         break;\r
596                 #endif /* configENABLE_TRUSTZONE */\r
597 \r
598                 case portSVC_START_SCHEDULER:\r
599                 {\r
600                         #if( configENABLE_TRUSTZONE == 1 )\r
601                         {\r
602                                 /* De-prioritize the non-secure exceptions so that the\r
603                                  * non-secure pendSV runs at the lowest priority. */\r
604                                 SecureInit_DePrioritizeNSExceptions();\r
605 \r
606                                 /* Initialize the secure context management system. */\r
607                                 SecureContext_Init();\r
608                         }\r
609                         #endif /* configENABLE_TRUSTZONE */\r
610 \r
611                         #if( configENABLE_FPU == 1 )\r
612                         {\r
613                                 /* Setup the Floating Point Unit (FPU). */\r
614                                 prvSetupFPU();\r
615                         }\r
616                         #endif /* configENABLE_FPU */\r
617 \r
618                         /* Setup the context of the first task so that the first task starts\r
619                          * executing. */\r
620                         vRestoreContextOfFirstTask();\r
621                 }\r
622                 break;\r
623 \r
624                 #if( configENABLE_MPU == 1 )\r
625                         case portSVC_RAISE_PRIVILEGE:\r
626                         {\r
627                                 /* Only raise the privilege, if the svc was raised from any of\r
628                                  * the system calls. */\r
629                                 if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
630                                         ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
631                                 {\r
632                                         vRaisePrivilege();\r
633                                 }\r
634                         }\r
635                         break;\r
636                 #endif /* configENABLE_MPU */\r
637 \r
638                 default:\r
639                 {\r
640                         /* Incorrect SVC call. */\r
641                         configASSERT( pdFALSE );\r
642                 }\r
643         }\r
644 }\r
645 /*-----------------------------------------------------------*/\r
646 \r
647 #if( configENABLE_MPU == 1 )\r
648         StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
649 #else\r
650         StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
651 #endif /* configENABLE_MPU */\r
652 {\r
653         /* Simulate the stack frame as it would be created by a context switch\r
654          * interrupt. */\r
655         #if( portPRELOAD_REGISTERS == 0 )\r
656         {\r
657                 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
658                 *pxTopOfStack = portINITIAL_XPSR;                                                       /* xPSR */\r
659                 pxTopOfStack--;\r
660                 *pxTopOfStack = ( StackType_t ) pxCode;                                         /* PC */\r
661                 pxTopOfStack--;\r
662                 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;        /* LR */\r
663                 pxTopOfStack -= 5;                                                                                      /* R12, R3, R2 and R1. */\r
664                 *pxTopOfStack = ( StackType_t ) pvParameters;                           /* R0 */\r
665                 pxTopOfStack -= 9;                                                                                      /* R11..R4, EXC_RETURN. */\r
666                 *pxTopOfStack = portINITIAL_EXC_RETURN;\r
667 \r
668                 #if( configENABLE_MPU == 1 )\r
669                 {\r
670                         pxTopOfStack--;\r
671                         if( xRunPrivileged == pdTRUE )\r
672                         {\r
673                                 *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;         /* Slot used to hold this task's CONTROL value. */\r
674                         }\r
675                         else\r
676                         {\r
677                                 *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;       /* Slot used to hold this task's CONTROL value. */\r
678                         }\r
679                 }\r
680                 #endif /* configENABLE_MPU */\r
681 \r
682                 pxTopOfStack--;\r
683                 *pxTopOfStack = ( StackType_t ) pxEndOfStack;   /* Slot used to hold this task's PSPLIM value. */\r
684 \r
685                 #if( configENABLE_TRUSTZONE == 1 )\r
686                 {\r
687                         pxTopOfStack--;\r
688                         *pxTopOfStack = portNO_SECURE_CONTEXT;          /* Slot used to hold this task's xSecureContext value. */\r
689                 }\r
690                 #endif /* configENABLE_TRUSTZONE */\r
691         }\r
692         #else /* portPRELOAD_REGISTERS */\r
693         {\r
694                 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
695                 *pxTopOfStack = portINITIAL_XPSR;                                                       /* xPSR */\r
696                 pxTopOfStack--;\r
697                 *pxTopOfStack = ( StackType_t ) pxCode;                                         /* PC */\r
698                 pxTopOfStack--;\r
699                 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;        /* LR */\r
700                 pxTopOfStack--;\r
701                 *pxTopOfStack = ( StackType_t ) 0x12121212UL;                           /* R12 */\r
702                 pxTopOfStack--;\r
703                 *pxTopOfStack = ( StackType_t ) 0x03030303UL;                           /* R3 */\r
704                 pxTopOfStack--;\r
705                 *pxTopOfStack = ( StackType_t ) 0x02020202UL;                           /* R2 */\r
706                 pxTopOfStack--;\r
707                 *pxTopOfStack = ( StackType_t ) 0x01010101UL;                           /* R1 */\r
708                 pxTopOfStack--;\r
709                 *pxTopOfStack = ( StackType_t ) pvParameters;                           /* R0 */\r
710                 pxTopOfStack--;\r
711                 *pxTopOfStack = ( StackType_t ) 0x11111111UL;                           /* R11 */\r
712                 pxTopOfStack--;\r
713                 *pxTopOfStack = ( StackType_t ) 0x10101010UL;                           /* R10 */\r
714                 pxTopOfStack--;\r
715                 *pxTopOfStack = ( StackType_t ) 0x09090909UL;                           /* R09 */\r
716                 pxTopOfStack--;\r
717                 *pxTopOfStack = ( StackType_t ) 0x08080808UL;                           /* R08 */\r
718                 pxTopOfStack--;\r
719                 *pxTopOfStack = ( StackType_t ) 0x07070707UL;                           /* R07 */\r
720                 pxTopOfStack--;\r
721                 *pxTopOfStack = ( StackType_t ) 0x06060606UL;                           /* R06 */\r
722                 pxTopOfStack--;\r
723                 *pxTopOfStack = ( StackType_t ) 0x05050505UL;                           /* R05 */\r
724                 pxTopOfStack--;\r
725                 *pxTopOfStack = ( StackType_t ) 0x04040404UL;                           /* R04 */\r
726                 pxTopOfStack--;\r
727                 *pxTopOfStack = portINITIAL_EXC_RETURN;                                         /* EXC_RETURN */\r
728 \r
729                 #if( configENABLE_MPU == 1 )\r
730                 {\r
731                         pxTopOfStack--;\r
732                         if( xRunPrivileged == pdTRUE )\r
733                         {\r
734                                 *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;         /* Slot used to hold this task's CONTROL value. */\r
735                         }\r
736                         else\r
737                         {\r
738                                 *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;       /* Slot used to hold this task's CONTROL value. */\r
739                         }\r
740                 }\r
741                 #endif /* configENABLE_MPU */\r
742 \r
743                 pxTopOfStack--;\r
744                 *pxTopOfStack = ( StackType_t ) pxEndOfStack;   /* Slot used to hold this task's PSPLIM value. */\r
745 \r
746                 #if( configENABLE_TRUSTZONE == 1 )\r
747                 {\r
748                         pxTopOfStack--;\r
749                         *pxTopOfStack = portNO_SECURE_CONTEXT;          /* Slot used to hold this task's xSecureContext value. */\r
750                 }\r
751                 #endif /* configENABLE_TRUSTZONE */\r
752         }\r
753         #endif /* portPRELOAD_REGISTERS */\r
754 \r
755         return pxTopOfStack;\r
756 }\r
757 /*-----------------------------------------------------------*/\r
758 \r
759 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\r
760 {\r
761         /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
762         *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
763         *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
764 \r
765         #if( configENABLE_MPU == 1 )\r
766         {\r
767                 /* Setup the Memory Protection Unit (MPU). */\r
768                 prvSetupMPU();\r
769         }\r
770         #endif /* configENABLE_MPU */\r
771 \r
772         /* Start the timer that generates the tick ISR. Interrupts are disabled\r
773          * here already. */\r
774         prvSetupTimerInterrupt();\r
775 \r
776         /* Initialize the critical nesting count ready for the first task. */\r
777         ulCriticalNesting = 0;\r
778 \r
779         /* Start the first task. */\r
780         vStartFirstTask();\r
781 \r
782         /* Should never get here as the tasks will now be executing. Call the task\r
783          * exit error function to prevent compiler warnings about a static function\r
784          * not being called in the case that the application writer overrides this\r
785          * functionality by defining configTASK_RETURN_ADDRESS. Call\r
786          * vTaskSwitchContext() so link time optimization does not remove the\r
787          * symbol. */\r
788         vTaskSwitchContext();\r
789         prvTaskExitError();\r
790 \r
791         /* Should not get here. */\r
792         return 0;\r
793 }\r
794 /*-----------------------------------------------------------*/\r
795 \r
796 void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\r
797 {\r
798         /* Not implemented in ports where there is nothing to return to.\r
799          * Artificially force an assert. */\r
800         configASSERT( ulCriticalNesting == 1000UL );\r
801 }\r
802 /*-----------------------------------------------------------*/\r
803 \r
804 #if( configENABLE_MPU == 1 )\r
805         void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
806         {\r
807         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
808         int32_t lIndex = 0;\r
809 \r
810                 /* Setup MAIR0. */\r
811                 xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
812                 xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
813 \r
814                 /* This function is called automatically when the task is created - in\r
815                  * which case the stack region parameters will be valid.  At all other\r
816                  * times the stack parameters will not be valid and it is assumed that\r
817                  * the stack region has already been configured. */\r
818                 if( ulStackDepth > 0 )\r
819                 {\r
820                         /* Define the region that allows access to the stack. */\r
821                         ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
822                         ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
823                         ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;\r
824 \r
825                         xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =    ( ulRegionStartAddress ) |\r
826                                                                                                                         ( portMPU_REGION_NON_SHAREABLE ) |\r
827                                                                                                                         ( portMPU_REGION_READ_WRITE ) |\r
828                                                                                                                         ( portMPU_REGION_EXECUTE_NEVER );\r
829 \r
830                         xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =    ( ulRegionEndAddress ) |\r
831                                                                                                                         ( portMPU_RLAR_ATTR_INDEX0 ) |\r
832                                                                                                                         ( portMPU_RLAR_REGION_ENABLE );\r
833                 }\r
834 \r
835                 /* User supplied configurable regions. */\r
836                 for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
837                 {\r
838                         /* If xRegions is NULL i.e. the task has not specified any MPU\r
839                          * region, the else part ensures that all the configurable MPU\r
840                          * regions are invalidated. */\r
841                         if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
842                         {\r
843                                 /* Translate the generic region definition contained in xRegions\r
844                                  * into the ARMv8 specific MPU settings that are then stored in\r
845                                  * xMPUSettings. */\r
846                                 ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
847                                 ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
848                                 ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;\r
849 \r
850                                 /* Start address. */\r
851                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =       ( ulRegionStartAddress ) |\r
852                                                                                                                                                         ( portMPU_REGION_NON_SHAREABLE );\r
853 \r
854                                 /* RO/RW. */\r
855                                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
856                                 {\r
857                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
858                                 }\r
859                                 else\r
860                                 {\r
861                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
862                                 }\r
863 \r
864                                 /* XN. */\r
865                                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
866                                 {\r
867                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
868                                 }\r
869 \r
870                                 /* End Address. */\r
871                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =       ( ulRegionEndAddress ) |\r
872                                                                                                                                                         ( portMPU_RLAR_REGION_ENABLE );\r
873 \r
874                                 /* Normal memory/ Device memory. */\r
875                                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
876                                 {\r
877                                         /* Attr1 in MAIR0 is configured as device memory. */\r
878                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
879                                 }\r
880                                 else\r
881                                 {\r
882                                         /* Attr1 in MAIR0 is configured as normal memory. */\r
883                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
884                                 }\r
885                         }\r
886                         else\r
887                         {\r
888                                 /* Invalidate the region. */\r
889                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
890                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
891                         }\r
892 \r
893                         lIndex++;\r
894                 }\r
895         }\r
896 #endif /* configENABLE_MPU */\r
897 /*-----------------------------------------------------------*/\r