2 * FreeRTOS Kernel V10.2.0
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
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29 * all the API functions to use the MPU wrappers. That should only be done when
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30 * task.h is included from an application file. */
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31 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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33 /* Scheduler includes. */
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34 #include "FreeRTOS.h"
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37 /* MPU wrappers includes. */
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38 #include "mpu_wrappers.h"
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40 /* Portasm includes. */
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41 #include "portasm.h"
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43 #if( configENABLE_TRUSTZONE == 1 )
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44 /* Secure components includes. */
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45 #include "secure_context.h"
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46 #include "secure_init.h"
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47 #endif /* configENABLE_TRUSTZONE */
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49 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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50 /*-----------------------------------------------------------*/
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53 * @brief Constants required to manipulate the NVIC.
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55 #define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )
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56 #define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )
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57 #define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )
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58 #define portNVIC_INT_CTRL ( ( volatile uint32_t * ) 0xe000ed04 )
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59 #define portNVIC_SYSPRI2 ( ( volatile uint32_t * ) 0xe000ed20 )
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60 #define portNVIC_SYSTICK_CLK ( 0x00000004 )
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61 #define portNVIC_SYSTICK_INT ( 0x00000002 )
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62 #define portNVIC_SYSTICK_ENABLE ( 0x00000001 )
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63 #define portNVIC_PENDSVSET ( 0x10000000 )
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64 #define portMIN_INTERRUPT_PRIORITY ( 255UL )
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65 #define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
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66 #define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
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67 /*-----------------------------------------------------------*/
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70 * @brief Constants required to manipulate the SCB.
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72 #define portSCB_SYS_HANDLER_CTRL_STATE_REG ( * ( volatile uint32_t * ) 0xe000ed24 )
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73 #define portSCB_MEM_FAULT_ENABLE ( 1UL << 16UL )
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74 /*-----------------------------------------------------------*/
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77 * @brief Constants required to manipulate the FPU.
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79 #define portCPACR ( ( volatile uint32_t * ) 0xe000ed88 ) /* Coprocessor Access Control Register. */
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80 #define portCPACR_CP10_VALUE ( 3UL )
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81 #define portCPACR_CP11_VALUE portCPACR_CP10_VALUE
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82 #define portCPACR_CP10_POS ( 20UL )
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83 #define portCPACR_CP11_POS ( 22UL )
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85 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating Point Context Control Register. */
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86 #define portFPCCR_ASPEN_POS ( 31UL )
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87 #define portFPCCR_ASPEN_MASK ( 1UL << portFPCCR_ASPEN_POS )
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88 #define portFPCCR_LSPEN_POS ( 30UL )
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89 #define portFPCCR_LSPEN_MASK ( 1UL << portFPCCR_LSPEN_POS )
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90 /*-----------------------------------------------------------*/
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93 * @brief Constants required to manipulate the MPU.
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95 #define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
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96 #define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
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97 #define portMPU_RNR_REG ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
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99 #define portMPU_RBAR_REG ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
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100 #define portMPU_RLAR_REG ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
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102 #define portMPU_RBAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
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103 #define portMPU_RLAR_A1_REG ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
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105 #define portMPU_RBAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edac ) )
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106 #define portMPU_RLAR_A2_REG ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
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108 #define portMPU_RBAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
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109 #define portMPU_RLAR_A3_REG ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
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111 #define portMPU_MAIR0_REG ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
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112 #define portMPU_MAIR1_REG ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
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114 #define portMPU_RBAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
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115 #define portMPU_RLAR_ADDRESS_MASK ( 0xffffffe0 ) /* Must be 32-byte aligned. */
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117 #define portMPU_MAIR_ATTR0_POS ( 0UL )
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118 #define portMPU_MAIR_ATTR0_MASK ( 0x000000ff )
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120 #define portMPU_MAIR_ATTR1_POS ( 8UL )
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121 #define portMPU_MAIR_ATTR1_MASK ( 0x0000ff00 )
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123 #define portMPU_MAIR_ATTR2_POS ( 16UL )
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124 #define portMPU_MAIR_ATTR2_MASK ( 0x00ff0000 )
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126 #define portMPU_MAIR_ATTR3_POS ( 24UL )
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127 #define portMPU_MAIR_ATTR3_MASK ( 0xff000000 )
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129 #define portMPU_MAIR_ATTR4_POS ( 0UL )
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130 #define portMPU_MAIR_ATTR4_MASK ( 0x000000ff )
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132 #define portMPU_MAIR_ATTR5_POS ( 8UL )
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133 #define portMPU_MAIR_ATTR5_MASK ( 0x0000ff00 )
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135 #define portMPU_MAIR_ATTR6_POS ( 16UL )
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136 #define portMPU_MAIR_ATTR6_MASK ( 0x00ff0000 )
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138 #define portMPU_MAIR_ATTR7_POS ( 24UL )
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139 #define portMPU_MAIR_ATTR7_MASK ( 0xff000000 )
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141 #define portMPU_RLAR_ATTR_INDEX0 ( 0UL << 1UL )
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142 #define portMPU_RLAR_ATTR_INDEX1 ( 1UL << 1UL )
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143 #define portMPU_RLAR_ATTR_INDEX2 ( 2UL << 1UL )
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144 #define portMPU_RLAR_ATTR_INDEX3 ( 3UL << 1UL )
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145 #define portMPU_RLAR_ATTR_INDEX4 ( 4UL << 1UL )
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146 #define portMPU_RLAR_ATTR_INDEX5 ( 5UL << 1UL )
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147 #define portMPU_RLAR_ATTR_INDEX6 ( 6UL << 1UL )
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148 #define portMPU_RLAR_ATTR_INDEX7 ( 7UL << 1UL )
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150 #define portMPU_RLAR_REGION_ENABLE ( 1UL )
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152 /* Enable privileged access to unmapped region. */
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153 #define portMPU_PRIV_BACKGROUND_ENABLE ( 1UL << 2UL )
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156 #define portMPU_ENABLE ( 1UL << 0UL )
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158 /* Expected value of the portMPU_TYPE register. */
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159 #define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
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160 /*-----------------------------------------------------------*/
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163 * @brief Constants required to set up the initial stack.
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165 #define portINITIAL_XPSR ( 0x01000000 )
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168 * @brief Initial EXC_RETURN value.
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171 * 1111 1111 1111 1111 1111 1111 1011 1100
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173 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
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174 * Bit[5] - 1 --> Do not skip stacking of additional state context.
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175 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
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176 * Bit[3] - 1 --> Return to the Thread mode.
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177 * Bit[2] - 1 --> Restore registers from the process stack.
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178 * Bit[1] - 0 --> Reserved, 0.
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179 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
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181 #define portINITIAL_EXC_RETURN ( 0xffffffbc )
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184 * @brief CONTROL register privileged bit mask.
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186 * Bit[0] in CONTROL register tells the privilege:
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187 * Bit[0] = 0 ==> The task is privileged.
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188 * Bit[0] = 1 ==> The task is not privileged.
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190 #define portCONTROL_PRIVILEGED_MASK ( 1UL << 0UL )
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193 * @brief Initial CONTROL register values.
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195 #define portINITIAL_CONTROL_UNPRIVILEGED ( 0x3 )
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196 #define portINITIAL_CONTROL_PRIVILEGED ( 0x2 )
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199 * @brief Let the user override the pre-loading of the initial LR with the
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200 * address of prvTaskExitError() in case it messes up unwinding of the stack
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203 #ifdef configTASK_RETURN_ADDRESS
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204 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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206 #define portTASK_RETURN_ADDRESS prvTaskExitError
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210 * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
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211 * when a task is created. This helps in debugging at the cost of code size.
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213 #define portPRELOAD_REGISTERS 1
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216 * @brief A task is created without a secure context, and must call
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217 * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
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218 * any secure calls.
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220 #define portNO_SECURE_CONTEXT 0
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221 /*-----------------------------------------------------------*/
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224 * @brief Setup the timer to generate the tick interrupts.
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226 static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
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229 * @brief Used to catch tasks that attempt to return from their implementing
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232 static void prvTaskExitError( void );
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234 #if( configENABLE_MPU == 1 )
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236 * @brief Setup the Memory Protection Unit (MPU).
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238 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
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239 #endif /* configENABLE_MPU */
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241 #if( configENABLE_FPU == 1 )
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243 * @brief Setup the Floating Point Unit (FPU).
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245 static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
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246 #endif /* configENABLE_FPU */
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249 * @brief Yield the processor.
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251 void vPortYield( void ) PRIVILEGED_FUNCTION;
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254 * @brief Enter critical section.
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256 void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
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259 * @brief Exit from critical section.
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261 void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
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264 * @brief SysTick handler.
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266 void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
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269 * @brief C part of SVC handler.
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271 void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
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272 /*-----------------------------------------------------------*/
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275 * @brief Each task maintains its own interrupt status in the critical nesting
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278 static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
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280 #if( configENABLE_TRUSTZONE == 1 )
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282 * @brief Saved as part of the task context to indicate which context the
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283 * task is using on the secure side.
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285 volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
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286 #endif /* configENABLE_TRUSTZONE */
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287 /*-----------------------------------------------------------*/
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289 static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
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291 /* Stop and reset the SysTick. */
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292 *( portNVIC_SYSTICK_CTRL ) = 0UL;
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293 *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
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295 /* Configure SysTick to interrupt at the requested rate. */
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296 *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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297 *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
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299 /*-----------------------------------------------------------*/
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301 static void prvTaskExitError( void )
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303 volatile uint32_t ulDummy = 0UL;
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305 /* A function that implements a task must not exit or attempt to return to
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306 * its caller as there is nothing to return to. If a task wants to exit it
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307 * should instead call vTaskDelete( NULL ). Artificially force an assert()
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308 * to be triggered if configASSERT() is defined, then stop here so
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309 * application writers can catch the error. */
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310 configASSERT( ulCriticalNesting == ~0UL );
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311 portDISABLE_INTERRUPTS();
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313 while( ulDummy == 0 )
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315 /* This file calls prvTaskExitError() after the scheduler has been
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316 * started to remove a compiler warning about the function being
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317 * defined but never called. ulDummy is used purely to quieten other
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318 * warnings about code appearing after this function is called - making
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319 * ulDummy volatile makes the compiler think the function could return
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320 * and therefore not output an 'unreachable code' warning for code that
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321 * appears after it. */
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324 /*-----------------------------------------------------------*/
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326 #if( configENABLE_MPU == 1 )
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327 static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
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329 #if defined( __ARMCC_VERSION )
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330 /* Declaration when these variable are defined in code instead of being
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331 * exported from linker scripts. */
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332 extern uint32_t * __privileged_functions_start__;
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333 extern uint32_t * __privileged_functions_end__;
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334 extern uint32_t * __syscalls_flash_start__;
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335 extern uint32_t * __unprivileged_flash_end__;
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336 extern uint32_t * __privileged_sram_start__;
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337 extern uint32_t * __privileged_sram_end__;
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339 /* Declaration when these variable are exported from linker scripts. */
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340 extern uint32_t __privileged_functions_start__[];
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341 extern uint32_t __privileged_functions_end__[];
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342 extern uint32_t __syscalls_flash_start__[];
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343 extern uint32_t __unprivileged_flash_end__[];
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344 extern uint32_t __privileged_sram_start__[];
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345 extern uint32_t __privileged_sram_end__[];
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346 #endif /* defined( __ARMCC_VERSION ) */
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348 /* Check that the MPU is present. */
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349 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
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351 /* MAIR0 - Index 0. */
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352 portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
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353 /* MAIR0 - Index 1. */
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354 portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
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356 /* Setup privileged flash as Read Only so that privileged tasks can
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357 * read it but not modify. */
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358 portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
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359 portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
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360 ( portMPU_REGION_NON_SHAREABLE ) |
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361 ( portMPU_REGION_PRIVILEGED_READ_ONLY );
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362 portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
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363 ( portMPU_RLAR_ATTR_INDEX0 ) |
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364 ( portMPU_RLAR_REGION_ENABLE );
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366 /* Setup unprivileged flash and system calls flash as Read Only by
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367 * both privileged and unprivileged tasks. All tasks can read it but
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368 * no-one can modify. */
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369 portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
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370 portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
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371 ( portMPU_REGION_NON_SHAREABLE ) |
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372 ( portMPU_REGION_READ_ONLY );
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373 portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
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374 ( portMPU_RLAR_ATTR_INDEX0 ) |
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375 ( portMPU_RLAR_REGION_ENABLE );
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377 /* Setup RAM containing kernel data for privileged access only. */
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378 portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
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379 portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
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380 ( portMPU_REGION_NON_SHAREABLE ) |
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381 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
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382 ( portMPU_REGION_EXECUTE_NEVER );
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383 portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
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384 ( portMPU_RLAR_ATTR_INDEX0 ) |
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385 ( portMPU_RLAR_REGION_ENABLE );
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387 /* By default allow everything to access the general peripherals.
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388 * The system peripherals and registers are protected. */
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389 portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;
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390 portMPU_RBAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |
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391 ( portMPU_REGION_NON_SHAREABLE ) |
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392 ( portMPU_REGION_READ_WRITE ) |
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393 ( portMPU_REGION_EXECUTE_NEVER );
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394 portMPU_RLAR_REG = ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |
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395 ( portMPU_RLAR_ATTR_INDEX1 ) |
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396 ( portMPU_RLAR_REGION_ENABLE );
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398 /* Enable mem fault. */
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399 portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
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401 /* Enable MPU with privileged background access i.e. unmapped
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402 * regions have privileged access. */
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403 portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
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406 #endif /* configENABLE_MPU */
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407 /*-----------------------------------------------------------*/
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409 #if( configENABLE_FPU == 1 )
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410 static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
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412 #if( configENABLE_TRUSTZONE == 1 )
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414 /* Enable non-secure access to the FPU. */
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415 SecureInit_EnableNSFPUAccess();
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417 #endif /* configENABLE_TRUSTZONE */
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419 /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
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420 * unprivileged code should be able to access FPU. CP11 should be
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421 * programmed to the same value as CP10. */
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422 *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
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423 ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
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426 /* ASPEN = 1 ==> Hardware should automatically preserve floating point
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427 * context on exception entry and restore on exception return.
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428 * LSPEN = 1 ==> Enable lazy context save of FP state. */
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429 *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
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431 #endif /* configENABLE_FPU */
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432 /*-----------------------------------------------------------*/
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434 void vPortYield( void ) /* PRIVILEGED_FUNCTION */
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436 /* Set a PendSV to request a context switch. */
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437 *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
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439 /* Barriers are normally not required but do ensure the code is
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440 * completely within the specified behaviour for the architecture. */
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441 __asm volatile( "dsb" ::: "memory" );
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442 __asm volatile( "isb" );
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444 /*-----------------------------------------------------------*/
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446 void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
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448 portDISABLE_INTERRUPTS();
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449 ulCriticalNesting++;
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451 /* Barriers are normally not required but do ensure the code is
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452 * completely within the specified behaviour for the architecture. */
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453 __asm volatile( "dsb" ::: "memory" );
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454 __asm volatile( "isb" );
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456 /*-----------------------------------------------------------*/
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458 void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
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460 configASSERT( ulCriticalNesting );
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461 ulCriticalNesting--;
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463 if( ulCriticalNesting == 0 )
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465 portENABLE_INTERRUPTS();
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468 /*-----------------------------------------------------------*/
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470 void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
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472 uint32_t ulPreviousMask;
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474 ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
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476 /* Increment the RTOS tick. */
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477 if( xTaskIncrementTick() != pdFALSE )
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479 /* Pend a context switch. */
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480 *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
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483 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
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485 /*-----------------------------------------------------------*/
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487 void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */
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489 #if( configENABLE_MPU == 1 )
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490 #if defined( __ARMCC_VERSION )
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491 /* Declaration when these variable are defined in code instead of being
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492 * exported from linker scripts. */
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493 extern uint32_t * __syscalls_flash_start__;
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494 extern uint32_t * __syscalls_flash_end__;
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496 /* Declaration when these variable are exported from linker scripts. */
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497 extern uint32_t __syscalls_flash_start__[];
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498 extern uint32_t __syscalls_flash_end__[];
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499 #endif /* defined( __ARMCC_VERSION ) */
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500 #endif /* configENABLE_MPU */
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504 #if( configENABLE_TRUSTZONE == 1 )
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506 #if( configENABLE_MPU == 1 )
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507 uint32_t ulControl, ulIsTaskPrivileged;
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508 #endif /* configENABLE_MPU */
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509 #endif /* configENABLE_TRUSTZONE */
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510 uint8_t ucSVCNumber;
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512 /* Register are stored on the stack in the following order - R0, R1, R2, R3,
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513 * R12, LR, PC, xPSR. */
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514 ulPC = pulCallerStackAddress[ 6 ];
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515 ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
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517 switch( ucSVCNumber )
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519 #if( configENABLE_TRUSTZONE == 1 )
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520 case portSVC_ALLOCATE_SECURE_CONTEXT:
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522 /* R0 contains the stack size passed as parameter to the
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523 * vPortAllocateSecureContext function. */
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524 ulR0 = pulCallerStackAddress[ 0 ];
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526 #if( configENABLE_MPU == 1 )
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528 /* Read the CONTROL register value. */
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529 __asm volatile ( "mrs %0, control" : "=r" ( ulControl ) );
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531 /* The task that raised the SVC is privileged if Bit[0]
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532 * in the CONTROL register is 0. */
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533 ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
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535 /* Allocate and load a context for the secure task. */
\r
536 xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
\r
540 /* Allocate and load a context for the secure task. */
\r
541 xSecureContext = SecureContext_AllocateContext( ulR0 );
\r
543 #endif /* configENABLE_MPU */
\r
545 configASSERT( xSecureContext != NULL );
\r
546 SecureContext_LoadContext( xSecureContext );
\r
550 case portSVC_FREE_SECURE_CONTEXT:
\r
552 /* R0 contains the secure context handle to be freed. */
\r
553 ulR0 = pulCallerStackAddress[ 0 ];
\r
555 /* Free the secure context. */
\r
556 SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
\r
559 #endif /* configENABLE_TRUSTZONE */
\r
561 case portSVC_START_SCHEDULER:
\r
563 #if( configENABLE_TRUSTZONE == 1 )
\r
565 /* De-prioritize the non-secure exceptions so that the
\r
566 * non-secure pendSV runs at the lowest priority. */
\r
567 SecureInit_DePrioritizeNSExceptions();
\r
569 /* Initialize the secure context management system. */
\r
570 SecureContext_Init();
\r
572 #endif /* configENABLE_TRUSTZONE */
\r
574 #if( configENABLE_FPU == 1 )
\r
576 /* Setup the Floating Point Unit (FPU). */
\r
579 #endif /* configENABLE_FPU */
\r
581 /* Setup the context of the first task so that the first task starts
\r
583 vRestoreContextOfFirstTask();
\r
587 #if( configENABLE_MPU == 1 )
\r
588 case portSVC_RAISE_PRIVILEGE:
\r
590 /* Only raise the privilege, if the svc was raised from any of
\r
591 * the system calls. */
\r
592 if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
\r
593 ulPC <= ( uint32_t ) __syscalls_flash_end__ )
\r
599 #endif /* configENABLE_MPU */
\r
603 /* Incorrect SVC call. */
\r
604 configASSERT( pdFALSE );
\r
608 /*-----------------------------------------------------------*/
\r
610 #if( configENABLE_MPU == 1 )
\r
611 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
\r
613 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
\r
614 #endif /* configENABLE_MPU */
\r
616 /* Simulate the stack frame as it would be created by a context switch
\r
618 #if( portPRELOAD_REGISTERS == 0 )
\r
620 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
\r
621 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
\r
623 *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
\r
625 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
\r
626 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
\r
627 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
\r
628 pxTopOfStack -= 9; /* R11..R4, EXC_RETURN. */
\r
629 *pxTopOfStack = portINITIAL_EXC_RETURN;
\r
631 #if( configENABLE_MPU == 1 )
\r
634 if( xRunPrivileged == pdTRUE )
\r
636 *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
\r
640 *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
\r
643 #endif /* configENABLE_MPU */
\r
646 *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
\r
648 #if( configENABLE_TRUSTZONE == 1 )
\r
651 *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
\r
653 #endif /* configENABLE_TRUSTZONE */
\r
655 #else /* portPRELOAD_REGISTERS */
\r
657 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
\r
658 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
\r
660 *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
\r
662 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
\r
664 *pxTopOfStack = ( StackType_t ) 0x12121212UL; /* R12 */
\r
666 *pxTopOfStack = ( StackType_t ) 0x03030303UL; /* R3 */
\r
668 *pxTopOfStack = ( StackType_t ) 0x02020202UL; /* R2 */
\r
670 *pxTopOfStack = ( StackType_t ) 0x01010101UL; /* R1 */
\r
672 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
\r
674 *pxTopOfStack = ( StackType_t ) 0x11111111UL; /* R11 */
\r
676 *pxTopOfStack = ( StackType_t ) 0x10101010UL; /* R10 */
\r
678 *pxTopOfStack = ( StackType_t ) 0x09090909UL; /* R09 */
\r
680 *pxTopOfStack = ( StackType_t ) 0x08080808UL; /* R08 */
\r
682 *pxTopOfStack = ( StackType_t ) 0x07070707UL; /* R07 */
\r
684 *pxTopOfStack = ( StackType_t ) 0x06060606UL; /* R06 */
\r
686 *pxTopOfStack = ( StackType_t ) 0x05050505UL; /* R05 */
\r
688 *pxTopOfStack = ( StackType_t ) 0x04040404UL; /* R04 */
\r
690 *pxTopOfStack = portINITIAL_EXC_RETURN; /* EXC_RETURN */
\r
692 #if( configENABLE_MPU == 1 )
\r
695 if( xRunPrivileged == pdTRUE )
\r
697 *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
\r
701 *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
\r
704 #endif /* configENABLE_MPU */
\r
707 *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
\r
709 #if( configENABLE_TRUSTZONE == 1 )
\r
712 *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
\r
714 #endif /* configENABLE_TRUSTZONE */
\r
716 #endif /* portPRELOAD_REGISTERS */
\r
718 return pxTopOfStack;
\r
720 /*-----------------------------------------------------------*/
\r
722 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
\r
724 /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
\r
725 *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
\r
726 *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
\r
728 #if( configENABLE_MPU == 1 )
\r
730 /* Setup the Memory Protection Unit (MPU). */
\r
733 #endif /* configENABLE_MPU */
\r
735 /* Start the timer that generates the tick ISR. Interrupts are disabled
\r
737 prvSetupTimerInterrupt();
\r
739 /* Initialize the critical nesting count ready for the first task. */
\r
740 ulCriticalNesting = 0;
\r
742 /* Start the first task. */
\r
745 /* Should never get here as the tasks will now be executing. Call the task
\r
746 * exit error function to prevent compiler warnings about a static function
\r
747 * not being called in the case that the application writer overrides this
\r
748 * functionality by defining configTASK_RETURN_ADDRESS. Call
\r
749 * vTaskSwitchContext() so link time optimization does not remove the
\r
751 vTaskSwitchContext();
\r
752 prvTaskExitError();
\r
754 /* Should not get here. */
\r
757 /*-----------------------------------------------------------*/
\r
759 void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
\r
761 /* Not implemented in ports where there is nothing to return to.
\r
762 * Artificially force an assert. */
\r
763 configASSERT( ulCriticalNesting == 1000UL );
\r
765 /*-----------------------------------------------------------*/
\r
767 #if( configENABLE_MPU == 1 )
\r
768 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
\r
770 uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
\r
771 int32_t lIndex = 0;
\r
774 xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
\r
775 xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
\r
777 /* This function is called automatically when the task is created - in
\r
778 * which case the stack region parameters will be valid. At all other
\r
779 * times the stack parameters will not be valid and it is assumed that
\r
780 * the stack region has already been configured. */
\r
781 if( ulStackDepth > 0 )
\r
783 /* Define the region that allows access to the stack. */
\r
784 ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
\r
785 ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
\r
786 ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
\r
788 xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
\r
789 ( portMPU_REGION_NON_SHAREABLE ) |
\r
790 ( portMPU_REGION_READ_WRITE ) |
\r
791 ( portMPU_REGION_EXECUTE_NEVER );
\r
793 xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
\r
794 ( portMPU_RLAR_ATTR_INDEX0 ) |
\r
795 ( portMPU_RLAR_REGION_ENABLE );
\r
798 /* User supplied configurable regions. */
\r
799 for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
\r
801 /* If xRegions is NULL i.e. the task has not specified any MPU
\r
802 * region, the else part ensures that all the configurable MPU
\r
803 * regions are invalidated. */
\r
804 if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
\r
806 /* Translate the generic region definition contained in xRegions
\r
807 * into the ARMv8 specific MPU settings that are then stored in
\r
809 ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
\r
810 ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
\r
811 ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
\r
813 /* Start address. */
\r
814 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
\r
815 ( portMPU_REGION_NON_SHAREABLE );
\r
818 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
\r
820 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
\r
824 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
\r
828 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
\r
830 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
\r
834 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
\r
835 ( portMPU_RLAR_REGION_ENABLE );
\r
837 /* Normal memory/ Device memory. */
\r
838 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
\r
840 /* Attr1 in MAIR0 is configured as device memory. */
\r
841 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
\r
845 /* Attr1 in MAIR0 is configured as normal memory. */
\r
846 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
\r
851 /* Invalidate the region. */
\r
852 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
\r
853 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
\r
859 #endif /* configENABLE_MPU */
\r
860 /*-----------------------------------------------------------*/
\r