1 /*This file has been prepared for Doxygen automatic documentation generation.*/
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2 /*! \file *********************************************************************
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4 * \brief FreeRTOS port source for AVR32 UC3.
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6 * - Compiler: IAR EWAVR32
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7 * - Supported devices: All AVR32 devices can be used.
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10 * \author Atmel Corporation: http://www.atmel.com \n
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11 * Support and FAQ: http://support.atmel.no/
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13 *****************************************************************************/
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16 FreeRTOS V7.5.1 - Copyright (C) 2013 Real Time Engineers Ltd.
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18 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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20 ***************************************************************************
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22 * FreeRTOS provides completely free yet professionally developed, *
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23 * robust, strictly quality controlled, supported, and cross *
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24 * platform software that has become a de facto standard. *
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26 * Help yourself get started quickly and support the FreeRTOS *
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27 * project by purchasing a FreeRTOS tutorial book, reference *
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28 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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32 ***************************************************************************
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34 This file is part of the FreeRTOS distribution.
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36 FreeRTOS is free software; you can redistribute it and/or modify it under
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37 the terms of the GNU General Public License (version 2) as published by the
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38 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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40 >>! NOTE: The modification to the GPL is included to allow you to distribute
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41 >>! a combined work that includes FreeRTOS without being obliged to provide
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42 >>! the source code for proprietary components outside of the FreeRTOS
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45 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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46 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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47 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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48 link: http://www.freertos.org/a00114.html
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52 ***************************************************************************
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54 * Having a problem? Start by reading the FAQ "My application does *
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55 * not run, what could be wrong?" *
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57 * http://www.FreeRTOS.org/FAQHelp.html *
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59 ***************************************************************************
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61 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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62 license and Real Time Engineers Ltd. contact details.
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64 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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65 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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66 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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68 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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69 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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70 licenses offer ticketed support, indemnification and middleware.
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72 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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73 engineered and independently SIL3 certified version for use in safety and
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74 mission critical applications that require provable dependability.
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80 /* Scheduler includes. */
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81 #include "FreeRTOS.h"
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84 /* AVR32 UC3 includes. */
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85 #include <avr32/io.h>
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86 #include <intrinsics.h>
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93 #if( configTICK_USE_TC==1 )
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98 /* Constants required to setup the task context. */
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99 #define portINITIAL_SR ( ( portSTACK_TYPE ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
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100 #define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 0 )
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102 /* Each task maintains its own critical nesting variable. */
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103 #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
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104 volatile unsigned long ulCriticalNesting = 9999UL;
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106 #if( configTICK_USE_TC==0 )
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107 static void prvScheduleNextTick( void );
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109 static void prvClearTcInt( void );
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112 /* Setup the timer to generate the tick interrupts. */
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113 static void prvSetupTimerInterrupt( void );
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115 /*-----------------------------------------------------------*/
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118 * Low-level initialization routine called during startup, before the main
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121 int __low_level_init(void)
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123 #if configHEAP_INIT
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124 #pragma segment = "HEAP"
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125 portBASE_TYPE *pxMem;
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128 /* Enable exceptions. */
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129 ENABLE_ALL_EXCEPTIONS();
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131 /* Initialize interrupt handling. */
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132 INTC_init_interrupts();
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134 #if configHEAP_INIT
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136 /* Initialize the heap used by malloc. */
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137 for( pxMem = __segment_begin( "HEAP" ); pxMem < ( portBASE_TYPE * ) __segment_end( "HEAP" ); )
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139 *pxMem++ = 0xA5A5A5A5;
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144 /* Code section present if and only if the debug trace is activated. */
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147 static const gpio_map_t DBG_USART_GPIO_MAP =
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149 { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
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150 { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
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153 static const usart_options_t DBG_USART_OPTIONS =
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155 .baudrate = configDBG_USART_BAUDRATE,
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157 .paritytype = USART_NO_PARITY,
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158 .stopbits = USART_1_STOPBIT,
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159 .channelmode = USART_NORMAL_CHMODE
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162 /* Initialize the USART used for the debug trace with the configured parameters. */
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163 extern volatile avr32_usart_t *volatile stdio_usart_base;
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164 stdio_usart_base = configDBG_USART;
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165 gpio_enable_module( DBG_USART_GPIO_MAP,
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166 sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
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167 usart_init_rs232(configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ);
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171 /* Request initialization of data segments. */
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174 /*-----------------------------------------------------------*/
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176 /* Added as there is no such function in FreeRTOS. */
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177 void *pvPortRealloc( void *pv, size_t xWantedSize )
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183 pvReturn = realloc( pv, xWantedSize );
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189 /*-----------------------------------------------------------*/
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191 /* The cooperative scheduler requires a normal IRQ service routine to
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192 simply increment the system tick. */
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193 /* The preemptive scheduler is defined as "naked" as the full context is saved
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194 on entry as part of the context switch. */
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195 #pragma shadow_registers = full // Naked.
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196 static void vTick( void )
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198 /* Save the context of the interrupted task. */
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199 portSAVE_CONTEXT_OS_INT();
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201 #if( configTICK_USE_TC==1 )
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202 /* Clear the interrupt flag. */
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205 /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
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206 clock cycles from now. */
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207 prvScheduleNextTick();
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210 /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
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211 calls in a critical section . */
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212 portENTER_CRITICAL();
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213 xTaskIncrementTick();
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214 portEXIT_CRITICAL();
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216 /* Restore the context of the "elected task". */
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217 portRESTORE_CONTEXT_OS_INT();
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219 /*-----------------------------------------------------------*/
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221 #pragma shadow_registers = full // Naked.
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222 void SCALLYield( void )
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224 /* Save the context of the interrupted task. */
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225 portSAVE_CONTEXT_SCALL();
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226 vTaskSwitchContext();
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227 portRESTORE_CONTEXT_SCALL();
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229 /*-----------------------------------------------------------*/
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231 /* The code generated by the GCC compiler uses the stack in different ways at
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232 different optimisation levels. The interrupt flags can therefore not always
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233 be saved to the stack. Instead the critical section nesting level is stored
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234 in a variable, which is then saved as part of the stack context. */
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235 #pragma optimize = no_inline
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236 void vPortEnterCritical( void )
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238 /* Disable interrupts */
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239 portDISABLE_INTERRUPTS();
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241 /* Now interrupts are disabled ulCriticalNesting can be accessed
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242 directly. Increment ulCriticalNesting to keep a count of how many times
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243 portENTER_CRITICAL() has been called. */
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244 ulCriticalNesting++;
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246 /*-----------------------------------------------------------*/
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248 #pragma optimize = no_inline
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249 void vPortExitCritical( void )
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251 if(ulCriticalNesting > portNO_CRITICAL_NESTING)
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253 ulCriticalNesting--;
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254 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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256 /* Enable all interrupt/exception. */
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257 portENABLE_INTERRUPTS();
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261 /*-----------------------------------------------------------*/
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264 * Initialise the stack of a task to look exactly as if a call to
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265 * portSAVE_CONTEXT had been called.
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267 * See header file for description.
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269 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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271 /* Setup the initial stack of the task. The stack is set exactly as
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272 expected by the portRESTORE_CONTEXT() macro. */
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274 /* When the task starts, it will expect to find the function parameter in R12. */
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276 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x08080808; /* R8 */
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277 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x09090909; /* R9 */
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278 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x0A0A0A0A; /* R10 */
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279 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x0B0B0B0B; /* R11 */
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280 *pxTopOfStack-- = ( portSTACK_TYPE ) pvParameters; /* R12 */
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281 *pxTopOfStack-- = ( portSTACK_TYPE ) 0xDEADBEEF; /* R14/LR */
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282 *pxTopOfStack-- = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
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283 *pxTopOfStack-- = ( portSTACK_TYPE ) portINITIAL_SR; /* SR */
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284 *pxTopOfStack-- = ( portSTACK_TYPE ) 0xFF0000FF; /* R0 */
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285 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x01010101; /* R1 */
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286 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x02020202; /* R2 */
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287 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x03030303; /* R3 */
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288 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x04040404; /* R4 */
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289 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x05050505; /* R5 */
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290 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x06060606; /* R6 */
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291 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x07070707; /* R7 */
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292 *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */
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294 return pxTopOfStack;
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296 /*-----------------------------------------------------------*/
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298 portBASE_TYPE xPortStartScheduler( void )
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300 /* Start the timer that generates the tick ISR. Interrupts are disabled
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302 prvSetupTimerInterrupt();
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304 /* Start the first task. */
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305 portRESTORE_CONTEXT();
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307 /* Should not get here! */
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310 /*-----------------------------------------------------------*/
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312 void vPortEndScheduler( void )
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314 /* It is unlikely that the AVR32 port will require this function as there
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315 is nothing to return to. */
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317 /*-----------------------------------------------------------*/
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319 /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
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320 clock cycles from now. */
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321 #if( configTICK_USE_TC==0 )
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322 static void prvScheduleFirstTick(void)
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324 unsigned long lCycles;
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326 lCycles = Get_system_register(AVR32_COUNT);
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327 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
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328 // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
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329 // generation feature does not get disabled.
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334 Set_system_register(AVR32_COMPARE, lCycles);
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337 #pragma optimize = no_inline
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338 static void prvScheduleNextTick(void)
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340 unsigned long lCycles, lCount;
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342 lCycles = Get_system_register(AVR32_COMPARE);
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343 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
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344 // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
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345 // generation feature does not get disabled.
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350 lCount = Get_system_register(AVR32_COUNT);
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351 if( lCycles < lCount )
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352 { // We missed a tick, recover for the next.
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353 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
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355 Set_system_register(AVR32_COMPARE, lCycles);
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358 #pragma optimize = no_inline
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359 static void prvClearTcInt(void)
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361 AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
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364 /*-----------------------------------------------------------*/
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366 /* Setup the timer to generate the tick interrupts. */
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367 static void prvSetupTimerInterrupt(void)
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369 #if( configTICK_USE_TC==1 )
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371 volatile avr32_tc_t *tc = &AVR32_TC;
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373 // Options for waveform genration.
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374 tc_waveform_opt_t waveform_opt =
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376 .channel = configTICK_TC_CHANNEL, /* Channel selection. */
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378 .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */
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379 .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */
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380 .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */
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381 .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */
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383 .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */
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384 .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */
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385 .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */
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386 .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
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388 .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
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389 .enetrg = FALSE, /* External event trigger enable. */
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390 .eevt = 0, /* External event selection. */
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391 .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */
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392 .cpcdis = FALSE, /* Counter disable when RC compare. */
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393 .cpcstop = FALSE, /* Counter clock stopped with RC compare. */
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395 .burst = FALSE, /* Burst signal selection. */
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396 .clki = FALSE, /* Clock inversion. */
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397 .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */
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400 tc_interrupt_t tc_interrupt =
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414 /* Disable all interrupt/exception. */
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415 portDISABLE_INTERRUPTS();
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417 /* Register the compare interrupt handler to the interrupt controller and
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418 enable the compare interrupt. */
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420 #if( configTICK_USE_TC==1 )
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422 INTC_register_interrupt((__int_handler)&vTick, configTICK_TC_IRQ, INT0);
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424 /* Initialize the timer/counter. */
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425 tc_init_waveform(tc, &waveform_opt);
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427 /* Set the compare triggers.
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428 Remember TC counter is 16-bits, so counting second is not possible!
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429 That's why we configure it to count ms. */
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430 tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
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432 tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
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434 /* Start the timer/counter. */
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435 tc_start(tc, configTICK_TC_CHANNEL);
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439 INTC_register_interrupt((__int_handler)&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
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440 prvScheduleFirstTick();
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