1 /*This file has been prepared for Doxygen automatic documentation generation.*/
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2 /*! \file *********************************************************************
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4 * \brief FreeRTOS port source for AVR32 UC3.
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6 * - Compiler: IAR EWAVR32
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7 * - Supported devices: All AVR32 devices can be used.
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10 * \author Atmel Corporation: http://www.atmel.com \n
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11 * Support and FAQ: http://support.atmel.no/
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13 *****************************************************************************/
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16 FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.
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19 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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21 This file is part of the FreeRTOS distribution.
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23 FreeRTOS is free software; you can redistribute it and/or modify it under
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24 the terms of the GNU General Public License (version 2) as published by the
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25 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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27 >>! NOTE: The modification to the GPL is included to allow you to !<<
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28 >>! distribute a combined work that includes FreeRTOS without being !<<
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29 >>! obliged to provide the source code for proprietary components !<<
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30 >>! outside of the FreeRTOS kernel. !<<
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32 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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33 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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34 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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35 link: http://www.freertos.org/a00114.html
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39 ***************************************************************************
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41 * Having a problem? Start by reading the FAQ "My application does *
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42 * not run, what could be wrong?". Have you defined configASSERT()? *
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44 * http://www.FreeRTOS.org/FAQHelp.html *
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46 ***************************************************************************
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48 ***************************************************************************
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50 * FreeRTOS provides completely free yet professionally developed, *
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51 * robust, strictly quality controlled, supported, and cross *
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52 * platform software that is more than just the market leader, it *
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53 * is the industry's de facto standard. *
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55 * Help yourself get started quickly while simultaneously helping *
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56 * to support the FreeRTOS project by purchasing a FreeRTOS *
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57 * tutorial book, reference manual, or both: *
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58 * http://www.FreeRTOS.org/Documentation *
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60 ***************************************************************************
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62 ***************************************************************************
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64 * Investing in training allows your team to be as productive as *
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65 * possible as early as possible, lowering your overall development *
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66 * cost, and enabling you to bring a more robust product to market *
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67 * earlier than would otherwise be possible. Richard Barry is both *
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68 * the architect and key author of FreeRTOS, and so also the world's *
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69 * leading authority on what is the world's most popular real time *
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70 * kernel for deeply embedded MCU designs. Obtaining your training *
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71 * from Richard ensures your team will gain directly from his in-depth *
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72 * product knowledge and years of usage experience. Contact Real Time *
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73 * Engineers Ltd to enquire about the FreeRTOS Masterclass, presented *
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74 * by Richard Barry: http://www.FreeRTOS.org/contact
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76 ***************************************************************************
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78 ***************************************************************************
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80 * You are receiving this top quality software for free. Please play *
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81 * fair and reciprocate by reporting any suspected issues and *
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82 * participating in the community forum: *
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83 * http://www.FreeRTOS.org/support *
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87 ***************************************************************************
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89 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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90 license and Real Time Engineers Ltd. contact details.
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92 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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93 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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94 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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96 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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97 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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99 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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100 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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101 licenses offer ticketed support, indemnification and commercial middleware.
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103 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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104 engineered and independently SIL3 certified version for use in safety and
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105 mission critical applications that require provable dependability.
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111 /* Scheduler includes. */
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112 #include "FreeRTOS.h"
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115 /* AVR32 UC3 includes. */
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116 #include <avr32/io.h>
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117 #include <intrinsics.h>
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124 #if( configTICK_USE_TC==1 )
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129 /* Constants required to setup the task context. */
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130 #define portINITIAL_SR ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
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131 #define portINSTRUCTION_SIZE ( ( StackType_t ) 0 )
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133 /* Each task maintains its own critical nesting variable. */
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134 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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135 volatile uint32_t ulCriticalNesting = 9999UL;
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137 #if( configTICK_USE_TC==0 )
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138 static void prvScheduleNextTick( void );
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140 static void prvClearTcInt( void );
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143 /* Setup the timer to generate the tick interrupts. */
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144 static void prvSetupTimerInterrupt( void );
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146 /*-----------------------------------------------------------*/
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149 * Low-level initialization routine called during startup, before the main
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152 int __low_level_init(void)
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154 #if configHEAP_INIT
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155 #pragma segment = "HEAP"
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159 /* Enable exceptions. */
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160 ENABLE_ALL_EXCEPTIONS();
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162 /* Initialize interrupt handling. */
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163 INTC_init_interrupts();
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165 #if configHEAP_INIT
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167 /* Initialize the heap used by malloc. */
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168 for( pxMem = __segment_begin( "HEAP" ); pxMem < ( BaseType_t * ) __segment_end( "HEAP" ); )
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170 *pxMem++ = 0xA5A5A5A5;
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175 /* Code section present if and only if the debug trace is activated. */
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178 static const gpio_map_t DBG_USART_GPIO_MAP =
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180 { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
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181 { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
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184 static const usart_options_t DBG_USART_OPTIONS =
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186 .baudrate = configDBG_USART_BAUDRATE,
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188 .paritytype = USART_NO_PARITY,
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189 .stopbits = USART_1_STOPBIT,
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190 .channelmode = USART_NORMAL_CHMODE
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193 /* Initialize the USART used for the debug trace with the configured parameters. */
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194 extern volatile avr32_usart_t *volatile stdio_usart_base;
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195 stdio_usart_base = configDBG_USART;
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196 gpio_enable_module( DBG_USART_GPIO_MAP,
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197 sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
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198 usart_init_rs232(configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ);
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202 /* Request initialization of data segments. */
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205 /*-----------------------------------------------------------*/
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207 /* Added as there is no such function in FreeRTOS. */
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208 void *pvPortRealloc( void *pv, size_t xWantedSize )
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214 pvReturn = realloc( pv, xWantedSize );
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220 /*-----------------------------------------------------------*/
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222 /* The cooperative scheduler requires a normal IRQ service routine to
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223 simply increment the system tick. */
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224 /* The preemptive scheduler is defined as "naked" as the full context is saved
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225 on entry as part of the context switch. */
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226 #pragma shadow_registers = full // Naked.
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227 static void vTick( void )
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229 /* Save the context of the interrupted task. */
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230 portSAVE_CONTEXT_OS_INT();
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232 #if( configTICK_USE_TC==1 )
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233 /* Clear the interrupt flag. */
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236 /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
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237 clock cycles from now. */
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238 prvScheduleNextTick();
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241 /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
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242 calls in a critical section . */
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243 portENTER_CRITICAL();
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244 xTaskIncrementTick();
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245 portEXIT_CRITICAL();
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247 /* Restore the context of the "elected task". */
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248 portRESTORE_CONTEXT_OS_INT();
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250 /*-----------------------------------------------------------*/
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252 #pragma shadow_registers = full // Naked.
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253 void SCALLYield( void )
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255 /* Save the context of the interrupted task. */
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256 portSAVE_CONTEXT_SCALL();
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257 vTaskSwitchContext();
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258 portRESTORE_CONTEXT_SCALL();
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260 /*-----------------------------------------------------------*/
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262 /* The code generated by the GCC compiler uses the stack in different ways at
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263 different optimisation levels. The interrupt flags can therefore not always
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264 be saved to the stack. Instead the critical section nesting level is stored
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265 in a variable, which is then saved as part of the stack context. */
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266 #pragma optimize = no_inline
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267 void vPortEnterCritical( void )
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269 /* Disable interrupts */
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270 portDISABLE_INTERRUPTS();
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272 /* Now interrupts are disabled ulCriticalNesting can be accessed
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273 directly. Increment ulCriticalNesting to keep a count of how many times
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274 portENTER_CRITICAL() has been called. */
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275 ulCriticalNesting++;
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277 /*-----------------------------------------------------------*/
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279 #pragma optimize = no_inline
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280 void vPortExitCritical( void )
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282 if(ulCriticalNesting > portNO_CRITICAL_NESTING)
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284 ulCriticalNesting--;
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285 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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287 /* Enable all interrupt/exception. */
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288 portENABLE_INTERRUPTS();
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292 /*-----------------------------------------------------------*/
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295 * Initialise the stack of a task to look exactly as if a call to
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296 * portSAVE_CONTEXT had been called.
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298 * See header file for description.
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300 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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302 /* Setup the initial stack of the task. The stack is set exactly as
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303 expected by the portRESTORE_CONTEXT() macro. */
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305 /* When the task starts, it will expect to find the function parameter in R12. */
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307 *pxTopOfStack-- = ( StackType_t ) 0x08080808; /* R8 */
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308 *pxTopOfStack-- = ( StackType_t ) 0x09090909; /* R9 */
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309 *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A; /* R10 */
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310 *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B; /* R11 */
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311 *pxTopOfStack-- = ( StackType_t ) pvParameters; /* R12 */
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312 *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF; /* R14/LR */
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313 *pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
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314 *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR; /* SR */
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315 *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF; /* R0 */
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316 *pxTopOfStack-- = ( StackType_t ) 0x01010101; /* R1 */
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317 *pxTopOfStack-- = ( StackType_t ) 0x02020202; /* R2 */
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318 *pxTopOfStack-- = ( StackType_t ) 0x03030303; /* R3 */
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319 *pxTopOfStack-- = ( StackType_t ) 0x04040404; /* R4 */
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320 *pxTopOfStack-- = ( StackType_t ) 0x05050505; /* R5 */
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321 *pxTopOfStack-- = ( StackType_t ) 0x06060606; /* R6 */
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322 *pxTopOfStack-- = ( StackType_t ) 0x07070707; /* R7 */
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323 *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */
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325 return pxTopOfStack;
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327 /*-----------------------------------------------------------*/
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329 BaseType_t xPortStartScheduler( void )
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331 /* Start the timer that generates the tick ISR. Interrupts are disabled
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333 prvSetupTimerInterrupt();
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335 /* Start the first task. */
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336 portRESTORE_CONTEXT();
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338 /* Should not get here! */
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341 /*-----------------------------------------------------------*/
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343 void vPortEndScheduler( void )
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345 /* It is unlikely that the AVR32 port will require this function as there
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346 is nothing to return to. */
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348 /*-----------------------------------------------------------*/
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350 /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
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351 clock cycles from now. */
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352 #if( configTICK_USE_TC==0 )
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353 static void prvScheduleFirstTick(void)
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357 lCycles = Get_system_register(AVR32_COUNT);
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358 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
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359 // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
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360 // generation feature does not get disabled.
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365 Set_system_register(AVR32_COMPARE, lCycles);
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368 #pragma optimize = no_inline
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369 static void prvScheduleNextTick(void)
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371 uint32_t lCycles, lCount;
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373 lCycles = Get_system_register(AVR32_COMPARE);
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374 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
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375 // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
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376 // generation feature does not get disabled.
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381 lCount = Get_system_register(AVR32_COUNT);
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382 if( lCycles < lCount )
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383 { // We missed a tick, recover for the next.
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384 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
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386 Set_system_register(AVR32_COMPARE, lCycles);
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389 #pragma optimize = no_inline
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390 static void prvClearTcInt(void)
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392 AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
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395 /*-----------------------------------------------------------*/
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397 /* Setup the timer to generate the tick interrupts. */
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398 static void prvSetupTimerInterrupt(void)
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400 #if( configTICK_USE_TC==1 )
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402 volatile avr32_tc_t *tc = &AVR32_TC;
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404 // Options for waveform genration.
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405 tc_waveform_opt_t waveform_opt =
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407 .channel = configTICK_TC_CHANNEL, /* Channel selection. */
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409 .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */
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410 .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */
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411 .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */
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412 .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */
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414 .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */
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415 .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */
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416 .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */
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417 .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
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419 .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
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420 .enetrg = FALSE, /* External event trigger enable. */
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421 .eevt = 0, /* External event selection. */
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422 .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */
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423 .cpcdis = FALSE, /* Counter disable when RC compare. */
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424 .cpcstop = FALSE, /* Counter clock stopped with RC compare. */
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426 .burst = FALSE, /* Burst signal selection. */
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427 .clki = FALSE, /* Clock inversion. */
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428 .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */
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431 tc_interrupt_t tc_interrupt =
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445 /* Disable all interrupt/exception. */
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446 portDISABLE_INTERRUPTS();
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448 /* Register the compare interrupt handler to the interrupt controller and
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449 enable the compare interrupt. */
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451 #if( configTICK_USE_TC==1 )
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453 INTC_register_interrupt((__int_handler)&vTick, configTICK_TC_IRQ, INT0);
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455 /* Initialize the timer/counter. */
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456 tc_init_waveform(tc, &waveform_opt);
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458 /* Set the compare triggers.
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459 Remember TC counter is 16-bits, so counting second is not possible!
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460 That's why we configure it to count ms. */
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461 tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
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463 tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
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465 /* Start the timer/counter. */
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466 tc_start(tc, configTICK_TC_CHANNEL);
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470 INTC_register_interrupt((__int_handler)&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
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471 prvScheduleFirstTick();
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