1 /*This file has been prepared for Doxygen automatic documentation generation.*/
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2 /*! \file *********************************************************************
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4 * \brief FreeRTOS port source for AVR32 UC3.
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6 * - Compiler: IAR EWAVR32
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7 * - Supported devices: All AVR32 devices can be used.
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10 * \author Atmel Corporation: http://www.atmel.com \n
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11 * Support and FAQ: http://support.atmel.no/
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13 *****************************************************************************/
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16 FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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18 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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19 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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21 ***************************************************************************
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23 * FreeRTOS tutorial books are available in pdf and paperback. *
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24 * Complete, revised, and edited pdf reference manuals are also *
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27 * Purchasing FreeRTOS documentation will not only help you, by *
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28 * ensuring you get running as quickly as possible and with an *
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29 * in-depth knowledge of how to use FreeRTOS, it will also help *
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30 * the FreeRTOS project to continue with its mission of providing *
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31 * professional grade, cross platform, de facto standard solutions *
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32 * for microcontrollers - completely free of charge! *
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34 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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36 * Thank you for using FreeRTOS, and thank you for your support! *
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38 ***************************************************************************
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41 This file is part of the FreeRTOS distribution.
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43 FreeRTOS is free software; you can redistribute it and/or modify it under
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44 the terms of the GNU General Public License (version 2) as published by the
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45 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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47 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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48 distribute a combined work that includes FreeRTOS without being obliged to
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49 provide the source code for proprietary components outside of the FreeRTOS
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52 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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53 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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54 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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55 details. You should have received a copy of the GNU General Public License
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56 and the FreeRTOS license exception along with FreeRTOS; if not it can be
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57 viewed here: http://www.freertos.org/a00114.html and also obtained by
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58 writing to Real Time Engineers Ltd., contact details for whom are available
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59 on the FreeRTOS WEB site.
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63 ***************************************************************************
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65 * Having a problem? Start by reading the FAQ "My application does *
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66 * not run, what could be wrong?" *
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68 * http://www.FreeRTOS.org/FAQHelp.html *
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70 ***************************************************************************
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73 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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74 license and Real Time Engineers Ltd. contact details.
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76 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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77 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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78 fully thread aware and reentrant UDP/IP stack.
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80 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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81 Integrity Systems, who sell the code with commercial support,
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82 indemnification and middleware, under the OpenRTOS brand.
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84 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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85 engineered and independently SIL3 certified version for use in safety and
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86 mission critical applications that require provable dependability.
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90 /* Scheduler includes. */
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91 #include "FreeRTOS.h"
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94 /* AVR32 UC3 includes. */
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95 #include <avr32/io.h>
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96 #include <intrinsics.h>
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103 #if( configTICK_USE_TC==1 )
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108 /* Constants required to setup the task context. */
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109 #define portINITIAL_SR ( ( portSTACK_TYPE ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
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110 #define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 0 )
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112 /* Each task maintains its own critical nesting variable. */
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113 #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
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114 volatile unsigned long ulCriticalNesting = 9999UL;
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116 #if( configTICK_USE_TC==0 )
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117 static void prvScheduleNextTick( void );
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119 static void prvClearTcInt( void );
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122 /* Setup the timer to generate the tick interrupts. */
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123 static void prvSetupTimerInterrupt( void );
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125 /*-----------------------------------------------------------*/
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128 * Low-level initialization routine called during startup, before the main
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131 int __low_level_init(void)
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133 #if configHEAP_INIT
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134 #pragma segment = "HEAP"
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135 portBASE_TYPE *pxMem;
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138 /* Enable exceptions. */
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139 ENABLE_ALL_EXCEPTIONS();
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141 /* Initialize interrupt handling. */
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142 INTC_init_interrupts();
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144 #if configHEAP_INIT
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146 /* Initialize the heap used by malloc. */
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147 for( pxMem = __segment_begin( "HEAP" ); pxMem < ( portBASE_TYPE * ) __segment_end( "HEAP" ); )
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149 *pxMem++ = 0xA5A5A5A5;
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154 /* Code section present if and only if the debug trace is activated. */
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157 static const gpio_map_t DBG_USART_GPIO_MAP =
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159 { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
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160 { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
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163 static const usart_options_t DBG_USART_OPTIONS =
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165 .baudrate = configDBG_USART_BAUDRATE,
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167 .paritytype = USART_NO_PARITY,
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168 .stopbits = USART_1_STOPBIT,
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169 .channelmode = USART_NORMAL_CHMODE
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172 /* Initialize the USART used for the debug trace with the configured parameters. */
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173 extern volatile avr32_usart_t *volatile stdio_usart_base;
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174 stdio_usart_base = configDBG_USART;
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175 gpio_enable_module( DBG_USART_GPIO_MAP,
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176 sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
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177 usart_init_rs232(configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ);
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181 /* Request initialization of data segments. */
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184 /*-----------------------------------------------------------*/
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186 /* Added as there is no such function in FreeRTOS. */
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187 void *pvPortRealloc( void *pv, size_t xWantedSize )
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193 pvReturn = realloc( pv, xWantedSize );
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199 /*-----------------------------------------------------------*/
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201 /* The cooperative scheduler requires a normal IRQ service routine to
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202 simply increment the system tick. */
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203 /* The preemptive scheduler is defined as "naked" as the full context is saved
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204 on entry as part of the context switch. */
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205 #pragma shadow_registers = full // Naked.
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206 static void vTick( void )
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208 /* Save the context of the interrupted task. */
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209 portSAVE_CONTEXT_OS_INT();
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211 #if( configTICK_USE_TC==1 )
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212 /* Clear the interrupt flag. */
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215 /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
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216 clock cycles from now. */
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217 prvScheduleNextTick();
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220 /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
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221 calls in a critical section . */
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222 portENTER_CRITICAL();
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223 xTaskIncrementTick();
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224 portEXIT_CRITICAL();
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226 /* Restore the context of the "elected task". */
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227 portRESTORE_CONTEXT_OS_INT();
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229 /*-----------------------------------------------------------*/
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231 #pragma shadow_registers = full // Naked.
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232 void SCALLYield( void )
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234 /* Save the context of the interrupted task. */
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235 portSAVE_CONTEXT_SCALL();
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236 vTaskSwitchContext();
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237 portRESTORE_CONTEXT_SCALL();
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239 /*-----------------------------------------------------------*/
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241 /* The code generated by the GCC compiler uses the stack in different ways at
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242 different optimisation levels. The interrupt flags can therefore not always
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243 be saved to the stack. Instead the critical section nesting level is stored
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244 in a variable, which is then saved as part of the stack context. */
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245 #pragma optimize = no_inline
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246 void vPortEnterCritical( void )
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248 /* Disable interrupts */
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249 portDISABLE_INTERRUPTS();
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251 /* Now interrupts are disabled ulCriticalNesting can be accessed
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252 directly. Increment ulCriticalNesting to keep a count of how many times
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253 portENTER_CRITICAL() has been called. */
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254 ulCriticalNesting++;
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256 /*-----------------------------------------------------------*/
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258 #pragma optimize = no_inline
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259 void vPortExitCritical( void )
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261 if(ulCriticalNesting > portNO_CRITICAL_NESTING)
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263 ulCriticalNesting--;
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264 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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266 /* Enable all interrupt/exception. */
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267 portENABLE_INTERRUPTS();
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271 /*-----------------------------------------------------------*/
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274 * Initialise the stack of a task to look exactly as if a call to
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275 * portSAVE_CONTEXT had been called.
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277 * See header file for description.
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279 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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281 /* Setup the initial stack of the task. The stack is set exactly as
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282 expected by the portRESTORE_CONTEXT() macro. */
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284 /* When the task starts, it will expect to find the function parameter in R12. */
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286 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x08080808; /* R8 */
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287 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x09090909; /* R9 */
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288 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x0A0A0A0A; /* R10 */
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289 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x0B0B0B0B; /* R11 */
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290 *pxTopOfStack-- = ( portSTACK_TYPE ) pvParameters; /* R12 */
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291 *pxTopOfStack-- = ( portSTACK_TYPE ) 0xDEADBEEF; /* R14/LR */
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292 *pxTopOfStack-- = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
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293 *pxTopOfStack-- = ( portSTACK_TYPE ) portINITIAL_SR; /* SR */
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294 *pxTopOfStack-- = ( portSTACK_TYPE ) 0xFF0000FF; /* R0 */
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295 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x01010101; /* R1 */
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296 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x02020202; /* R2 */
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297 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x03030303; /* R3 */
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298 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x04040404; /* R4 */
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299 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x05050505; /* R5 */
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300 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x06060606; /* R6 */
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301 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x07070707; /* R7 */
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302 *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */
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304 return pxTopOfStack;
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306 /*-----------------------------------------------------------*/
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308 portBASE_TYPE xPortStartScheduler( void )
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310 /* Start the timer that generates the tick ISR. Interrupts are disabled
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312 prvSetupTimerInterrupt();
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314 /* Start the first task. */
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315 portRESTORE_CONTEXT();
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317 /* Should not get here! */
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320 /*-----------------------------------------------------------*/
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322 void vPortEndScheduler( void )
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324 /* It is unlikely that the AVR32 port will require this function as there
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325 is nothing to return to. */
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327 /*-----------------------------------------------------------*/
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329 /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
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330 clock cycles from now. */
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331 #if( configTICK_USE_TC==0 )
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332 static void prvScheduleFirstTick(void)
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334 unsigned long lCycles;
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336 lCycles = Get_system_register(AVR32_COUNT);
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337 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
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338 // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
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339 // generation feature does not get disabled.
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344 Set_system_register(AVR32_COMPARE, lCycles);
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347 #pragma optimize = no_inline
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348 static void prvScheduleNextTick(void)
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350 unsigned long lCycles, lCount;
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352 lCycles = Get_system_register(AVR32_COMPARE);
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353 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
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354 // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
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355 // generation feature does not get disabled.
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360 lCount = Get_system_register(AVR32_COUNT);
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361 if( lCycles < lCount )
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362 { // We missed a tick, recover for the next.
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363 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
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365 Set_system_register(AVR32_COMPARE, lCycles);
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368 #pragma optimize = no_inline
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369 static void prvClearTcInt(void)
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371 AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
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374 /*-----------------------------------------------------------*/
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376 /* Setup the timer to generate the tick interrupts. */
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377 static void prvSetupTimerInterrupt(void)
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379 #if( configTICK_USE_TC==1 )
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381 volatile avr32_tc_t *tc = &AVR32_TC;
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383 // Options for waveform genration.
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384 tc_waveform_opt_t waveform_opt =
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386 .channel = configTICK_TC_CHANNEL, /* Channel selection. */
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388 .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */
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389 .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */
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390 .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */
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391 .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */
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393 .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */
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394 .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */
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395 .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */
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396 .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
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398 .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
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399 .enetrg = FALSE, /* External event trigger enable. */
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400 .eevt = 0, /* External event selection. */
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401 .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */
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402 .cpcdis = FALSE, /* Counter disable when RC compare. */
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403 .cpcstop = FALSE, /* Counter clock stopped with RC compare. */
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405 .burst = FALSE, /* Burst signal selection. */
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406 .clki = FALSE, /* Clock inversion. */
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407 .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */
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410 tc_interrupt_t tc_interrupt =
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424 /* Disable all interrupt/exception. */
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425 portDISABLE_INTERRUPTS();
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427 /* Register the compare interrupt handler to the interrupt controller and
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428 enable the compare interrupt. */
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430 #if( configTICK_USE_TC==1 )
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432 INTC_register_interrupt((__int_handler)&vTick, configTICK_TC_IRQ, INT0);
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434 /* Initialize the timer/counter. */
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435 tc_init_waveform(tc, &waveform_opt);
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437 /* Set the compare triggers.
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438 Remember TC counter is 16-bits, so counting second is not possible!
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439 That's why we configure it to count ms. */
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440 tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
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442 tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
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444 /* Start the timer/counter. */
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445 tc_start(tc, configTICK_TC_CHANNEL);
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449 INTC_register_interrupt((__int_handler)&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
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450 prvScheduleFirstTick();
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