git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/IAR/AVR32_UC3/port.c

   1 /*This file has been prepared for Doxygen automatic documentation generation.*/\r
   2 /*! \file *********************************************************************\r
   3  *\r
   4  * \brief FreeRTOS port source for AVR32 UC3.\r
   5  *\r
   6  * - Compiler:           IAR EWAVR32\r
   7  * - Supported devices:  All AVR32 devices can be used.\r
   8  * - AppNote:\r
   9  *\r
  10  * \author               Atmel Corporation: http://www.atmel.com \n\r
  11  *                       Support and FAQ: http://support.atmel.no/\r
  12  *\r
  13  *****************************************************************************/\r
  14 \r
  15 /*\r
  16     FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
  17     All rights reserved\r
  18 \r
  19     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
  20 \r
  21     This file is part of the FreeRTOS distribution.\r
  22 \r
  23     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  24     the terms of the GNU General Public License (version 2) as published by the\r
  25     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  26 \r
  27     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  28     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  29     >>!   obliged to provide the source code for proprietary components     !<<\r
  30     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  31 \r
  32     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  33     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  34     FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
  35     link: http://www.freertos.org/a00114.html\r
  36 \r
  37     1 tab == 4 spaces!\r
  38 \r
  39     ***************************************************************************\r
  40      *                                                                       *\r
  41      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  42      *    not run, what could be wrong?".  Have you defined configASSERT()?  *\r
  43      *                                                                       *\r
  44      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  45      *                                                                       *\r
  46     ***************************************************************************\r
  47 \r
  48     ***************************************************************************\r
  49      *                                                                       *\r
  50      *    FreeRTOS provides completely free yet professionally developed,    *\r
  51      *    robust, strictly quality controlled, supported, and cross          *\r
  52      *    platform software that is more than just the market leader, it     *\r
  53      *    is the industry's de facto standard.                               *\r
  54      *                                                                       *\r
  55      *    Help yourself get started quickly while simultaneously helping     *\r
  56      *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r
  57      *    tutorial book, reference manual, or both:                          *\r
  58      *    http://www.FreeRTOS.org/Documentation                              *\r
  59      *                                                                       *\r
  60     ***************************************************************************\r
  61 \r
  62     ***************************************************************************\r
  63      *                                                                       *\r
  64      *   Investing in training allows your team to be as productive as       *\r
  65      *   possible as early as possible, lowering your overall development    *\r
  66      *   cost, and enabling you to bring a more robust product to market     *\r
  67      *   earlier than would otherwise be possible.  Richard Barry is both    *\r
  68      *   the architect and key author of FreeRTOS, and so also the world's   *\r
  69      *   leading authority on what is the world's most popular real time     *\r
  70      *   kernel for deeply embedded MCU designs.  Obtaining your training    *\r
  71      *   from Richard ensures your team will gain directly from his in-depth *\r
  72      *   product knowledge and years of usage experience.  Contact Real Time *\r
  73      *   Engineers Ltd to enquire about the FreeRTOS Masterclass, presented  *\r
  74      *   by Richard Barry:  http://www.FreeRTOS.org/contact\r
  75      *                                                                       *\r
  76     ***************************************************************************\r
  77 \r
  78     ***************************************************************************\r
  79      *                                                                       *\r
  80      *    You are receiving this top quality software for free.  Please play *\r
  81      *    fair and reciprocate by reporting any suspected issues and         *\r
  82      *    participating in the community forum:                              *\r
  83      *    http://www.FreeRTOS.org/support                                    *\r
  84      *                                                                       *\r
  85      *    Thank you!                                                         *\r
  86      *                                                                       *\r
  87     ***************************************************************************\r
  88 \r
  89     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  90     license and Real Time Engineers Ltd. contact details.\r
  91 \r
  92     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  93     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  94     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  95 \r
  96     http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
  97     Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
  98 \r
  99     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
 100     Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
 101     licenses offer ticketed support, indemnification and commercial middleware.\r
 102 \r
 103     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
 104     engineered and independently SIL3 certified version for use in safety and\r
 105     mission critical applications that require provable dependability.\r
 106 \r
 107     1 tab == 4 spaces!\r
 108 */\r
 109 \r
 110 \r
 111 /* Scheduler includes. */\r
 112 #include "FreeRTOS.h"\r
 113 #include "task.h"\r
 114 \r
 115 /* AVR32 UC3 includes. */\r
 116 #include <avr32/io.h>\r
 117 #include <intrinsics.h>\r
 118 #include "gpio.h"\r
 119 \r
 120 #if configDBG\r
 121         #include "usart.h"\r
 122 #endif\r
 123 \r
 124 #if( configTICK_USE_TC==1 )\r
 125         #include "tc.h"\r
 126 #endif\r
 127 \r
 128 \r
 129 /* Constants required to setup the task context. */\r
 130 #define portINITIAL_SR            ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */\r
 131 #define portINSTRUCTION_SIZE      ( ( StackType_t ) 0 )\r
 132 \r
 133 /* Each task maintains its own critical nesting variable. */\r
 134 #define portNO_CRITICAL_NESTING   ( ( uint32_t ) 0 )\r
 135 volatile uint32_t ulCriticalNesting = 9999UL;\r
 136 \r
 137 #if( configTICK_USE_TC==0 )\r
 138         static void prvScheduleNextTick( void );\r
 139 #else\r
 140         static void prvClearTcInt( void );\r
 141 #endif\r
 142 \r
 143 /* Setup the timer to generate the tick interrupts. */\r
 144 static void prvSetupTimerInterrupt( void );\r
 145 \r
 146 /*-----------------------------------------------------------*/\r
 147 \r
 148 /*\r
 149  * Low-level initialization routine called during startup, before the main\r
 150  * function.\r
 151  */\r
 152 int __low_level_init(void)\r
 153 {\r
 154         #if configHEAP_INIT\r
 155                 #pragma segment = "HEAP"\r
 156                 BaseType_t *pxMem;\r
 157         #endif\r
 158 \r
 159         /* Enable exceptions. */\r
 160         ENABLE_ALL_EXCEPTIONS();\r
 161 \r
 162         /* Initialize interrupt handling. */\r
 163         INTC_init_interrupts();\r
 164 \r
 165         #if configHEAP_INIT\r
 166         {\r
 167                 /* Initialize the heap used by malloc. */\r
 168                 for( pxMem = __segment_begin( "HEAP" ); pxMem < ( BaseType_t * ) __segment_end( "HEAP" ); )\r
 169                 {\r
 170                         *pxMem++ = 0xA5A5A5A5;\r
 171                 }\r
 172         }\r
 173         #endif\r
 174 \r
 175         /* Code section present if and only if the debug trace is activated. */\r
 176         #if configDBG\r
 177         {\r
 178                 static const gpio_map_t DBG_USART_GPIO_MAP =\r
 179                 {\r
 180                         { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },\r
 181                         { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }\r
 182                 };\r
 183 \r
 184                 static const usart_options_t DBG_USART_OPTIONS =\r
 185                 {\r
 186                         .baudrate = configDBG_USART_BAUDRATE,\r
 187                         .charlength = 8,\r
 188                         .paritytype = USART_NO_PARITY,\r
 189                         .stopbits = USART_1_STOPBIT,\r
 190                         .channelmode = USART_NORMAL_CHMODE\r
 191                 };\r
 192 \r
 193                 /* Initialize the USART used for the debug trace with the configured parameters. */\r
 194                 extern volatile avr32_usart_t *volatile stdio_usart_base;\r
 195                 stdio_usart_base = configDBG_USART;\r
 196                 gpio_enable_module( DBG_USART_GPIO_MAP,\r
 197                                     sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );\r
 198                 usart_init_rs232(configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ);\r
 199         }\r
 200         #endif\r
 201 \r
 202         /* Request initialization of data segments. */\r
 203         return 1;\r
 204 }\r
 205 /*-----------------------------------------------------------*/\r
 206 \r
 207 /* Added as there is no such function in FreeRTOS. */\r
 208 void *pvPortRealloc( void *pv, size_t xWantedSize )\r
 209 {\r
 210 void *pvReturn;\r
 211 \r
 212         vTaskSuspendAll();\r
 213         {\r
 214                 pvReturn = realloc( pv, xWantedSize );\r
 215         }\r
 216         xTaskResumeAll();\r
 217 \r
 218         return pvReturn;\r
 219 }\r
 220 /*-----------------------------------------------------------*/\r
 221 \r
 222 /* The cooperative scheduler requires a normal IRQ service routine to\r
 223 simply increment the system tick. */\r
 224 /* The preemptive scheduler is defined as "naked" as the full context is saved\r
 225 on entry as part of the context switch. */\r
 226 #pragma shadow_registers = full   // Naked.\r
 227 static void vTick( void )\r
 228 {\r
 229         /* Save the context of the interrupted task. */\r
 230         portSAVE_CONTEXT_OS_INT();\r
 231 \r
 232         #if( configTICK_USE_TC==1 )\r
 233                 /* Clear the interrupt flag. */\r
 234                 prvClearTcInt();\r
 235         #else\r
 236                 /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)\r
 237                 clock cycles from now. */\r
 238                 prvScheduleNextTick();\r
 239         #endif\r
 240 \r
 241         /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS\r
 242         calls in a critical section . */\r
 243         portENTER_CRITICAL();\r
 244                 xTaskIncrementTick();\r
 245         portEXIT_CRITICAL();\r
 246 \r
 247         /* Restore the context of the "elected task". */\r
 248         portRESTORE_CONTEXT_OS_INT();\r
 249 }\r
 250 /*-----------------------------------------------------------*/\r
 251 \r
 252 #pragma shadow_registers = full   // Naked.\r
 253 void SCALLYield( void )\r
 254 {\r
 255         /* Save the context of the interrupted task. */\r
 256         portSAVE_CONTEXT_SCALL();\r
 257         vTaskSwitchContext();\r
 258         portRESTORE_CONTEXT_SCALL();\r
 259 }\r
 260 /*-----------------------------------------------------------*/\r
 261 \r
 262 /* The code generated by the GCC compiler uses the stack in different ways at\r
 263 different optimisation levels.  The interrupt flags can therefore not always\r
 264 be saved to the stack.  Instead the critical section nesting level is stored\r
 265 in a variable, which is then saved as part of the stack context. */\r
 266 #pragma optimize = no_inline\r
 267 void vPortEnterCritical( void )\r
 268 {\r
 269         /* Disable interrupts */\r
 270         portDISABLE_INTERRUPTS();\r
 271 \r
 272         /* Now interrupts are disabled ulCriticalNesting can be accessed\r
 273          directly.  Increment ulCriticalNesting to keep a count of how many times\r
 274          portENTER_CRITICAL() has been called. */\r
 275         ulCriticalNesting++;\r
 276 }\r
 277 /*-----------------------------------------------------------*/\r
 278 \r
 279 #pragma optimize = no_inline\r
 280 void vPortExitCritical( void )\r
 281 {\r
 282         if(ulCriticalNesting > portNO_CRITICAL_NESTING)\r
 283         {\r
 284                 ulCriticalNesting--;\r
 285                 if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
 286                 {\r
 287                         /* Enable all interrupt/exception. */\r
 288                         portENABLE_INTERRUPTS();\r
 289                 }\r
 290         }\r
 291 }\r
 292 /*-----------------------------------------------------------*/\r
 293 \r
 294 /*\r
 295  * Initialise the stack of a task to look exactly as if a call to\r
 296  * portSAVE_CONTEXT had been called.\r
 297  *\r
 298  * See header file for description.\r
 299  */\r
 300 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
 301 {\r
 302         /* Setup the initial stack of the task.  The stack is set exactly as\r
 303         expected by the portRESTORE_CONTEXT() macro. */\r
 304 \r
 305         /* When the task starts, it will expect to find the function parameter in R12. */\r
 306         pxTopOfStack--;\r
 307         *pxTopOfStack-- = ( StackType_t ) 0x08080808;                                   /* R8 */\r
 308         *pxTopOfStack-- = ( StackType_t ) 0x09090909;                                   /* R9 */\r
 309         *pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A;                                   /* R10 */\r
 310         *pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B;                                   /* R11 */\r
 311         *pxTopOfStack-- = ( StackType_t ) pvParameters;                                 /* R12 */\r
 312         *pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF;                                   /* R14/LR */\r
 313         *pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */\r
 314         *pxTopOfStack-- = ( StackType_t ) portINITIAL_SR;                               /* SR */\r
 315         *pxTopOfStack-- = ( StackType_t ) 0xFF0000FF;                                   /* R0 */\r
 316         *pxTopOfStack-- = ( StackType_t ) 0x01010101;                                   /* R1 */\r
 317         *pxTopOfStack-- = ( StackType_t ) 0x02020202;                                   /* R2 */\r
 318         *pxTopOfStack-- = ( StackType_t ) 0x03030303;                                   /* R3 */\r
 319         *pxTopOfStack-- = ( StackType_t ) 0x04040404;                                   /* R4 */\r
 320         *pxTopOfStack-- = ( StackType_t ) 0x05050505;                                   /* R5 */\r
 321         *pxTopOfStack-- = ( StackType_t ) 0x06060606;                                   /* R6 */\r
 322         *pxTopOfStack-- = ( StackType_t ) 0x07070707;                                   /* R7 */\r
 323         *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING;                        /* ulCriticalNesting */\r
 324 \r
 325         return pxTopOfStack;\r
 326 }\r
 327 /*-----------------------------------------------------------*/\r
 328 \r
 329 BaseType_t xPortStartScheduler( void )\r
 330 {\r
 331         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 332         here already. */\r
 333         prvSetupTimerInterrupt();\r
 334 \r
 335         /* Start the first task. */\r
 336         portRESTORE_CONTEXT();\r
 337 \r
 338         /* Should not get here! */\r
 339         return 0;\r
 340 }\r
 341 /*-----------------------------------------------------------*/\r
 342 \r
 343 void vPortEndScheduler( void )\r
 344 {\r
 345         /* It is unlikely that the AVR32 port will require this function as there\r
 346         is nothing to return to.  */\r
 347 }\r
 348 /*-----------------------------------------------------------*/\r
 349 \r
 350 /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)\r
 351 clock cycles from now. */\r
 352 #if( configTICK_USE_TC==0 )\r
 353         static void prvScheduleFirstTick(void)\r
 354         {\r
 355                 uint32_t lCycles;\r
 356 \r
 357                 lCycles = Get_system_register(AVR32_COUNT);\r
 358                 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);\r
 359                 // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception\r
 360                 // generation feature does not get disabled.\r
 361                 if(0 == lCycles)\r
 362                 {\r
 363                         lCycles++;\r
 364                 }\r
 365                 Set_system_register(AVR32_COMPARE, lCycles);\r
 366         }\r
 367         \r
 368         #pragma optimize = no_inline\r
 369         static void prvScheduleNextTick(void)\r
 370         {\r
 371                 uint32_t lCycles, lCount;\r
 372 \r
 373                 lCycles = Get_system_register(AVR32_COMPARE);\r
 374                 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);\r
 375                 // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception\r
 376                 // generation feature does not get disabled.\r
 377                 if(0 == lCycles)\r
 378                 {\r
 379                         lCycles++;\r
 380                 }\r
 381                 lCount = Get_system_register(AVR32_COUNT);\r
 382                 if( lCycles < lCount )\r
 383                 {               // We missed a tick, recover for the next.\r
 384                         lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);\r
 385                 }\r
 386                 Set_system_register(AVR32_COMPARE, lCycles);\r
 387         }\r
 388 #else\r
 389         #pragma optimize = no_inline\r
 390         static void prvClearTcInt(void)\r
 391         {\r
 392                 AVR32_TC.channel[configTICK_TC_CHANNEL].sr;\r
 393         }\r
 394 #endif\r
 395 /*-----------------------------------------------------------*/\r
 396 \r
 397 /* Setup the timer to generate the tick interrupts. */\r
 398 static void prvSetupTimerInterrupt(void)\r
 399 {\r
 400         #if( configTICK_USE_TC==1 )\r
 401 \r
 402                 volatile avr32_tc_t *tc = &AVR32_TC;\r
 403 \r
 404                 // Options for waveform genration.\r
 405                 tc_waveform_opt_t waveform_opt =\r
 406                 {\r
 407                 .channel  = configTICK_TC_CHANNEL,             /* Channel selection. */\r
 408 \r
 409                 .bswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOB. */\r
 410                 .beevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOB. */\r
 411                 .bcpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOB. */\r
 412                 .bcpb     = TC_EVT_EFFECT_NOOP,                /* RB compare effect on TIOB. */\r
 413 \r
 414                 .aswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOA. */\r
 415                 .aeevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOA. */\r
 416                 .acpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOA: toggle. */\r
 417                 .acpa     = TC_EVT_EFFECT_NOOP,                /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */\r
 418 \r
 419                 .wavsel   = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */\r
 420                 .enetrg   = FALSE,                             /* External event trigger enable. */\r
 421                 .eevt     = 0,                                 /* External event selection. */\r
 422                 .eevtedg  = TC_SEL_NO_EDGE,                    /* External event edge selection. */\r
 423                 .cpcdis   = FALSE,                             /* Counter disable when RC compare. */\r
 424                 .cpcstop  = FALSE,                             /* Counter clock stopped with RC compare. */\r
 425 \r
 426                 .burst    = FALSE,                             /* Burst signal selection. */\r
 427                 .clki     = FALSE,                             /* Clock inversion. */\r
 428                 .tcclks   = TC_CLOCK_SOURCE_TC2                /* Internal source clock 2. */\r
 429                 };\r
 430 \r
 431                 tc_interrupt_t tc_interrupt =\r
 432                 {\r
 433                         .etrgs=0,\r
 434                         .ldrbs=0,\r
 435                         .ldras=0,\r
 436                         .cpcs =1,\r
 437                         .cpbs =0,\r
 438                         .cpas =0,\r
 439                         .lovrs=0,\r
 440                         .covfs=0,\r
 441                 };\r
 442 \r
 443         #endif\r
 444 \r
 445         /* Disable all interrupt/exception. */\r
 446         portDISABLE_INTERRUPTS();\r
 447 \r
 448         /* Register the compare interrupt handler to the interrupt controller and\r
 449         enable the compare interrupt. */\r
 450 \r
 451         #if( configTICK_USE_TC==1 )\r
 452         {\r
 453                 INTC_register_interrupt((__int_handler)&vTick, configTICK_TC_IRQ, INT0);\r
 454 \r
 455                 /* Initialize the timer/counter. */\r
 456                 tc_init_waveform(tc, &waveform_opt);\r
 457 \r
 458                 /* Set the compare triggers.\r
 459                 Remember TC counter is 16-bits, so counting second is not possible!\r
 460                 That's why we configure it to count ms. */\r
 461                 tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );\r
 462 \r
 463                 tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );\r
 464 \r
 465                 /* Start the timer/counter. */\r
 466                 tc_start(tc, configTICK_TC_CHANNEL);\r
 467         }\r
 468         #else\r
 469         {\r
 470                 INTC_register_interrupt((__int_handler)&vTick, AVR32_CORE_COMPARE_IRQ, INT0);\r
 471                 prvScheduleFirstTick();\r
 472         }\r
 473         #endif\r
 474 }\r