1 // ----------------------------------------------------------------------------
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2 // ATMEL Microcontroller Software Support - ROUSSET -
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3 // ----------------------------------------------------------------------------
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4 // The software is delivered "AS IS" without warranty or condition of any
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5 // kind, either express, implied or statutory. This includes without
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6 // limitation any warranty or condition with respect to merchantability or
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7 // fitness for any particular purpose, or against the infringements of
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8 // intellectual property rights of others.
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9 // ----------------------------------------------------------------------------
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10 // File Name : AT91SAM7S64.h
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11 // Object : AT91SAM7S64 definitions
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12 // Generated : AT91 SW Application Group 07/16/2004 (07:43:09)
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14 // CVS Reference : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004//
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15 // CVS Reference : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004//
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16 // CVS Reference : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004//
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17 // CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 2 14:45:38 2002//
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18 // CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
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19 // CVS Reference : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
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20 // CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
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21 // CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
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22 // CVS Reference : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004//
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23 // CVS Reference : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//
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24 // CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 8 13:26:40 2002//
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25 // CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
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26 // CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 7 10:30:08 2003//
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27 // CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//
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28 // CVS Reference : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//
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29 // CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
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30 // ----------------------------------------------------------------------------
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32 // Hardware register definition
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34 // *****************************************************************************
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35 // SOFTWARE API DEFINITION FOR System Peripherals
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36 // *****************************************************************************
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37 // *** Register offset in AT91S_SYSC structure ***
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38 #define SYSC_AIC_SMR ( 0) // Source Mode Register
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39 #define SYSC_AIC_SVR (128) // Source Vector Register
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40 #define SYSC_AIC_IVR (256) // IRQ Vector Register
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41 #define SYSC_AIC_FVR (260) // FIQ Vector Register
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42 #define SYSC_AIC_ISR (264) // Interrupt Status Register
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43 #define SYSC_AIC_IPR (268) // Interrupt Pending Register
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44 #define SYSC_AIC_IMR (272) // Interrupt Mask Register
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45 #define SYSC_AIC_CISR (276) // Core Interrupt Status Register
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46 #define SYSC_AIC_IECR (288) // Interrupt Enable Command Register
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47 #define SYSC_AIC_IDCR (292) // Interrupt Disable Command Register
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48 #define SYSC_AIC_ICCR (296) // Interrupt Clear Command Register
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49 #define SYSC_AIC_ISCR (300) // Interrupt Set Command Register
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50 #define SYSC_AIC_EOICR (304) // End of Interrupt Command Register
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51 #define SYSC_AIC_SPU (308) // Spurious Vector Register
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52 #define SYSC_AIC_DCR (312) // Debug Control Register (Protect)
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53 #define SYSC_AIC_FFER (320) // Fast Forcing Enable Register
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54 #define SYSC_AIC_FFDR (324) // Fast Forcing Disable Register
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55 #define SYSC_AIC_FFSR (328) // Fast Forcing Status Register
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56 #define SYSC_DBGU_CR (512) // Control Register
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57 #define SYSC_DBGU_MR (516) // Mode Register
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58 #define SYSC_DBGU_IER (520) // Interrupt Enable Register
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59 #define SYSC_DBGU_IDR (524) // Interrupt Disable Register
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60 #define SYSC_DBGU_IMR (528) // Interrupt Mask Register
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61 #define SYSC_DBGU_CSR (532) // Channel Status Register
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62 #define SYSC_DBGU_RHR (536) // Receiver Holding Register
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63 #define SYSC_DBGU_THR (540) // Transmitter Holding Register
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64 #define SYSC_DBGU_BRGR (544) // Baud Rate Generator Register
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65 #define SYSC_DBGU_C1R (576) // Chip ID1 Register
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66 #define SYSC_DBGU_C2R (580) // Chip ID2 Register
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67 #define SYSC_DBGU_FNTR (584) // Force NTRST Register
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68 #define SYSC_DBGU_RPR (768) // Receive Pointer Register
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69 #define SYSC_DBGU_RCR (772) // Receive Counter Register
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70 #define SYSC_DBGU_TPR (776) // Transmit Pointer Register
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71 #define SYSC_DBGU_TCR (780) // Transmit Counter Register
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72 #define SYSC_DBGU_RNPR (784) // Receive Next Pointer Register
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73 #define SYSC_DBGU_RNCR (788) // Receive Next Counter Register
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74 #define SYSC_DBGU_TNPR (792) // Transmit Next Pointer Register
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75 #define SYSC_DBGU_TNCR (796) // Transmit Next Counter Register
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76 #define SYSC_DBGU_PTCR (800) // PDC Transfer Control Register
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77 #define SYSC_DBGU_PTSR (804) // PDC Transfer Status Register
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78 #define SYSC_PIOA_PER (1024) // PIO Enable Register
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79 #define SYSC_PIOA_PDR (1028) // PIO Disable Register
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80 #define SYSC_PIOA_PSR (1032) // PIO Status Register
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81 #define SYSC_PIOA_OER (1040) // Output Enable Register
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82 #define SYSC_PIOA_ODR (1044) // Output Disable Registerr
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83 #define SYSC_PIOA_OSR (1048) // Output Status Register
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84 #define SYSC_PIOA_IFER (1056) // Input Filter Enable Register
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85 #define SYSC_PIOA_IFDR (1060) // Input Filter Disable Register
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86 #define SYSC_PIOA_IFSR (1064) // Input Filter Status Register
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87 #define SYSC_PIOA_SODR (1072) // Set Output Data Register
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88 #define SYSC_PIOA_CODR (1076) // Clear Output Data Register
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89 #define SYSC_PIOA_ODSR (1080) // Output Data Status Register
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90 #define SYSC_PIOA_PDSR (1084) // Pin Data Status Register
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91 #define SYSC_PIOA_IER (1088) // Interrupt Enable Register
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92 #define SYSC_PIOA_IDR (1092) // Interrupt Disable Register
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93 #define SYSC_PIOA_IMR (1096) // Interrupt Mask Register
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94 #define SYSC_PIOA_ISR (1100) // Interrupt Status Register
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95 #define SYSC_PIOA_MDER (1104) // Multi-driver Enable Register
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96 #define SYSC_PIOA_MDDR (1108) // Multi-driver Disable Register
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97 #define SYSC_PIOA_MDSR (1112) // Multi-driver Status Register
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98 #define SYSC_PIOA_PPUDR (1120) // Pull-up Disable Register
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99 #define SYSC_PIOA_PPUER (1124) // Pull-up Enable Register
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100 #define SYSC_PIOA_PPUSR (1128) // Pad Pull-up Status Register
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101 #define SYSC_PIOA_ASR (1136) // Select A Register
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102 #define SYSC_PIOA_BSR (1140) // Select B Register
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103 #define SYSC_PIOA_ABSR (1144) // AB Select Status Register
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104 #define SYSC_PIOA_OWER (1184) // Output Write Enable Register
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105 #define SYSC_PIOA_OWDR (1188) // Output Write Disable Register
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106 #define SYSC_PIOA_OWSR (1192) // Output Write Status Register
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107 #define SYSC_PMC_SCER (3072) // System Clock Enable Register
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108 #define SYSC_PMC_SCDR (3076) // System Clock Disable Register
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109 #define SYSC_PMC_SCSR (3080) // System Clock Status Register
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110 #define SYSC_PMC_PCER (3088) // Peripheral Clock Enable Register
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111 #define SYSC_PMC_PCDR (3092) // Peripheral Clock Disable Register
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112 #define SYSC_PMC_PCSR (3096) // Peripheral Clock Status Register
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113 #define SYSC_PMC_MOR (3104) // Main Oscillator Register
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114 #define SYSC_PMC_MCFR (3108) // Main Clock Frequency Register
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115 #define SYSC_PMC_PLLR (3116) // PLL Register
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116 #define SYSC_PMC_MCKR (3120) // Master Clock Register
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117 #define SYSC_PMC_PCKR (3136) // Programmable Clock Register
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118 #define SYSC_PMC_IER (3168) // Interrupt Enable Register
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119 #define SYSC_PMC_IDR (3172) // Interrupt Disable Register
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120 #define SYSC_PMC_SR (3176) // Status Register
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121 #define SYSC_PMC_IMR (3180) // Interrupt Mask Register
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122 #define SYSC_RSTC_RCR (3328) // Reset Control Register
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123 #define SYSC_RSTC_RSR (3332) // Reset Status Register
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124 #define SYSC_RSTC_RMR (3336) // Reset Mode Register
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125 #define SYSC_RTTC_RTMR (3360) // Real-time Mode Register
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126 #define SYSC_RTTC_RTAR (3364) // Real-time Alarm Register
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127 #define SYSC_RTTC_RTVR (3368) // Real-time Value Register
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128 #define SYSC_RTTC_RTSR (3372) // Real-time Status Register
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129 #define SYSC_PITC_PIMR (3376) // Period Interval Mode Register
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130 #define SYSC_PITC_PISR (3380) // Period Interval Status Register
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131 #define SYSC_PITC_PIVR (3384) // Period Interval Value Register
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132 #define SYSC_PITC_PIIR (3388) // Period Interval Image Register
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133 #define SYSC_WDTC_WDCR (3392) // Watchdog Control Register
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134 #define SYSC_WDTC_WDMR (3396) // Watchdog Mode Register
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135 #define SYSC_WDTC_WDSR (3400) // Watchdog Status Register
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136 #define SYSC_SYSC_VRPM (3424) // Voltage Regulator Power Mode Register
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137 // -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register --------
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138 #define AT91C_SYSC_PSTDBY (0x1 << 0) // (SYSC) Voltage Regulator Power Mode
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140 // *****************************************************************************
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141 // SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
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142 // *****************************************************************************
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143 // *** Register offset in AT91S_AIC structure ***
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144 #define AIC_SMR ( 0) // Source Mode Register
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145 #define AIC_SVR (128) // Source Vector Register
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146 #define AIC_IVR (256) // IRQ Vector Register
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147 #define AIC_FVR (260) // FIQ Vector Register
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148 #define AIC_ISR (264) // Interrupt Status Register
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149 #define AIC_IPR (268) // Interrupt Pending Register
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150 #define AIC_IMR (272) // Interrupt Mask Register
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151 #define AIC_CISR (276) // Core Interrupt Status Register
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152 #define AIC_IECR (288) // Interrupt Enable Command Register
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153 #define AIC_IDCR (292) // Interrupt Disable Command Register
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154 #define AIC_ICCR (296) // Interrupt Clear Command Register
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155 #define AIC_ISCR (300) // Interrupt Set Command Register
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156 #define AIC_EOICR (304) // End of Interrupt Command Register
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157 #define AIC_SPU (308) // Spurious Vector Register
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158 #define AIC_DCR (312) // Debug Control Register (Protect)
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159 #define AIC_FFER (320) // Fast Forcing Enable Register
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160 #define AIC_FFDR (324) // Fast Forcing Disable Register
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161 #define AIC_FFSR (328) // Fast Forcing Status Register
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162 // -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
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163 #define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
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164 #define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
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165 #define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
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166 #define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
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167 #define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
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168 #define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
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169 #define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
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170 #define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
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171 // -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
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172 #define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
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173 #define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
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174 // -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
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175 #define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
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176 #define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
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178 // *****************************************************************************
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179 // SOFTWARE API DEFINITION FOR Debug Unit
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180 // *****************************************************************************
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181 // *** Register offset in AT91S_DBGU structure ***
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182 #define DBGU_CR ( 0) // Control Register
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183 #define DBGU_MR ( 4) // Mode Register
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184 #define DBGU_IER ( 8) // Interrupt Enable Register
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185 #define DBGU_IDR (12) // Interrupt Disable Register
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186 #define DBGU_IMR (16) // Interrupt Mask Register
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187 #define DBGU_CSR (20) // Channel Status Register
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188 #define DBGU_RHR (24) // Receiver Holding Register
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189 #define DBGU_THR (28) // Transmitter Holding Register
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190 #define DBGU_BRGR (32) // Baud Rate Generator Register
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191 #define DBGU_C1R (64) // Chip ID1 Register
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192 #define DBGU_C2R (68) // Chip ID2 Register
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193 #define DBGU_FNTR (72) // Force NTRST Register
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194 #define DBGU_RPR (256) // Receive Pointer Register
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195 #define DBGU_RCR (260) // Receive Counter Register
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196 #define DBGU_TPR (264) // Transmit Pointer Register
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197 #define DBGU_TCR (268) // Transmit Counter Register
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198 #define DBGU_RNPR (272) // Receive Next Pointer Register
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199 #define DBGU_RNCR (276) // Receive Next Counter Register
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200 #define DBGU_TNPR (280) // Transmit Next Pointer Register
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201 #define DBGU_TNCR (284) // Transmit Next Counter Register
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202 #define DBGU_PTCR (288) // PDC Transfer Control Register
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203 #define DBGU_PTSR (292) // PDC Transfer Status Register
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204 // -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
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205 #define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
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206 #define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
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207 #define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
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208 #define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
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209 #define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
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210 #define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
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211 // -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
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212 #define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
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213 #define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
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214 #define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
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215 #define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
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216 #define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
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217 #define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
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218 #define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
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219 #define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
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220 #define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
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221 #define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
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222 #define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
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223 #define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
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224 // -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
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225 #define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
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226 #define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
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227 #define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
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228 #define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
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229 #define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
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230 #define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
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231 #define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
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232 #define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
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233 #define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
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234 #define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
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235 #define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
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236 #define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
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237 // -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
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238 // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
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239 // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
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240 // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
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241 #define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
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243 // *****************************************************************************
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244 // SOFTWARE API DEFINITION FOR Peripheral Data Controller
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245 // *****************************************************************************
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246 // *** Register offset in AT91S_PDC structure ***
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247 #define PDC_RPR ( 0) // Receive Pointer Register
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248 #define PDC_RCR ( 4) // Receive Counter Register
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249 #define PDC_TPR ( 8) // Transmit Pointer Register
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250 #define PDC_TCR (12) // Transmit Counter Register
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251 #define PDC_RNPR (16) // Receive Next Pointer Register
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252 #define PDC_RNCR (20) // Receive Next Counter Register
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253 #define PDC_TNPR (24) // Transmit Next Pointer Register
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254 #define PDC_TNCR (28) // Transmit Next Counter Register
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255 #define PDC_PTCR (32) // PDC Transfer Control Register
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256 #define PDC_PTSR (36) // PDC Transfer Status Register
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257 // -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
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258 #define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
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259 #define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
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260 #define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
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261 #define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
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262 // -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
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264 // *****************************************************************************
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265 // SOFTWARE API DEFINITION FOR Parallel Input Output Controler
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266 // *****************************************************************************
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267 // *** Register offset in AT91S_PIO structure ***
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268 #define PIO_PER ( 0) // PIO Enable Register
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269 #define PIO_PDR ( 4) // PIO Disable Register
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270 #define PIO_PSR ( 8) // PIO Status Register
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271 #define PIO_OER (16) // Output Enable Register
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272 #define PIO_ODR (20) // Output Disable Registerr
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273 #define PIO_OSR (24) // Output Status Register
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274 #define PIO_IFER (32) // Input Filter Enable Register
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275 #define PIO_IFDR (36) // Input Filter Disable Register
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276 #define PIO_IFSR (40) // Input Filter Status Register
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277 #define PIO_SODR (48) // Set Output Data Register
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278 #define PIO_CODR (52) // Clear Output Data Register
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279 #define PIO_ODSR (56) // Output Data Status Register
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280 #define PIO_PDSR (60) // Pin Data Status Register
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281 #define PIO_IER (64) // Interrupt Enable Register
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282 #define PIO_IDR (68) // Interrupt Disable Register
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283 #define PIO_IMR (72) // Interrupt Mask Register
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284 #define PIO_ISR (76) // Interrupt Status Register
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285 #define PIO_MDER (80) // Multi-driver Enable Register
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286 #define PIO_MDDR (84) // Multi-driver Disable Register
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287 #define PIO_MDSR (88) // Multi-driver Status Register
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288 #define PIO_PPUDR (96) // Pull-up Disable Register
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289 #define PIO_PPUER (100) // Pull-up Enable Register
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290 #define PIO_PPUSR (104) // Pad Pull-up Status Register
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291 #define PIO_ASR (112) // Select A Register
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292 #define PIO_BSR (116) // Select B Register
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293 #define PIO_ABSR (120) // AB Select Status Register
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294 #define PIO_OWER (160) // Output Write Enable Register
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295 #define PIO_OWDR (164) // Output Write Disable Register
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296 #define PIO_OWSR (168) // Output Write Status Register
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298 // *****************************************************************************
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299 // SOFTWARE API DEFINITION FOR Clock Generator Controler
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300 // *****************************************************************************
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301 // *** Register offset in AT91S_CKGR structure ***
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302 #define CKGR_MOR ( 0) // Main Oscillator Register
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303 #define CKGR_MCFR ( 4) // Main Clock Frequency Register
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304 #define CKGR_PLLR (12) // PLL Register
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305 // -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
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306 #define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
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307 #define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
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308 #define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
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309 // -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
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310 #define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
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311 #define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
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312 // -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
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313 #define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected
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314 #define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0
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315 #define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed
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316 #define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter
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317 #define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range
\r
318 #define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
\r
319 #define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
\r
320 #define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
\r
321 #define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
\r
322 #define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier
\r
323 #define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
\r
324 #define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
\r
325 #define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
\r
326 #define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
\r
328 // *****************************************************************************
\r
329 // SOFTWARE API DEFINITION FOR Power Management Controler
\r
330 // *****************************************************************************
\r
331 // *** Register offset in AT91S_PMC structure ***
\r
332 #define PMC_SCER ( 0) // System Clock Enable Register
\r
333 #define PMC_SCDR ( 4) // System Clock Disable Register
\r
334 #define PMC_SCSR ( 8) // System Clock Status Register
\r
335 #define PMC_PCER (16) // Peripheral Clock Enable Register
\r
336 #define PMC_PCDR (20) // Peripheral Clock Disable Register
\r
337 #define PMC_PCSR (24) // Peripheral Clock Status Register
\r
338 #define PMC_MOR (32) // Main Oscillator Register
\r
339 #define PMC_MCFR (36) // Main Clock Frequency Register
\r
340 #define PMC_PLLR (44) // PLL Register
\r
341 #define PMC_MCKR (48) // Master Clock Register
\r
342 #define PMC_PCKR (64) // Programmable Clock Register
\r
343 #define PMC_IER (96) // Interrupt Enable Register
\r
344 #define PMC_IDR (100) // Interrupt Disable Register
\r
345 #define PMC_SR (104) // Status Register
\r
346 #define PMC_IMR (108) // Interrupt Mask Register
\r
347 // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
\r
348 #define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
\r
349 #define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
\r
350 #define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
\r
351 #define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
\r
352 #define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
\r
353 #define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
\r
354 // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
\r
355 // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
\r
356 // -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
\r
357 // -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
\r
358 // -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
\r
359 // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
\r
360 #define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
\r
361 #define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
\r
362 #define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
\r
363 #define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected
\r
364 #define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
\r
365 #define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
\r
366 #define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
\r
367 #define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
\r
368 #define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
\r
369 #define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
\r
370 #define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
\r
371 #define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
\r
372 // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
\r
373 // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
\r
374 #define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
\r
375 #define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask
\r
376 #define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
\r
377 #define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
\r
378 #define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
\r
379 #define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
\r
380 #define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
\r
381 // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
\r
382 // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
\r
383 // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
\r
385 // *****************************************************************************
\r
386 // SOFTWARE API DEFINITION FOR Reset Controller Interface
\r
387 // *****************************************************************************
\r
388 // *** Register offset in AT91S_RSTC structure ***
\r
389 #define RSTC_RCR ( 0) // Reset Control Register
\r
390 #define RSTC_RSR ( 4) // Reset Status Register
\r
391 #define RSTC_RMR ( 8) // Reset Mode Register
\r
392 // -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
\r
393 #define AT91C_SYSC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
\r
394 #define AT91C_SYSC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset
\r
395 #define AT91C_SYSC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
\r
396 #define AT91C_SYSC_EXTRST (0x1 << 3) // (RSTC) External Reset
\r
397 #define AT91C_SYSC_KEY (0xFF << 24) // (RSTC) Password
\r
398 // -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
\r
399 #define AT91C_SYSC_URSTS (0x1 << 0) // (RSTC) User Reset Status
\r
400 #define AT91C_SYSC_BODSTS (0x1 << 1) // (RSTC) Brown-out Detection Status
\r
401 #define AT91C_SYSC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
\r
402 #define AT91C_SYSC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising.
\r
403 #define AT91C_SYSC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
\r
404 #define AT91C_SYSC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
\r
405 #define AT91C_SYSC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
\r
406 #define AT91C_SYSC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brown-out Reset.
\r
407 #define AT91C_SYSC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
\r
408 #define AT91C_SYSC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
\r
409 // -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
\r
410 #define AT91C_SYSC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
\r
411 #define AT91C_SYSC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
\r
412 #define AT91C_SYSC_ERSTL (0xF << 8) // (RSTC) User Reset Enable
\r
413 #define AT91C_SYSC_BODIEN (0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable
\r
415 // *****************************************************************************
\r
416 // SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
\r
417 // *****************************************************************************
\r
418 // *** Register offset in AT91S_RTTC structure ***
\r
419 #define RTTC_RTMR ( 0) // Real-time Mode Register
\r
420 #define RTTC_RTAR ( 4) // Real-time Alarm Register
\r
421 #define RTTC_RTVR ( 8) // Real-time Value Register
\r
422 #define RTTC_RTSR (12) // Real-time Status Register
\r
423 // -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
\r
424 #define AT91C_SYSC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
\r
425 #define AT91C_SYSC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
\r
426 #define AT91C_SYSC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
\r
427 #define AT91C_SYSC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
\r
428 // -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
\r
429 #define AT91C_SYSC_ALMV (0x0 << 0) // (RTTC) Alarm Value
\r
430 // -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
\r
431 #define AT91C_SYSC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
\r
432 // -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
\r
433 #define AT91C_SYSC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
\r
434 #define AT91C_SYSC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
\r
436 // *****************************************************************************
\r
437 // SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
\r
438 // *****************************************************************************
\r
439 // *** Register offset in AT91S_PITC structure ***
\r
440 #define PITC_PIMR ( 0) // Period Interval Mode Register
\r
441 #define PITC_PISR ( 4) // Period Interval Status Register
\r
442 #define PITC_PIVR ( 8) // Period Interval Value Register
\r
443 #define PITC_PIIR (12) // Period Interval Image Register
\r
444 // -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
\r
445 #define AT91C_SYSC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
\r
446 #define AT91C_SYSC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
\r
447 #define AT91C_SYSC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
\r
448 // -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
\r
449 #define AT91C_SYSC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
\r
450 // -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
\r
451 #define AT91C_SYSC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
\r
452 #define AT91C_SYSC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
\r
453 // -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
\r
455 // *****************************************************************************
\r
456 // SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
\r
457 // *****************************************************************************
\r
458 // *** Register offset in AT91S_WDTC structure ***
\r
459 #define WDTC_WDCR ( 0) // Watchdog Control Register
\r
460 #define WDTC_WDMR ( 4) // Watchdog Mode Register
\r
461 #define WDTC_WDSR ( 8) // Watchdog Status Register
\r
462 // -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
\r
463 #define AT91C_SYSC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
\r
464 // -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
\r
465 #define AT91C_SYSC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
\r
466 #define AT91C_SYSC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
\r
467 #define AT91C_SYSC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
\r
468 #define AT91C_SYSC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
\r
469 #define AT91C_SYSC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
\r
470 #define AT91C_SYSC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
\r
471 #define AT91C_SYSC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
\r
472 #define AT91C_SYSC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
\r
473 // -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
\r
474 #define AT91C_SYSC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
\r
475 #define AT91C_SYSC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
\r
477 // *****************************************************************************
\r
478 // SOFTWARE API DEFINITION FOR Memory Controller Interface
\r
479 // *****************************************************************************
\r
480 // *** Register offset in AT91S_MC structure ***
\r
481 #define MC_RCR ( 0) // MC Remap Control Register
\r
482 #define MC_ASR ( 4) // MC Abort Status Register
\r
483 #define MC_AASR ( 8) // MC Abort Address Status Register
\r
484 #define MC_FMR (96) // MC Flash Mode Register
\r
485 #define MC_FCR (100) // MC Flash Command Register
\r
486 #define MC_FSR (104) // MC Flash Status Register
\r
487 // -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
\r
488 #define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit
\r
489 // -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
\r
490 #define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status
\r
491 #define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status
\r
492 #define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status
\r
493 #define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte
\r
494 #define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word
\r
495 #define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word
\r
496 #define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status
\r
497 #define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read
\r
498 #define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write
\r
499 #define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch
\r
500 #define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source
\r
501 #define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source
\r
502 #define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source
\r
503 #define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source
\r
504 // -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
\r
505 #define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready
\r
506 #define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error
\r
507 #define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error
\r
508 #define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming
\r
509 #define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State
\r
510 #define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations
\r
511 #define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations
\r
512 #define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations
\r
513 #define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations
\r
514 #define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number
\r
515 // -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
\r
516 #define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command
\r
517 #define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
\r
518 #define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
\r
519 #define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
\r
520 #define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
\r
521 #define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
\r
522 #define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits.
\r
523 #define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits.
\r
524 #define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit.
\r
525 #define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number
\r
526 #define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key
\r
527 // -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
\r
528 #define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status
\r
529 #define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status
\r
530 #define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status
\r
531 #define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status
\r
532 #define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status
\r
533 #define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status
\r
534 #define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status
\r
535 #define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status
\r
536 #define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status
\r
537 #define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status
\r
538 #define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status
\r
539 #define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status
\r
540 #define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status
\r
541 #define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status
\r
542 #define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status
\r
543 #define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status
\r
544 #define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status
\r
545 #define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status
\r
546 #define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status
\r
547 #define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status
\r
548 #define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status
\r
549 #define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status
\r
550 #define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status
\r
551 #define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status
\r
552 #define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status
\r
554 // *****************************************************************************
\r
555 // SOFTWARE API DEFINITION FOR Serial Parallel Interface
\r
556 // *****************************************************************************
\r
557 // *** Register offset in AT91S_SPI structure ***
\r
558 #define SPI_CR ( 0) // Control Register
\r
559 #define SPI_MR ( 4) // Mode Register
\r
560 #define SPI_RDR ( 8) // Receive Data Register
\r
561 #define SPI_TDR (12) // Transmit Data Register
\r
562 #define SPI_SR (16) // Status Register
\r
563 #define SPI_IER (20) // Interrupt Enable Register
\r
564 #define SPI_IDR (24) // Interrupt Disable Register
\r
565 #define SPI_IMR (28) // Interrupt Mask Register
\r
566 #define SPI_CSR (48) // Chip Select Register
\r
567 #define SPI_RPR (256) // Receive Pointer Register
\r
568 #define SPI_RCR (260) // Receive Counter Register
\r
569 #define SPI_TPR (264) // Transmit Pointer Register
\r
570 #define SPI_TCR (268) // Transmit Counter Register
\r
571 #define SPI_RNPR (272) // Receive Next Pointer Register
\r
572 #define SPI_RNCR (276) // Receive Next Counter Register
\r
573 #define SPI_TNPR (280) // Transmit Next Pointer Register
\r
574 #define SPI_TNCR (284) // Transmit Next Counter Register
\r
575 #define SPI_PTCR (288) // PDC Transfer Control Register
\r
576 #define SPI_PTSR (292) // PDC Transfer Status Register
\r
577 // -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
\r
578 #define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
\r
579 #define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
\r
580 #define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
\r
581 #define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
\r
582 // -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
\r
583 #define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
\r
584 #define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
\r
585 #define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
\r
586 #define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
\r
587 #define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
\r
588 #define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
\r
589 #define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
\r
590 #define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
\r
591 #define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
\r
592 #define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
\r
593 // -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
\r
594 #define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
\r
595 #define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
\r
596 // -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
\r
597 #define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
\r
598 #define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
\r
599 // -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
\r
600 #define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
\r
601 #define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
\r
602 #define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
\r
603 #define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
\r
604 #define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
\r
605 #define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
\r
606 #define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
\r
607 #define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
\r
608 #define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
\r
609 #define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
\r
610 #define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
\r
611 // -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
\r
612 // -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
\r
613 // -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
\r
614 // -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
\r
615 #define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
\r
616 #define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
\r
617 #define AT91C_SPI_CSAAT (0x1 << 2) // (SPI) Chip Select Active After Transfer
\r
618 #define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
\r
619 #define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
\r
620 #define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
\r
621 #define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
\r
622 #define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
\r
623 #define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
\r
624 #define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
\r
625 #define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
\r
626 #define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
\r
627 #define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
\r
628 #define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
\r
629 #define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Serial Clock Baud Rate
\r
630 #define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
\r
632 // *****************************************************************************
\r
633 // SOFTWARE API DEFINITION FOR Analog to Digital Convertor
\r
634 // *****************************************************************************
\r
635 // *** Register offset in AT91S_ADC structure ***
\r
636 #define ADC_CR ( 0) // ADC Control Register
\r
637 #define ADC_MR ( 4) // ADC Mode Register
\r
638 #define ADC_CHER (16) // ADC Channel Enable Register
\r
639 #define ADC_CHDR (20) // ADC Channel Disable Register
\r
640 #define ADC_CHSR (24) // ADC Channel Status Register
\r
641 #define ADC_SR (28) // ADC Status Register
\r
642 #define ADC_LCDR (32) // ADC Last Converted Data Register
\r
643 #define ADC_IER (36) // ADC Interrupt Enable Register
\r
644 #define ADC_IDR (40) // ADC Interrupt Disable Register
\r
645 #define ADC_IMR (44) // ADC Interrupt Mask Register
\r
646 #define ADC_CDR0 (48) // ADC Channel Data Register 0
\r
647 #define ADC_CDR1 (52) // ADC Channel Data Register 1
\r
648 #define ADC_CDR2 (56) // ADC Channel Data Register 2
\r
649 #define ADC_CDR3 (60) // ADC Channel Data Register 3
\r
650 #define ADC_CDR4 (64) // ADC Channel Data Register 4
\r
651 #define ADC_CDR5 (68) // ADC Channel Data Register 5
\r
652 #define ADC_CDR6 (72) // ADC Channel Data Register 6
\r
653 #define ADC_CDR7 (76) // ADC Channel Data Register 7
\r
654 #define ADC_RPR (256) // Receive Pointer Register
\r
655 #define ADC_RCR (260) // Receive Counter Register
\r
656 #define ADC_TPR (264) // Transmit Pointer Register
\r
657 #define ADC_TCR (268) // Transmit Counter Register
\r
658 #define ADC_RNPR (272) // Receive Next Pointer Register
\r
659 #define ADC_RNCR (276) // Receive Next Counter Register
\r
660 #define ADC_TNPR (280) // Transmit Next Pointer Register
\r
661 #define ADC_TNCR (284) // Transmit Next Counter Register
\r
662 #define ADC_PTCR (288) // PDC Transfer Control Register
\r
663 #define ADC_PTSR (292) // PDC Transfer Status Register
\r
664 // -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
\r
665 #define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
\r
666 #define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
\r
667 // -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
\r
668 #define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
\r
669 #define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
\r
670 #define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
\r
671 #define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
\r
672 #define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0
\r
673 #define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1
\r
674 #define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2
\r
675 #define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3
\r
676 #define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4
\r
677 #define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5
\r
678 #define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
\r
679 #define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
\r
680 #define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
\r
681 #define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
\r
682 #define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
\r
683 #define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
\r
684 #define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
\r
685 #define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
\r
686 #define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
\r
687 #define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
\r
688 // -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
\r
689 #define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
\r
690 #define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
\r
691 #define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
\r
692 #define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
\r
693 #define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
\r
694 #define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
\r
695 #define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
\r
696 #define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
\r
697 // -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
\r
698 // -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
\r
699 // -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
\r
700 #define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
\r
701 #define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
\r
702 #define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
\r
703 #define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
\r
704 #define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
\r
705 #define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
\r
706 #define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
\r
707 #define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
\r
708 #define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
\r
709 #define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
\r
710 #define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
\r
711 #define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
\r
712 #define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
\r
713 #define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
\r
714 #define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
\r
715 #define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
\r
716 #define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
\r
717 #define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
\r
718 #define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
\r
719 #define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
\r
720 // -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
\r
721 #define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
\r
722 // -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
\r
723 // -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
\r
724 // -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
\r
725 // -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
\r
726 #define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
\r
727 // -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
\r
728 // -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
\r
729 // -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
\r
730 // -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
\r
731 // -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
\r
732 // -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
\r
733 // -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
\r
735 // *****************************************************************************
\r
736 // SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
\r
737 // *****************************************************************************
\r
738 // *** Register offset in AT91S_SSC structure ***
\r
739 #define SSC_CR ( 0) // Control Register
\r
740 #define SSC_CMR ( 4) // Clock Mode Register
\r
741 #define SSC_RCMR (16) // Receive Clock ModeRegister
\r
742 #define SSC_RFMR (20) // Receive Frame Mode Register
\r
743 #define SSC_TCMR (24) // Transmit Clock Mode Register
\r
744 #define SSC_TFMR (28) // Transmit Frame Mode Register
\r
745 #define SSC_RHR (32) // Receive Holding Register
\r
746 #define SSC_THR (36) // Transmit Holding Register
\r
747 #define SSC_RSHR (48) // Receive Sync Holding Register
\r
748 #define SSC_TSHR (52) // Transmit Sync Holding Register
\r
749 #define SSC_RC0R (56) // Receive Compare 0 Register
\r
750 #define SSC_RC1R (60) // Receive Compare 1 Register
\r
751 #define SSC_SR (64) // Status Register
\r
752 #define SSC_IER (68) // Interrupt Enable Register
\r
753 #define SSC_IDR (72) // Interrupt Disable Register
\r
754 #define SSC_IMR (76) // Interrupt Mask Register
\r
755 #define SSC_RPR (256) // Receive Pointer Register
\r
756 #define SSC_RCR (260) // Receive Counter Register
\r
757 #define SSC_TPR (264) // Transmit Pointer Register
\r
758 #define SSC_TCR (268) // Transmit Counter Register
\r
759 #define SSC_RNPR (272) // Receive Next Pointer Register
\r
760 #define SSC_RNCR (276) // Receive Next Counter Register
\r
761 #define SSC_TNPR (280) // Transmit Next Pointer Register
\r
762 #define SSC_TNCR (284) // Transmit Next Counter Register
\r
763 #define SSC_PTCR (288) // PDC Transfer Control Register
\r
764 #define SSC_PTSR (292) // PDC Transfer Status Register
\r
765 // -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
\r
766 #define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
\r
767 #define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
\r
768 #define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
\r
769 #define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
\r
770 #define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
\r
771 // -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
\r
772 #define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
\r
773 #define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
\r
774 #define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
\r
775 #define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
\r
776 #define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
\r
777 #define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
\r
778 #define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
\r
779 #define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
\r
780 #define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
\r
781 #define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection
\r
782 #define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
\r
783 #define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
\r
784 #define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
\r
785 #define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
\r
786 #define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
\r
787 #define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
\r
788 #define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
\r
789 #define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
\r
790 #define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
\r
791 #define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
\r
792 #define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
\r
793 #define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
\r
794 #define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
\r
795 #define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection
\r
796 #define AT91C_SSC_STTOUT (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection
\r
797 #define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
\r
798 #define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
\r
799 // -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
\r
800 #define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
\r
801 #define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
\r
802 #define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
\r
803 #define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
\r
804 #define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
\r
805 #define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
\r
806 #define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
\r
807 #define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
\r
808 #define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
\r
809 #define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
\r
810 #define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
\r
811 #define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
\r
812 #define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
\r
813 // -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
\r
814 // -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
\r
815 #define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
\r
816 #define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
\r
817 // -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
\r
818 #define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
\r
819 #define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
\r
820 #define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
\r
821 #define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
\r
822 #define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
\r
823 #define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
\r
824 #define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
\r
825 #define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
\r
826 #define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0
\r
827 #define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1
\r
828 #define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
\r
829 #define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
\r
830 #define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
\r
831 #define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
\r
832 // -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
\r
833 // -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
\r
834 // -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
\r
836 // *****************************************************************************
\r
837 // SOFTWARE API DEFINITION FOR Usart
\r
838 // *****************************************************************************
\r
839 // *** Register offset in AT91S_USART structure ***
\r
840 #define US_CR ( 0) // Control Register
\r
841 #define US_MR ( 4) // Mode Register
\r
842 #define US_IER ( 8) // Interrupt Enable Register
\r
843 #define US_IDR (12) // Interrupt Disable Register
\r
844 #define US_IMR (16) // Interrupt Mask Register
\r
845 #define US_CSR (20) // Channel Status Register
\r
846 #define US_RHR (24) // Receiver Holding Register
\r
847 #define US_THR (28) // Transmitter Holding Register
\r
848 #define US_BRGR (32) // Baud Rate Generator Register
\r
849 #define US_RTOR (36) // Receiver Time-out Register
\r
850 #define US_TTGR (40) // Transmitter Time-guard Register
\r
851 #define US_FIDI (64) // FI_DI_Ratio Register
\r
852 #define US_NER (68) // Nb Errors Register
\r
853 #define US_XXR (72) // XON_XOFF Register
\r
854 #define US_IF (76) // IRDA_FILTER Register
\r
855 #define US_RPR (256) // Receive Pointer Register
\r
856 #define US_RCR (260) // Receive Counter Register
\r
857 #define US_TPR (264) // Transmit Pointer Register
\r
858 #define US_TCR (268) // Transmit Counter Register
\r
859 #define US_RNPR (272) // Receive Next Pointer Register
\r
860 #define US_RNCR (276) // Receive Next Counter Register
\r
861 #define US_TNPR (280) // Transmit Next Pointer Register
\r
862 #define US_TNCR (284) // Transmit Next Counter Register
\r
863 #define US_PTCR (288) // PDC Transfer Control Register
\r
864 #define US_PTSR (292) // PDC Transfer Status Register
\r
865 // -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
\r
866 #define AT91C_US_RSTSTA (0x1 << 8) // (USART) Reset Status Bits
\r
867 #define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
\r
868 #define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
\r
869 #define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
\r
870 #define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
\r
871 #define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
\r
872 #define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
\r
873 #define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
\r
874 #define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
\r
875 #define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
\r
876 #define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
\r
877 #define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
\r
878 // -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
\r
879 #define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
\r
880 #define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
\r
881 #define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
\r
882 #define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
\r
883 #define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
\r
884 #define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
\r
885 #define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
\r
886 #define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
\r
887 #define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
\r
888 #define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
\r
889 #define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
\r
890 #define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
\r
891 #define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
\r
892 #define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
\r
893 #define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
\r
894 #define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
\r
895 #define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
\r
896 #define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
\r
897 #define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
\r
898 #define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
\r
899 #define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
\r
900 #define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
\r
901 #define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
\r
902 #define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
\r
903 #define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
\r
904 #define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
\r
905 #define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
\r
906 #define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
\r
907 #define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
\r
908 #define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
\r
909 #define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
\r
910 #define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
\r
911 // -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
\r
912 #define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
\r
913 #define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
\r
914 #define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
\r
915 #define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
\r
916 #define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
\r
917 #define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
\r
918 #define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
\r
919 #define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
\r
920 // -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
\r
921 // -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
\r
922 // -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
\r
923 #define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
\r
924 #define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
\r
925 #define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
\r
926 #define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
\r
928 // *****************************************************************************
\r
929 // SOFTWARE API DEFINITION FOR Two-wire Interface
\r
930 // *****************************************************************************
\r
931 // *** Register offset in AT91S_TWI structure ***
\r
932 #define TWI_CR ( 0) // Control Register
\r
933 #define TWI_MMR ( 4) // Master Mode Register
\r
934 #define TWI_SMR ( 8) // Slave Mode Register
\r
935 #define TWI_IADR (12) // Internal Address Register
\r
936 #define TWI_CWGR (16) // Clock Waveform Generator Register
\r
937 #define TWI_SR (32) // Status Register
\r
938 #define TWI_IER (36) // Interrupt Enable Register
\r
939 #define TWI_IDR (40) // Interrupt Disable Register
\r
940 #define TWI_IMR (44) // Interrupt Mask Register
\r
941 #define TWI_RHR (48) // Receive Holding Register
\r
942 #define TWI_THR (52) // Transmit Holding Register
\r
943 // -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
\r
944 #define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
\r
945 #define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
\r
946 #define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
\r
947 #define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
\r
948 #define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave Transfer Enabled
\r
949 #define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave Transfer Disabled
\r
950 #define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
\r
951 // -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
\r
952 #define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
\r
953 #define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
\r
954 #define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
\r
955 #define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
\r
956 #define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
\r
957 #define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
\r
958 #define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
\r
959 // -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------
\r
960 #define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Device Address
\r
961 // -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
\r
962 #define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
\r
963 #define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
\r
964 #define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
\r
965 // -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
\r
966 #define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed
\r
967 #define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
\r
968 #define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY
\r
969 #define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave Read
\r
970 #define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave Access
\r
971 #define AT91C_TWI_GCACC (0x1 << 5) // (TWI) General Call Access
\r
972 #define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error
\r
973 #define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error
\r
974 #define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged
\r
975 #define AT91C_TWI_ARBLST (0x1 << 9) // (TWI) Arbitration Lost
\r
976 // -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
\r
977 // -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
\r
978 // -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
\r
980 // *****************************************************************************
\r
981 // SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
\r
982 // *****************************************************************************
\r
983 // *** Register offset in AT91S_TC structure ***
\r
984 #define TC_CCR ( 0) // Channel Control Register
\r
985 #define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
\r
986 #define TC_CV (16) // Counter Value
\r
987 #define TC_RA (20) // Register A
\r
988 #define TC_RB (24) // Register B
\r
989 #define TC_RC (28) // Register C
\r
990 #define TC_SR (32) // Status Register
\r
991 #define TC_IER (36) // Interrupt Enable Register
\r
992 #define TC_IDR (40) // Interrupt Disable Register
\r
993 #define TC_IMR (44) // Interrupt Mask Register
\r
994 // -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
\r
995 #define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
\r
996 #define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
\r
997 #define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
\r
998 // -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
\r
999 #define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
\r
1000 #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
\r
1001 #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
\r
1002 #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
\r
1003 #define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
\r
1004 #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
\r
1005 #define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
\r
1006 #define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
\r
1007 #define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
\r
1008 #define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
\r
1009 #define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
\r
1010 #define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
\r
1011 #define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
\r
1012 #define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
\r
1013 #define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
\r
1014 #define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
\r
1015 #define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
\r
1016 #define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
\r
1017 #define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
\r
1018 #define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
\r
1019 #define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
\r
1020 #define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
\r
1021 #define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
\r
1022 #define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
\r
1023 #define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
\r
1024 #define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
\r
1025 #define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
\r
1026 #define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
\r
1027 #define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
\r
1028 #define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
\r
1029 #define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
\r
1030 #define AT91C_TC_EEVT_NONE (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
\r
1031 #define AT91C_TC_EEVT_RISING (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
\r
1032 #define AT91C_TC_EEVT_FALLING (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
\r
1033 #define AT91C_TC_EEVT_BOTH (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
\r
1034 #define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
\r
1035 #define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
\r
1036 #define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
\r
1037 #define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
\r
1038 #define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
\r
1039 #define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
\r
1040 #define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
\r
1041 #define AT91C_TC_WAVE (0x1 << 15) // (TC)
\r
1042 #define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
\r
1043 #define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
\r
1044 #define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
\r
1045 #define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
\r
1046 #define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
\r
1047 #define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
\r
1048 #define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
\r
1049 #define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
\r
1050 #define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
\r
1051 #define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
\r
1052 #define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
\r
1053 #define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
\r
1054 #define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
\r
1055 #define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
\r
1056 #define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
\r
1057 #define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
\r
1058 #define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
\r
1059 #define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
\r
1060 #define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
\r
1061 #define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
\r
1062 #define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
\r
1063 #define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
\r
1064 #define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
\r
1065 #define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
\r
1066 #define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
\r
1067 #define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
\r
1068 #define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
\r
1069 #define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
\r
1070 #define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
\r
1071 #define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
\r
1072 #define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
\r
1073 #define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
\r
1074 #define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
\r
1075 #define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
\r
1076 #define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
\r
1077 #define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
\r
1078 #define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
\r
1079 #define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
\r
1080 #define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
\r
1081 #define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
\r
1082 #define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
\r
1083 #define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
\r
1084 #define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
\r
1085 #define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
\r
1086 #define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
\r
1087 #define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
\r
1088 #define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
\r
1089 #define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
\r
1090 #define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
\r
1091 #define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
\r
1092 // -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
\r
1093 #define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
\r
1094 #define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
\r
1095 #define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
\r
1096 #define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
\r
1097 #define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
\r
1098 #define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
\r
1099 #define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
\r
1100 #define AT91C_TC_ETRCS (0x1 << 7) // (TC) External Trigger
\r
1101 #define AT91C_TC_ETRGS (0x1 << 16) // (TC) Clock Enabling
\r
1102 #define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
\r
1103 #define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
\r
1104 // -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
\r
1105 // -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
\r
1106 // -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
\r
1108 // *****************************************************************************
\r
1109 // SOFTWARE API DEFINITION FOR Timer Counter Interface
\r
1110 // *****************************************************************************
\r
1111 // *** Register offset in AT91S_TCB structure ***
\r
1112 #define TCB_TC0 ( 0) // TC Channel 0
\r
1113 #define TCB_TC1 (64) // TC Channel 1
\r
1114 #define TCB_TC2 (128) // TC Channel 2
\r
1115 #define TCB_BCR (192) // TC Block Control Register
\r
1116 #define TCB_BMR (196) // TC Block Mode Register
\r
1117 // -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
\r
1118 #define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
\r
1119 // -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
\r
1120 #define AT91C_TCB_TC0XC0S (0x1 << 0) // (TCB) External Clock Signal 0 Selection
\r
1121 #define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
\r
1122 #define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
\r
1123 #define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
\r
1124 #define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
\r
1125 #define AT91C_TCB_TC1XC1S (0x1 << 2) // (TCB) External Clock Signal 1 Selection
\r
1126 #define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
\r
1127 #define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
\r
1128 #define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
\r
1129 #define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
\r
1130 #define AT91C_TCB_TC2XC2S (0x1 << 4) // (TCB) External Clock Signal 2 Selection
\r
1131 #define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
\r
1132 #define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
\r
1133 #define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
\r
1134 #define AT91C_TCB_TC2XC2S_TIOA2 (0x3 << 4) // (TCB) TIOA2 connected to XC2
\r
1136 // *****************************************************************************
\r
1137 // SOFTWARE API DEFINITION FOR PWMC Channel Interface
\r
1138 // *****************************************************************************
\r
1139 // *** Register offset in AT91S_PWMC_CH structure ***
\r
1140 #define PWMC_CMR ( 0) // Channel Mode Register
\r
1141 #define PWMC_CDTYR ( 4) // Channel Duty Cycle Register
\r
1142 #define PWMC_CPRDR ( 8) // Channel Period Register
\r
1143 #define PWMC_CCNTR (12) // Channel Counter Register
\r
1144 #define PWMC_CUPDR (16) // Channel Update Register
\r
1145 #define PWMC_Reserved (20) // Reserved
\r
1146 // -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
\r
1147 #define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
\r
1148 #define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH)
\r
1149 #define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH)
\r
1150 #define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH)
\r
1151 #define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment
\r
1152 #define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity
\r
1153 #define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period
\r
1154 // -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
\r
1155 #define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle
\r
1156 // -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
\r
1157 #define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period
\r
1158 // -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
\r
1159 #define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter
\r
1160 // -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
\r
1161 #define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update
\r
1163 // *****************************************************************************
\r
1164 // SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
\r
1165 // *****************************************************************************
\r
1166 // *** Register offset in AT91S_PWMC structure ***
\r
1167 #define PWMC_MR ( 0) // PWMC Mode Register
\r
1168 #define PWMC_ENA ( 4) // PWMC Enable Register
\r
1169 #define PWMC_DIS ( 8) // PWMC Disable Register
\r
1170 #define PWMC_SR (12) // PWMC Status Register
\r
1171 #define PWMC_IER (16) // PWMC Interrupt Enable Register
\r
1172 #define PWMC_IDR (20) // PWMC Interrupt Disable Register
\r
1173 #define PWMC_IMR (24) // PWMC Interrupt Mask Register
\r
1174 #define PWMC_ISR (28) // PWMC Interrupt Status Register
\r
1175 #define PWMC_VR (252) // PWMC Version Register
\r
1176 #define PWMC_CH (512) // PWMC Channel 0
\r
1177 // -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
\r
1178 #define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor.
\r
1179 #define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A
\r
1180 #define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC)
\r
1181 #define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor.
\r
1182 #define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
\r
1183 #define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC)
\r
1184 // -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
\r
1185 #define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0
\r
1186 #define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1
\r
1187 #define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2
\r
1188 #define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3
\r
1189 #define AT91C_PWMC_CHID4 (0x1 << 4) // (PWMC) Channel ID 4
\r
1190 #define AT91C_PWMC_CHID5 (0x1 << 5) // (PWMC) Channel ID 5
\r
1191 #define AT91C_PWMC_CHID6 (0x1 << 6) // (PWMC) Channel ID 6
\r
1192 #define AT91C_PWMC_CHID7 (0x1 << 7) // (PWMC) Channel ID 7
\r
1193 // -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
\r
1194 // -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
\r
1195 // -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
\r
1196 // -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
\r
1197 // -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
\r
1198 // -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
\r
1200 // *****************************************************************************
\r
1201 // SOFTWARE API DEFINITION FOR USB Device Interface
\r
1202 // *****************************************************************************
\r
1203 // *** Register offset in AT91S_UDP structure ***
\r
1204 #define UDP_NUM ( 0) // Frame Number Register
\r
1205 #define UDP_GLBSTATE ( 4) // Global State Register
\r
1206 #define UDP_FADDR ( 8) // Function Address Register
\r
1207 #define UDP_IER (16) // Interrupt Enable Register
\r
1208 #define UDP_IDR (20) // Interrupt Disable Register
\r
1209 #define UDP_IMR (24) // Interrupt Mask Register
\r
1210 #define UDP_ISR (28) // Interrupt Status Register
\r
1211 #define UDP_ICR (32) // Interrupt Clear Register
\r
1212 #define UDP_RSTEP (40) // Reset Endpoint Register
\r
1213 #define UDP_CSR (48) // Endpoint Control and Status Register
\r
1214 #define UDP_FDR (80) // Endpoint FIFO Data Register
\r
1215 // -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
\r
1216 #define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
\r
1217 #define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
\r
1218 #define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
\r
1219 // -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
\r
1220 #define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
\r
1221 #define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
\r
1222 #define AT91C_UDP_RMWUPE (0x1 << 2) // (UDP) Remote Wake Up Enable
\r
1223 #define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
\r
1224 // -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
\r
1225 #define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
\r
1226 #define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
\r
1227 // -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
\r
1228 #define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
\r
1229 #define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
\r
1230 #define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
\r
1231 #define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
\r
1232 #define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
\r
1233 #define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
\r
1234 #define AT91C_UDP_EPINT6 (0x1 << 6) // (UDP) Endpoint 6 Interrupt
\r
1235 #define AT91C_UDP_EPINT7 (0x1 << 7) // (UDP) Endpoint 7 Interrupt
\r
1236 #define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
\r
1237 #define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
\r
1238 #define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
\r
1239 #define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
\r
1240 #define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
\r
1241 // -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
\r
1242 // -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
\r
1243 // -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
\r
1244 #define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
\r
1245 // -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
\r
1246 // -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
\r
1247 #define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
\r
1248 #define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
\r
1249 #define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
\r
1250 #define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
\r
1251 #define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
\r
1252 #define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
\r
1253 #define AT91C_UDP_EP6 (0x1 << 6) // (UDP) Reset Endpoint 6
\r
1254 #define AT91C_UDP_EP7 (0x1 << 7) // (UDP) Reset Endpoint 7
\r
1255 // -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
\r
1256 #define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
\r
1257 #define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
\r
1258 #define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
\r
1259 #define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
\r
1260 #define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
\r
1261 #define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
\r
1262 #define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
\r
1263 #define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
\r
1264 #define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
\r
1265 #define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
\r
1266 #define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
\r
1267 #define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
\r
1268 #define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
\r
1269 #define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
\r
1270 #define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
\r
1271 #define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
\r
1272 #define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
\r
1273 #define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
\r
1274 #define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
\r
1276 // *****************************************************************************
\r
1277 // REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
\r
1278 // *****************************************************************************
\r
1279 // ========== Register definition for SYSC peripheral ==========
\r
1280 #define AT91C_SYSC_SYSC_VRPM (0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register
\r
1281 // ========== Register definition for AIC peripheral ==========
\r
1282 #define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register
\r
1283 #define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register
\r
1284 #define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register
\r
1285 #define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register
\r
1286 #define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register
\r
1287 #define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect)
\r
1288 #define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register
\r
1289 #define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register
\r
1290 #define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register
\r
1291 #define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register
\r
1292 #define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register
\r
1293 #define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register
\r
1294 #define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register
\r
1295 #define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register
\r
1296 #define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register
\r
1297 #define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register
\r
1298 #define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register
\r
1299 #define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register
\r
1300 // ========== Register definition for DBGU peripheral ==========
\r
1301 #define AT91C_DBGU_C2R (0xFFFFF244) // (DBGU) Chip ID2 Register
\r
1302 #define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register
\r
1303 #define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register
\r
1304 #define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register
\r
1305 #define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register
\r
1306 #define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register
\r
1307 #define AT91C_DBGU_C1R (0xFFFFF240) // (DBGU) Chip ID1 Register
\r
1308 #define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register
\r
1309 #define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register
\r
1310 #define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register
\r
1311 #define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register
\r
1312 #define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register
\r
1313 // ========== Register definition for PDC_DBGU peripheral ==========
\r
1314 #define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
\r
1315 #define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
\r
1316 #define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
\r
1317 #define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
\r
1318 #define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
\r
1319 #define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
\r
1320 #define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
\r
1321 #define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
\r
1322 #define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
\r
1323 #define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
\r
1324 // ========== Register definition for PIOA peripheral ==========
\r
1325 #define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register
\r
1326 #define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register
\r
1327 #define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register
\r
1328 #define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register
\r
1329 #define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register
\r
1330 #define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register
\r
1331 #define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register
\r
1332 #define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register
\r
1333 #define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register
\r
1334 #define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register
\r
1335 #define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register
\r
1336 #define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register
\r
1337 #define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register
\r
1338 #define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register
\r
1339 #define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr
\r
1340 #define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register
\r
1341 #define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register
\r
1342 #define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register
\r
1343 #define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pad Pull-up Status Register
\r
1344 #define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register
\r
1345 #define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register
\r
1346 #define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register
\r
1347 #define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register
\r
1348 #define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register
\r
1349 #define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register
\r
1350 #define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register
\r
1351 #define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register
\r
1352 #define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register
\r
1353 #define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register
\r
1354 // ========== Register definition for CKGR peripheral ==========
\r
1355 #define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register
\r
1356 #define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register
\r
1357 #define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register
\r
1358 // ========== Register definition for PMC peripheral ==========
\r
1359 #define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register
\r
1360 #define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register
\r
1361 #define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register
\r
1362 #define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register
\r
1363 #define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
\r
1364 #define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register
\r
1365 #define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register
\r
1366 #define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register
\r
1367 #define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register
\r
1368 #define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register
\r
1369 #define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
\r
1370 #define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
\r
1371 #define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register
\r
1372 #define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register
\r
1373 #define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register
\r
1374 // ========== Register definition for RSTC peripheral ==========
\r
1375 #define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register
\r
1376 #define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register
\r
1377 #define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register
\r
1378 // ========== Register definition for RTTC peripheral ==========
\r
1379 #define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register
\r
1380 #define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register
\r
1381 #define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register
\r
1382 #define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register
\r
1383 // ========== Register definition for PITC peripheral ==========
\r
1384 #define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register
\r
1385 #define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register
\r
1386 #define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register
\r
1387 #define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register
\r
1388 // ========== Register definition for WDTC peripheral ==========
\r
1389 #define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register
\r
1390 #define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register
\r
1391 #define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register
\r
1392 // ========== Register definition for MC peripheral ==========
\r
1393 #define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register
\r
1394 #define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register
\r
1395 #define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register
\r
1396 #define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register
\r
1397 #define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register
\r
1398 #define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register
\r
1399 // ========== Register definition for PDC_SPI peripheral ==========
\r
1400 #define AT91C_SPI_PTCR (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
\r
1401 #define AT91C_SPI_TNPR (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
\r
1402 #define AT91C_SPI_RNPR (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
\r
1403 #define AT91C_SPI_TPR (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
\r
1404 #define AT91C_SPI_RPR (0xFFFE0100) // (PDC_SPI) Receive Pointer Register
\r
1405 #define AT91C_SPI_PTSR (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
\r
1406 #define AT91C_SPI_TNCR (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
\r
1407 #define AT91C_SPI_RNCR (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
\r
1408 #define AT91C_SPI_TCR (0xFFFE010C) // (PDC_SPI) Transmit Counter Register
\r
1409 #define AT91C_SPI_RCR (0xFFFE0104) // (PDC_SPI) Receive Counter Register
\r
1410 // ========== Register definition for SPI peripheral ==========
\r
1411 #define AT91C_SPI_CSR (0xFFFE0030) // (SPI) Chip Select Register
\r
1412 #define AT91C_SPI_IDR (0xFFFE0018) // (SPI) Interrupt Disable Register
\r
1413 #define AT91C_SPI_SR (0xFFFE0010) // (SPI) Status Register
\r
1414 #define AT91C_SPI_RDR (0xFFFE0008) // (SPI) Receive Data Register
\r
1415 #define AT91C_SPI_CR (0xFFFE0000) // (SPI) Control Register
\r
1416 #define AT91C_SPI_IMR (0xFFFE001C) // (SPI) Interrupt Mask Register
\r
1417 #define AT91C_SPI_IER (0xFFFE0014) // (SPI) Interrupt Enable Register
\r
1418 #define AT91C_SPI_TDR (0xFFFE000C) // (SPI) Transmit Data Register
\r
1419 #define AT91C_SPI_MR (0xFFFE0004) // (SPI) Mode Register
\r
1420 // ========== Register definition for PDC_ADC peripheral ==========
\r
1421 #define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
\r
1422 #define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
\r
1423 #define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
\r
1424 #define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
\r
1425 #define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
\r
1426 #define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
\r
1427 #define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
\r
1428 #define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
\r
1429 #define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
\r
1430 #define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register
\r
1431 // ========== Register definition for ADC peripheral ==========
\r
1432 #define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
\r
1433 #define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4
\r
1434 #define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2
\r
1435 #define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0
\r
1436 #define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7
\r
1437 #define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1
\r
1438 #define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3
\r
1439 #define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5
\r
1440 #define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register
\r
1441 #define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6
\r
1442 #define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register
\r
1443 #define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register
\r
1444 #define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register
\r
1445 #define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
\r
1446 #define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register
\r
1447 #define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register
\r
1448 #define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
\r
1449 #define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register
\r
1450 // ========== Register definition for PDC_SSC peripheral ==========
\r
1451 #define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
\r
1452 #define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
\r
1453 #define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
\r
1454 #define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
\r
1455 #define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
\r
1456 #define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
\r
1457 #define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
\r
1458 #define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
\r
1459 #define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
\r
1460 #define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register
\r
1461 // ========== Register definition for SSC peripheral ==========
\r
1462 #define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register
\r
1463 #define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register
\r
1464 #define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register
\r
1465 #define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register
\r
1466 #define AT91C_SSC_RC0R (0xFFFD4038) // (SSC) Receive Compare 0 Register
\r
1467 #define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register
\r
1468 #define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register
\r
1469 #define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register
\r
1470 #define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister
\r
1471 #define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register
\r
1472 #define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register
\r
1473 #define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register
\r
1474 #define AT91C_SSC_RC1R (0xFFFD403C) // (SSC) Receive Compare 1 Register
\r
1475 #define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register
\r
1476 #define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register
\r
1477 #define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register
\r
1478 // ========== Register definition for PDC_US1 peripheral ==========
\r
1479 #define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
\r
1480 #define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
\r
1481 #define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
\r
1482 #define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register
\r
1483 #define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register
\r
1484 #define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
\r
1485 #define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
\r
1486 #define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
\r
1487 #define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
\r
1488 #define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register
\r
1489 // ========== Register definition for US1 peripheral ==========
\r
1490 #define AT91C_US1_XXR (0xFFFC4048) // (US1) XON_XOFF Register
\r
1491 #define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register
\r
1492 #define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register
\r
1493 #define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register
\r
1494 #define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register
\r
1495 #define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register
\r
1496 #define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register
\r
1497 #define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register
\r
1498 #define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register
\r
1499 #define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register
\r
1500 #define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register
\r
1501 #define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register
\r
1502 #define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register
\r
1503 #define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register
\r
1504 #define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register
\r
1505 // ========== Register definition for PDC_US0 peripheral ==========
\r
1506 #define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
\r
1507 #define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
\r
1508 #define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
\r
1509 #define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
\r
1510 #define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register
\r
1511 #define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
\r
1512 #define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
\r
1513 #define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
\r
1514 #define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register
\r
1515 #define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register
\r
1516 // ========== Register definition for US0 peripheral ==========
\r
1517 #define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register
\r
1518 #define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register
\r
1519 #define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register
\r
1520 #define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register
\r
1521 #define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register
\r
1522 #define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register
\r
1523 #define AT91C_US0_XXR (0xFFFC0048) // (US0) XON_XOFF Register
\r
1524 #define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register
\r
1525 #define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register
\r
1526 #define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register
\r
1527 #define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register
\r
1528 #define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register
\r
1529 #define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register
\r
1530 #define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register
\r
1531 #define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register
\r
1532 // ========== Register definition for TWI peripheral ==========
\r
1533 #define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register
\r
1534 #define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register
\r
1535 #define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register
\r
1536 #define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register
\r
1537 #define AT91C_TWI_SMR (0xFFFB8008) // (TWI) Slave Mode Register
\r
1538 #define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register
\r
1539 #define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register
\r
1540 #define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register
\r
1541 #define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register
\r
1542 #define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register
\r
1543 #define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register
\r
1544 // ========== Register definition for TC2 peripheral ==========
\r
1545 #define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register
\r
1546 #define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register
\r
1547 #define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C
\r
1548 #define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A
\r
1549 #define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
\r
1550 #define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register
\r
1551 #define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register
\r
1552 #define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B
\r
1553 #define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value
\r
1554 #define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register
\r
1555 // ========== Register definition for TC1 peripheral ==========
\r
1556 #define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register
\r
1557 #define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register
\r
1558 #define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C
\r
1559 #define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A
\r
1560 #define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
\r
1561 #define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register
\r
1562 #define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register
\r
1563 #define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B
\r
1564 #define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value
\r
1565 #define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register
\r
1566 // ========== Register definition for TC0 peripheral ==========
\r
1567 #define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register
\r
1568 #define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register
\r
1569 #define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C
\r
1570 #define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A
\r
1571 #define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
\r
1572 #define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register
\r
1573 #define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register
\r
1574 #define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B
\r
1575 #define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value
\r
1576 #define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register
\r
1577 // ========== Register definition for TCB peripheral ==========
\r
1578 #define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register
\r
1579 #define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register
\r
1580 // ========== Register definition for PWMC_CH3 peripheral ==========
\r
1581 #define AT91C_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register
\r
1582 #define AT91C_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register
\r
1583 #define AT91C_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
\r
1584 #define AT91C_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved
\r
1585 #define AT91C_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
\r
1586 #define AT91C_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
\r
1587 // ========== Register definition for PWMC_CH2 peripheral ==========
\r
1588 #define AT91C_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register
\r
1589 #define AT91C_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register
\r
1590 #define AT91C_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
\r
1591 #define AT91C_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved
\r
1592 #define AT91C_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
\r
1593 #define AT91C_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
\r
1594 // ========== Register definition for PWMC_CH1 peripheral ==========
\r
1595 #define AT91C_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register
\r
1596 #define AT91C_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register
\r
1597 #define AT91C_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
\r
1598 #define AT91C_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved
\r
1599 #define AT91C_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
\r
1600 #define AT91C_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
\r
1601 // ========== Register definition for PWMC_CH0 peripheral ==========
\r
1602 #define AT91C_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register
\r
1603 #define AT91C_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register
\r
1604 #define AT91C_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
\r
1605 #define AT91C_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved
\r
1606 #define AT91C_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
\r
1607 #define AT91C_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
\r
1608 // ========== Register definition for PWMC peripheral ==========
\r
1609 #define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register
\r
1610 #define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
\r
1611 #define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
\r
1612 #define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register
\r
1613 #define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register
\r
1614 #define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
\r
1615 #define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register
\r
1616 #define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register
\r
1617 #define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
\r
1618 // ========== Register definition for UDP peripheral ==========
\r
1619 #define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register
\r
1620 #define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register
\r
1621 #define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register
\r
1622 #define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
\r
1623 #define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register
\r
1624 #define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register
\r
1625 #define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register
\r
1626 #define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register
\r
1627 #define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register
\r
1628 #define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register
\r
1629 #define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register
\r
1631 // *****************************************************************************
\r
1632 // PIO DEFINITIONS FOR AT91SAM7S64
\r
1633 // *****************************************************************************
\r
1634 #define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
\r
1635 #define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0
\r
1636 #define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A
\r
1637 #define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
\r
1638 #define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1
\r
1639 #define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B
\r
1640 #define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
\r
1641 #define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data
\r
1642 #define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2
\r
1643 #define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
\r
1644 #define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0
\r
1645 #define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0
\r
1646 #define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
\r
1647 #define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave
\r
1648 #define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1
\r
1649 #define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
\r
1650 #define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave
\r
1651 #define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2
\r
1652 #define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
\r
1653 #define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock
\r
1654 #define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3
\r
1655 #define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
\r
1656 #define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync
\r
1657 #define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A
\r
1658 #define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
\r
1659 #define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock
\r
1660 #define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B
\r
1661 #define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
\r
1662 #define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data
\r
1663 #define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1
\r
1664 #define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
\r
1665 #define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data
\r
1666 #define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2
\r
1667 #define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
\r
1668 #define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock
\r
1669 #define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input
\r
1670 #define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
\r
1671 #define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2
\r
1672 #define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock
\r
1673 #define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
\r
1674 #define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync
\r
1675 #define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0
\r
1676 #define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
\r
1677 #define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data
\r
1678 #define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1
\r
1679 #define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
\r
1680 #define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data
\r
1681 #define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3
\r
1682 #define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
\r
1683 #define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock
\r
1684 #define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0
\r
1685 #define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
\r
1686 #define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send
\r
1687 #define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1
\r
1688 #define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
\r
1689 #define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send
\r
1690 #define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2
\r
1691 #define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
\r
1692 #define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect
\r
1693 #define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A
\r
1694 #define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
\r
1695 #define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready
\r
1696 #define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B
\r
1697 #define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
\r
1698 #define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready
\r
1699 #define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input
\r
1700 #define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
\r
1701 #define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator
\r
1702 #define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input
\r
1703 #define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
\r
1704 #define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data
\r
1705 #define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3
\r
1706 #define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
\r
1707 #define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1
\r
1708 #define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2
\r
1709 #define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31
\r
1710 #define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1
\r
1711 #define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2
\r
1712 #define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
\r
1713 #define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock
\r
1714 #define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input
\r
1715 #define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
\r
1716 #define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data
\r
1717 #define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3
\r
1718 #define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
\r
1719 #define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data
\r
1720 #define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0
\r
1721 #define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
\r
1722 #define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send
\r
1723 #define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3
\r
1724 #define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
\r
1725 #define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send
\r
1726 #define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger
\r
1727 #define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
\r
1728 #define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data
\r
1729 #define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1
\r
1731 // *****************************************************************************
\r
1732 // PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
\r
1733 // *****************************************************************************
\r
1734 #define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
\r
1735 #define AT91C_ID_SYS ( 1) // System Peripheral
\r
1736 #define AT91C_ID_PIOA ( 2) // Parallel IO Controller
\r
1737 #define AT91C_ID_3_Reserved ( 3) // Reserved
\r
1738 #define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter
\r
1739 #define AT91C_ID_SPI ( 5) // Serial Peripheral Interface
\r
1740 #define AT91C_ID_US0 ( 6) // USART 0
\r
1741 #define AT91C_ID_US1 ( 7) // USART 1
\r
1742 #define AT91C_ID_SSC ( 8) // Serial Synchronous Controller
\r
1743 #define AT91C_ID_TWI ( 9) // Two-Wire Interface
\r
1744 #define AT91C_ID_PWMC (10) // PWM Controller
\r
1745 #define AT91C_ID_UDP (11) // USB Device Port
\r
1746 #define AT91C_ID_TC0 (12) // Timer Counter 0
\r
1747 #define AT91C_ID_TC1 (13) // Timer Counter 1
\r
1748 #define AT91C_ID_TC2 (14) // Timer Counter 2
\r
1749 #define AT91C_ID_15_Reserved (15) // Reserved
\r
1750 #define AT91C_ID_16_Reserved (16) // Reserved
\r
1751 #define AT91C_ID_17_Reserved (17) // Reserved
\r
1752 #define AT91C_ID_18_Reserved (18) // Reserved
\r
1753 #define AT91C_ID_19_Reserved (19) // Reserved
\r
1754 #define AT91C_ID_20_Reserved (20) // Reserved
\r
1755 #define AT91C_ID_21_Reserved (21) // Reserved
\r
1756 #define AT91C_ID_22_Reserved (22) // Reserved
\r
1757 #define AT91C_ID_23_Reserved (23) // Reserved
\r
1758 #define AT91C_ID_24_Reserved (24) // Reserved
\r
1759 #define AT91C_ID_25_Reserved (25) // Reserved
\r
1760 #define AT91C_ID_26_Reserved (26) // Reserved
\r
1761 #define AT91C_ID_27_Reserved (27) // Reserved
\r
1762 #define AT91C_ID_28_Reserved (28) // Reserved
\r
1763 #define AT91C_ID_29_Reserved (29) // Reserved
\r
1764 #define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
\r
1765 #define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
\r
1767 // *****************************************************************************
\r
1768 // BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
\r
1769 // *****************************************************************************
\r
1770 #define AT91C_BASE_SYSC (0xFFFFF000) // (SYSC) Base Address
\r
1771 #define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address
\r
1772 #define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address
\r
1773 #define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address
\r
1774 #define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address
\r
1775 #define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address
\r
1776 #define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address
\r
1777 #define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address
\r
1778 #define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address
\r
1779 #define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address
\r
1780 #define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address
\r
1781 #define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address
\r
1782 #define AT91C_BASE_PDC_SPI (0xFFFE0100) // (PDC_SPI) Base Address
\r
1783 #define AT91C_BASE_SPI (0xFFFE0000) // (SPI) Base Address
\r
1784 #define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address
\r
1785 #define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address
\r
1786 #define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address
\r
1787 #define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address
\r
1788 #define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address
\r
1789 #define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address
\r
1790 #define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address
\r
1791 #define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address
\r
1792 #define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address
\r
1793 #define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address
\r
1794 #define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address
\r
1795 #define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address
\r
1796 #define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address
\r
1797 #define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address
\r
1798 #define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address
\r
1799 #define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address
\r
1800 #define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address
\r
1801 #define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address
\r
1802 #define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address
\r
1804 // *****************************************************************************
\r
1805 // MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
\r
1806 // *****************************************************************************
\r
1807 #define AT91C_ISRAM (0x00200000) // Internal SRAM base address
\r
1808 #define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbyte)
\r
1809 #define AT91C_IFLASH (0x00100000) // Internal ROM base address
\r
1810 #define AT91C_IFLASH_SIZE (0x00010000) // Internal ROM size in byte (64 Kbyte)
\r