2 * FreeRTOS Kernel V10.2.1
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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29 * The FreeRTOS kernel's RISC-V port is split between the the code that is
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30 * common across all currently supported RISC-V chips (implementations of the
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31 * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
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33 * + The code that is common to all RISC-V chips is implemented in
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34 * FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
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35 * portASM.S file because the same file is used no matter which RISC-V chip is
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38 * + The code that tailors the kernel's RISC-V port to a specific RISC-V
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39 * chip is implemented in freertos_risc_v_chip_specific_extensions.h. There
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40 * is one freertos_risc_v_chip_specific_extensions.h that can be used with any
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41 * RISC-V chip that both includes a standard CLINT and does not add to the
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42 * base set of RISC-V registers. There are additional
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43 * freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
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44 * that do not include a standard CLINT or do add to the base set of RISC-V
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47 * CARE MUST BE TAKEN TO INCLDUE THE CORRECT
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48 * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
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49 * IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h
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50 * header file ensure the path to the correct header file is in the assembler's
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53 * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
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54 * that include a standard CLINT and do not add to the base set of RISC-V
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58 #if __riscv_xlen == 64
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59 #define portWORD_SIZE 8
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62 #elif __riscv_xlen == 32
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65 #define portWORD_SIZE 4
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67 #error Assembler did not define __riscv_xlen
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70 #include "freertos_risc_v_chip_specific_extensions.h"
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72 /* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
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74 #if defined( portasmHAS_CLINT ) && defined( portasmHAS_MTIME )
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75 #error The portasmHAS_CLINT constant has been depracted. Please replace it with portasmHAS_CLINT. portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once.
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78 #ifdef portasmHAS_CLINT
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79 #warning The portasmHAS_CLINT constant has been depracted. Please replace it with portasmHAS_CLINT. For now portasmHAS_MTIME is derived from portasmHAS_CLINT.
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80 #define portasmHAS_MTIME portasmHAS_CLINT
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83 #ifndef portasmHAS_MTIME
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84 #error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present).
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87 #ifndef portasmHANDLE_INTERRUPT
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88 #error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file.
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91 /* CSR definitions. */
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92 #define CSR_MSTATUS 0x300
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93 #define CSR_MTVEC 0x305
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94 #define CSR_MEPC 0x341
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95 #define CSR_MCAUSE 0x342
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98 /* Only the standard core registers are stored by default. Any additional
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99 registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
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100 portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
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101 specific version of freertos_risc_v_chip_specific_extensions.h. See the notes
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102 at the top of this file. */
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103 #define portCONTEXT_SIZE ( 30 * portWORD_SIZE )
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105 PUBLIC xPortStartFirstTask
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106 PUBLIC freertos_risc_v_trap_handler
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107 PUBLIC pxPortInitialiseStack
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108 EXTERN pxCurrentTCB
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109 EXTERN ulPortTrapHandler
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110 EXTERN vTaskSwitchContext
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111 EXTERN xTaskIncrementTick
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112 EXTERN Timer_IRQHandler
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113 EXTERN pullMachineTimerCompareRegister
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114 EXTERN pullNextTime
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115 EXTERN uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
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116 EXTERN xISRStackTop
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117 EXTERN portasmHANDLE_INTERRUPT
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119 /*-----------------------------------------------------------*/
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121 SECTION `.text`:CODE:NOROOT(2)
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124 freertos_risc_v_trap_handler:
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125 addi sp, sp, -portCONTEXT_SIZE
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126 store_x x1, 1 * portWORD_SIZE( sp )
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127 store_x x5, 2 * portWORD_SIZE( sp )
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128 store_x x6, 3 * portWORD_SIZE( sp )
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129 store_x x7, 4 * portWORD_SIZE( sp )
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130 store_x x8, 5 * portWORD_SIZE( sp )
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131 store_x x9, 6 * portWORD_SIZE( sp )
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132 store_x x10, 7 * portWORD_SIZE( sp )
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133 store_x x11, 8 * portWORD_SIZE( sp )
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134 store_x x12, 9 * portWORD_SIZE( sp )
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135 store_x x13, 10 * portWORD_SIZE( sp )
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136 store_x x14, 11 * portWORD_SIZE( sp )
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137 store_x x15, 12 * portWORD_SIZE( sp )
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138 store_x x16, 13 * portWORD_SIZE( sp )
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139 store_x x17, 14 * portWORD_SIZE( sp )
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140 store_x x18, 15 * portWORD_SIZE( sp )
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141 store_x x19, 16 * portWORD_SIZE( sp )
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142 store_x x20, 17 * portWORD_SIZE( sp )
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143 store_x x21, 18 * portWORD_SIZE( sp )
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144 store_x x22, 19 * portWORD_SIZE( sp )
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145 store_x x23, 20 * portWORD_SIZE( sp )
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146 store_x x24, 21 * portWORD_SIZE( sp )
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147 store_x x25, 22 * portWORD_SIZE( sp )
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148 store_x x26, 23 * portWORD_SIZE( sp )
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149 store_x x27, 24 * portWORD_SIZE( sp )
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150 store_x x28, 25 * portWORD_SIZE( sp )
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151 store_x x29, 26 * portWORD_SIZE( sp )
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152 store_x x30, 27 * portWORD_SIZE( sp )
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153 store_x x31, 28 * portWORD_SIZE( sp )
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155 csrr t0, CSR_MSTATUS /* Required for MPIE bit. */
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156 store_x t0, 29 * portWORD_SIZE( sp )
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158 portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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160 load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */
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161 store_x sp, 0( t0 ) /* Write sp to first TCB member. */
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163 csrr a0, CSR_MCAUSE
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166 test_if_asynchronous:
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167 srli a2, a0, __riscv_xlen - 1 /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */
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168 beq a2, x0, handle_synchronous /* Branch past interrupt handing if not asynchronous. */
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169 store_x a1, 0( sp ) /* Asynch so save unmodified exception return address. */
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171 handle_asynchronous:
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173 #if( portasmHAS_MTIME != 0 )
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175 test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
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179 slli t0, t0, __riscv_xlen - 1 /* LSB is already set, shift into MSB. Shift 31 on 32-bit or 63 on 64-bit cores. */
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180 addi t1, t0, 7 /* 0x8000[]0007 == machine timer interrupt. */
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181 bne a0, t1, test_if_external_interrupt
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183 load_x t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */
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184 load_x t1, pullNextTime /* Load the address of ullNextTime into t1. */
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186 #if( __riscv_xlen == 32 )
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188 /* Update the 64-bit mtimer compare match value in two 32-bit writes. */
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190 lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */
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191 lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */
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192 sw t4, 0(t0) /* Low word no smaller than old value to start with - will be overwritten below. */
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193 sw t3, 4(t0) /* Store high word of ullNextTime into compare register. No smaller than new value. */
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194 sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */
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195 lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
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196 add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
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197 sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */
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198 add t6, t3, t5 /* Add overflow to high word of ullNextTime. */
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199 sw t4, 0(t1) /* Store new low word of ullNextTime. */
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200 sw t6, 4(t1) /* Store new high word of ullNextTime. */
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202 #endif /* __riscv_xlen == 32 */
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204 #if( __riscv_xlen == 64 )
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206 /* Update the 64-bit mtimer compare match value. */
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207 ld t2, 0(t1) /* Load ullNextTime into t2. */
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208 sd t2, 0(t0) /* Store ullNextTime into compare register. */
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209 ld t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
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210 add t4, t0, t2 /* Add ullNextTime to the timer increments for one tick. */
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211 sd t4, 0(t1) /* Store ullNextTime. */
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213 #endif /* __riscv_xlen == 64 */
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215 load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
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216 jal xTaskIncrementTick
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217 beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */
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218 jal vTaskSwitchContext
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221 test_if_external_interrupt: /* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */
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222 addi t1, t1, 4 /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
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223 bne a0, t1, as_yet_unhandled /* Something as yet unhandled. */
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225 #endif /* portasmHAS_MTIME */
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227 load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
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228 jal portasmHANDLE_INTERRUPT /* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */
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231 handle_synchronous:
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232 addi a1, a1, 4 /* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */
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233 store_x a1, 0( sp ) /* Save updated exception return address. */
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235 test_if_environment_call:
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236 li t0, 11 /* 11 == environment call. */
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237 bne a0, t0, is_exception /* Not an M environment call, so some other exception. */
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238 load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
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239 jal vTaskSwitchContext
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243 csrr t0, CSR_MCAUSE /* For viewing in the debugger only. */
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244 csrr t1, CSR_MEPC /* For viewing in the debugger only */
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245 csrr t2, CSR_MSTATUS
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246 j is_exception /* No other exceptions handled yet. */
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249 csrr t0, mcause /* For viewing in the debugger only. */
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253 load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */
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254 load_x sp, 0( t1 ) /* Read sp from first TCB member. */
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256 /* Load mret with the address of the next instruction in the task to run next. */
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260 portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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262 /* Load mstatus with the interrupt enable bits used by the task. */
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263 load_x t0, 29 * portWORD_SIZE( sp )
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264 csrw CSR_MSTATUS, t0 /* Required for MPIE bit. */
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266 load_x x1, 1 * portWORD_SIZE( sp )
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267 load_x x5, 2 * portWORD_SIZE( sp ) /* t0 */
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268 load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */
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269 load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
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270 load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
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271 load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
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272 load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
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273 load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
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274 load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
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275 load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
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276 load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
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277 load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
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278 load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
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279 load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
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280 load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
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281 load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
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282 load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
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283 load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
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284 load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
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285 load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
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286 load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
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287 load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
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288 load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
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289 load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
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290 load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
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291 load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
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292 load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
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293 load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
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294 addi sp, sp, portCONTEXT_SIZE
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298 /*-----------------------------------------------------------*/
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300 xPortStartFirstTask:
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302 #if( portasmHAS_MTIME != 0 )
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303 /* If there is a clint then interrupts can branch directly to the FreeRTOS
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304 trap handler. Otherwise the interrupt controller will need to be configured
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305 outside of this file. */
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306 la t0, freertos_risc_v_trap_handler
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308 #endif /* portasmHAS_CLILNT */
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310 load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */
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311 load_x sp, 0( sp ) /* Read sp from first TCB member. */
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313 load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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315 portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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317 load_x t0, 29 * portWORD_SIZE( sp ) /* mstatus */
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318 addi t0, t0, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
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319 csrrw x0, CSR_MSTATUS, t0 /* Interrupts enabled from here! */
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321 load_x x5, 2 * portWORD_SIZE( sp ) /* t0 */
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322 load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */
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323 load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
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324 load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
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325 load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
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326 load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
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327 load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
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328 load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
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329 load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
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330 load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
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331 load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
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332 load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
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333 load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
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334 load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
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335 load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
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336 load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
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337 load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
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338 load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
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339 load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
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340 load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
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341 load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
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342 load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
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343 load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
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344 load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
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345 load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
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346 load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
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347 load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
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348 addi sp, sp, portCONTEXT_SIZE
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351 /*-----------------------------------------------------------*/
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354 * Unlike other ports pxPortInitialiseStack() is written in assembly code as it
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355 * needs access to the portasmADDITIONAL_CONTEXT_SIZE constant. The prototype
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356 * for the function is as per the other ports:
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357 * StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
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359 * As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
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360 * a1, and pvParameters in a2. The new top of stack is passed out in a0.
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362 * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
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363 * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
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365 * Register ABI Name Description Saver
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366 * x0 zero Hard-wired zero -
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367 * x1 ra Return address Caller
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368 * x2 sp Stack pointer Callee
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369 * x3 gp Global pointer -
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370 * x4 tp Thread pointer -
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371 * x5-7 t0-2 Temporaries Caller
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372 * x8 s0/fp Saved register/Frame pointer Callee
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373 * x9 s1 Saved register Callee
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374 * x10-11 a0-1 Function Arguments/return values Caller
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375 * x12-17 a2-7 Function arguments Caller
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376 * x18-27 s2-11 Saved registers Callee
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377 * x28-31 t3-6 Temporaries Caller
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379 * The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
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380 * where the global and thread pointers are currently assumed to be constant so
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411 * portTASK_RETURN_ADDRESS
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412 * [chip specific registers go here]
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415 pxPortInitialiseStack:
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417 csrr t0, CSR_MSTATUS /* Obtain current mstatus value. */
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418 addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
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420 or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
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422 addi a0, a0, -portWORD_SIZE
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423 store_x t0, 0(a0) /* mstatus onto the stack. */
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424 addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */
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425 store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
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426 addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */
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427 store_x x0, 0(a0) /* Return address onto the stack, could be portTASK_RETURN_ADDRESS */
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428 addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
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429 chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
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430 beq t0, x0, no_more_regs /* No more chip specific registers to save. */
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431 addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
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432 store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */
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433 addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
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434 j chip_specific_stack_frame /* Until no more chip specific registers. */
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436 addi a0, a0, -portWORD_SIZE
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437 store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
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440 /*-----------------------------------------------------------*/
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