2 FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 /*-----------------------------------------------------------
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71 * Implementation of functions defined in portable.h for the SH2A port.
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72 *----------------------------------------------------------*/
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74 /* Standard C includes. */
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77 /* Scheduler includes. */
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78 #include "FreeRTOS.h"
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81 /* Library includes. */
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84 /* Hardware specifics. */
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85 #include "iorx111.h"
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87 /*-----------------------------------------------------------*/
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89 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
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90 PSW is set with U and I set, and PM and IPL clear. */
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91 #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
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93 /* The peripheral clock is divided by this value before being supplying the
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95 #if ( configUSE_TICKLESS_IDLE == 0 )
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96 /* If tickless idle is not used then the divisor can be fixed. */
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97 #define portCLOCK_DIVISOR 8UL
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98 #elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
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99 #define portCLOCK_DIVISOR 512UL
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100 #elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
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101 #define portCLOCK_DIVISOR 128UL
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102 #elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
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103 #define portCLOCK_DIVISOR 32UL
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105 #define portCLOCK_DIVISOR 8UL
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109 /* Keys required to lock and unlock access to certain system registers
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111 #define portUNLOCK_KEY 0xA50B
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112 #define portLOCK_KEY 0xA500
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114 /*-----------------------------------------------------------*/
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117 * Function to start the first task executing - written in asm code as direct
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118 * access to registers is required.
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120 extern void prvStartFirstTask( void );
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123 * The tick ISR handler. The peripheral used is configured by the application
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124 * via a hook/callback function.
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126 __interrupt static void prvTickISR( void );
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129 * Sets up the periodic ISR used for the RTOS tick using the CMT.
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130 * The application writer can define configSETUP_TICK_INTERRUPT() (in
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131 * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
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132 * in place of prvSetupTimerInterrupt().
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134 static void prvSetupTimerInterrupt( void );
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135 #ifndef configSETUP_TICK_INTERRUPT
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136 /* The user has not provided their own tick interrupt configuration so use
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137 the definition in this file (which uses the interval timer). */
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138 #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
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139 #endif /* configSETUP_TICK_INTERRUPT */
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142 * Called after the sleep mode registers have been configured, prvSleep()
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143 * executes the pre and post sleep macros, and actually calls the wait
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146 #if configUSE_TICKLESS_IDLE == 1
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147 static void prvSleep( TickType_t xExpectedIdleTime );
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148 #endif /* configUSE_TICKLESS_IDLE */
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150 /*-----------------------------------------------------------*/
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152 extern void *pxCurrentTCB;
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154 /*-----------------------------------------------------------*/
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156 /* Calculate how many clock increments make up a single tick period. */
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157 static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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159 #if configUSE_TICKLESS_IDLE == 1
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161 /* Holds the maximum number of ticks that can be suppressed - which is
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162 basically how far into the future an interrupt can be generated. Set
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163 during initialisation. This is the maximum possible value that the
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164 compare match register can hold divided by ulMatchValueForOneTick. */
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165 static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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167 /* Flag set from the tick interrupt to allow the sleep processing to know if
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168 sleep mode was exited because of a tick interrupt, or an interrupt
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169 generated by something else. */
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170 static volatile uint32_t ulTickFlag = pdFALSE;
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172 /* The CMT counter is stopped temporarily each time it is re-programmed.
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173 The following constant offsets the CMT counter match value by the number of
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174 CMT counts that would typically be missed while the counter was stopped to
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175 compensate for the lost time. The large difference between the divided CMT
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176 clock and the CPU clock means it is likely ulStoppedTimerCompensation will
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177 equal zero - and be optimised away. */
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178 static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
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182 /*-----------------------------------------------------------*/
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185 * See header file for description.
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187 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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189 /* Offset to end up on 8 byte boundary. */
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192 /* R0 is not included as it is the stack pointer. */
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193 *pxTopOfStack = 0x00;
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195 *pxTopOfStack = 0x00;
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197 *pxTopOfStack = portINITIAL_PSW;
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199 *pxTopOfStack = ( StackType_t ) pxCode;
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201 /* When debugging it can be useful if every register is set to a known
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202 value. Otherwise code space can be saved by just setting the registers
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203 that need to be set. */
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204 #ifdef USE_FULL_REGISTER_INITIALISATION
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207 *pxTopOfStack = 0x12345678; /* r15. */
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209 *pxTopOfStack = 0xaaaabbbb;
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211 *pxTopOfStack = 0xdddddddd;
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213 *pxTopOfStack = 0xcccccccc;
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215 *pxTopOfStack = 0xbbbbbbbb;
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217 *pxTopOfStack = 0xaaaaaaaa;
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219 *pxTopOfStack = 0x99999999;
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221 *pxTopOfStack = 0x88888888;
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223 *pxTopOfStack = 0x77777777;
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225 *pxTopOfStack = 0x66666666;
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227 *pxTopOfStack = 0x55555555;
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229 *pxTopOfStack = 0x44444444;
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231 *pxTopOfStack = 0x33333333;
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233 *pxTopOfStack = 0x22222222;
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238 /* Leave space for the registers that will get popped from the stack
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239 when the task first starts executing. */
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240 pxTopOfStack -= 15;
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244 *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
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246 *pxTopOfStack = 0x12345678; /* Accumulator. */
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248 *pxTopOfStack = 0x87654321; /* Accumulator. */
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250 return pxTopOfStack;
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252 /*-----------------------------------------------------------*/
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254 BaseType_t xPortStartScheduler( void )
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256 /* Use pxCurrentTCB just so it does not get optimised away. */
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257 if( pxCurrentTCB != NULL )
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259 /* Call an application function to set up the timer that will generate
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260 the tick interrupt. This way the application can decide which
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261 peripheral to use. If tickless mode is used then the default
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262 implementation defined in this file (which uses CMT0) should not be
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264 configSETUP_TICK_INTERRUPT();
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266 /* Enable the software interrupt. */
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267 _IEN( _ICU_SWINT ) = 1;
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269 /* Ensure the software interrupt is clear. */
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270 _IR( _ICU_SWINT ) = 0;
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272 /* Ensure the software interrupt is set to the kernel priority. */
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273 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
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275 /* Start the first task. */
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276 prvStartFirstTask();
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279 /* Execution should not reach here as the tasks are now running!
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280 prvSetupTimerInterrupt() is called here to prevent the compiler outputting
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281 a warning about a statically declared function not being referenced in the
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282 case that the application writer has provided their own tick interrupt
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283 configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
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284 their own routine will be called in place of prvSetupTimerInterrupt()). */
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285 prvSetupTimerInterrupt();
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287 /* Should not get here. */
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290 /*-----------------------------------------------------------*/
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292 #pragma vector = configTICK_VECTOR
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293 __interrupt static void prvTickISR( void )
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295 /* Re-enable interrupts. */
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296 __enable_interrupt();
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298 /* Increment the tick, and perform any processing the new tick value
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300 __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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302 if( xTaskIncrementTick() != pdFALSE )
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307 __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
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309 #if configUSE_TICKLESS_IDLE == 1
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311 /* The CPU woke because of a tick. */
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312 ulTickFlag = pdTRUE;
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314 /* If this is the first tick since exiting tickless mode then the CMT
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315 compare match value needs resetting. */
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316 CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
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320 /*-----------------------------------------------------------*/
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322 void vPortEndScheduler( void )
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324 /* Not implemented in ports where there is nothing to return to.
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325 Artificially force an assert. */
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326 configASSERT( pxCurrentTCB == NULL );
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328 /*-----------------------------------------------------------*/
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330 static void prvSetupTimerInterrupt( void )
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333 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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339 SYSTEM.PRCR.WORD = portLOCK_KEY;
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341 /* Interrupt on compare match. */
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342 CMT0.CMCR.BIT.CMIE = 1;
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344 /* Set the compare match value. */
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345 CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
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347 /* Divide the PCLK. */
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348 #if portCLOCK_DIVISOR == 512
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350 CMT0.CMCR.BIT.CKS = 3;
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352 #elif portCLOCK_DIVISOR == 128
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354 CMT0.CMCR.BIT.CKS = 2;
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356 #elif portCLOCK_DIVISOR == 32
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358 CMT0.CMCR.BIT.CKS = 1;
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360 #elif portCLOCK_DIVISOR == 8
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362 CMT0.CMCR.BIT.CKS = 0;
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366 #error Invalid portCLOCK_DIVISOR setting
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371 /* Enable the interrupt... */
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372 _IEN( _CMT0_CMI0 ) = 1;
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374 /* ...and set its priority to the application defined kernel priority. */
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375 _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
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377 /* Start the timer. */
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378 CMT.CMSTR0.BIT.STR0 = 1;
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380 /*-----------------------------------------------------------*/
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382 #if configUSE_TICKLESS_IDLE == 1
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384 static void prvSleep( TickType_t xExpectedIdleTime )
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386 /* Allow the application to define some pre-sleep processing. */
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387 configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
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389 /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
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390 means the application defined code has already executed the WAIT
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392 if( xExpectedIdleTime > 0 )
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394 __wait_for_interrupt();
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397 /* Allow the application to define some post sleep processing. */
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398 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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401 #endif /* configUSE_TICKLESS_IDLE */
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402 /*-----------------------------------------------------------*/
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404 #if configUSE_TICKLESS_IDLE == 1
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406 void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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408 uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
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409 eSleepModeStatus eSleepAction;
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411 /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
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413 /* Make sure the CMT reload value does not overflow the counter. */
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414 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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416 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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419 /* Calculate the reload value required to wait xExpectedIdleTime tick
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421 ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
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422 if( ulMatchValue > ulStoppedTimerCompensation )
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424 /* Compensate for the fact that the CMT is going to be stopped
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426 ulMatchValue -= ulStoppedTimerCompensation;
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429 /* Stop the CMT momentarily. The time the CMT is stopped for is
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430 accounted for as best it can be, but using the tickless mode will
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431 inevitably result in some tiny drift of the time maintained by the
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432 kernel with respect to calendar time. */
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433 CMT.CMSTR0.BIT.STR0 = 0;
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434 while( CMT.CMSTR0.BIT.STR0 == 1 )
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436 /* Nothing to do here. */
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439 /* Critical section using the global interrupt bit as the i bit is
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440 automatically reset by the WAIT instruction. */
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441 __disable_interrupt();
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443 /* The tick flag is set to false before sleeping. If it is true when
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444 sleep mode is exited then sleep mode was probably exited because the
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445 tick was suppressed for the entire xExpectedIdleTime period. */
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446 ulTickFlag = pdFALSE;
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448 /* If a context switch is pending then abandon the low power entry as
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449 the context switch might have been pended by an external interrupt that
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450 requires processing. */
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451 eSleepAction = eTaskConfirmSleepModeStatus();
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452 if( eSleepAction == eAbortSleep )
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454 /* Restart tick. */
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455 CMT.CMSTR0.BIT.STR0 = 1;
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456 __enable_interrupt();
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458 else if( eSleepAction == eNoTasksWaitingTimeout )
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460 /* Protection off. */
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461 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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463 /* Ready for software standby with all clocks stopped. */
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464 SYSTEM.SBYCR.BIT.SSBY = 1;
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466 /* Protection on. */
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467 SYSTEM.PRCR.WORD = portLOCK_KEY;
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469 /* Sleep until something happens. Calling prvSleep() will
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470 automatically reset the i bit in the PSW. */
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471 prvSleep( xExpectedIdleTime );
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473 /* Restart the CMT. */
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474 CMT.CMSTR0.BIT.STR0 = 1;
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478 /* Protection off. */
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479 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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481 /* Ready for deep sleep mode. */
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482 SYSTEM.MSTPCRC.BIT.DSLPE = 1;
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483 SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
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484 SYSTEM.SBYCR.BIT.SSBY = 0;
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486 /* Protection on. */
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487 SYSTEM.PRCR.WORD = portLOCK_KEY;
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489 /* Adjust the match value to take into account that the current
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490 time slice is already partially complete. */
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491 ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
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492 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
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494 /* Restart the CMT to count up to the new match value. */
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496 CMT.CMSTR0.BIT.STR0 = 1;
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498 /* Sleep until something happens. Calling prvSleep() will
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499 automatically reset the i bit in the PSW. */
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500 prvSleep( xExpectedIdleTime );
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502 /* Stop CMT. Again, the time the SysTick is stopped for is
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503 accounted for as best it can be, but using the tickless mode will
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504 inevitably result in some tiny drift of the time maintained by the
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505 kernel with respect to calendar time. */
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506 CMT.CMSTR0.BIT.STR0 = 0;
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507 while( CMT.CMSTR0.BIT.STR0 == 1 )
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509 /* Nothing to do here. */
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512 ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
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514 if( ulTickFlag != pdFALSE )
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516 /* The tick interrupt has already executed, although because
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517 this function is called with the scheduler suspended the actual
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518 tick processing will not occur until after this function has
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519 exited. Reset the match value with whatever remains of this
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521 ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
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522 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
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524 /* The tick interrupt handler will already have pended the tick
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525 processing in the kernel. As the pending tick will be
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526 processed as soon as this function exits, the tick value
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527 maintained by the tick is stepped forward by one less than the
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528 time spent sleeping. The actual stepping of the tick appears
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529 later in this function. */
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530 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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534 /* Something other than the tick interrupt ended the sleep.
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535 How many complete tick periods passed while the processor was
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537 ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
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539 /* The match value is set to whatever fraction of a single tick
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541 ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
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542 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
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545 /* Restart the CMT so it runs up to the match value. The match value
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546 will get set to the value required to generate exactly one tick period
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547 the next time the CMT interrupt executes. */
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549 CMT.CMSTR0.BIT.STR0 = 1;
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551 /* Wind the tick forward by the number of tick periods that the CPU
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552 remained in a low power state. */
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553 vTaskStepTick( ulCompleteTickPeriods );
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557 #endif /* configUSE_TICKLESS_IDLE */
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